Cypress Semiconductor CY7C1350-80AC, CY7C1350-143AC, CY7C1350-133AC, CY7C1350-100AC Datasheet

128Kx36 Pipelin ed SRAM with NoBL™ Arch itecture

CY7C1350

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999

Features

• Pin compatible and f unctionally equivalent to ZBT™ de­vices IDT71V546, MT55L128L36P, and MCM63Z736

• Supports 143-MHz bus operations wi th zero wait states

—D ata is transferre d on every clock

• Internally self-timed output buff er control to eliminate
the need to use OE

• Fully registered (inputs and outputs) for pipelined
operation

• Byte Write capabil it y

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

—4.0 ns (for 143-MHz devi ce)
—4.2 ns (for 133-MHz devi ce)
—5.0 ns (for 100-MHz devi ce)
—7.0 ns (for 80-MHz devi ce)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Asynchr onous output enable

• JEDEC-standard 100 TQFP package

• Burst Capability — linear or interleaved burst order

• Low standby power (17.325 mW max.)

Functional Description

The CY7C1350 is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350 is equipped with t he adv anc ed No
Bus Latency™ (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramaticall y improves the throughput
of the SRAM, especially in systems that require frequent
Write/Read transitions. The CY7C1350 is pin/functionally
compatible to ZBT™ SRAMs IDT71V546, MT55L128L36P,
and MCM63Z736.

All synchronous input s pass through i nput regist er s controll ed
by the rising edge of the clock. All data outputs pass through
output regi sters control led by the ri sing edge of the clock. The
clock input is qualified by the Cl ock Enable (CEN

) signal, which
when deasserted suspends operation and extends the previ­ous clock cycle. Maximum access delay from the clock rise is

4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select

(BWS

[3:0]

) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

1

, CE2, CE3) and an

asynchronous Output Enable (OE

) provide for easy bank se­lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

.

NoBLand No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.

CLK

A

[16:0]

CEN

WE

BWS

[3:0]

CE

1

CE

CE

2

OE

OOUTPUT

128Kx36

MEMORY

ARRAY

CLK

Logic Block Diagram

DQ

[31:0]

Data-In REG.

Q

D

CE

CONTROL

and WRIT E

LOGIC

3

REGISTERS

and LOGIC

ADV/LD

36

36

36

17

17

36

DP

[3:0]

MODE

Selection G uide

7C1350-143 7C1350-133 7C1350-100 7C1350-80

Maximum Access Time (ns) 4.0 4.2 5.0 7.0
Maximum Operating Curr ent (mA) Commercial 450 400 350 300
Maximum CMOS Standby Current (mA) Commercial 5 5 5 5

CY7C1350

2

Pin Configuration

A5A4A3A2A1A

0

DNU

DNU

V

SS

V

DD

DNU

A

10

A11A12A13A

14

A

16

DP1
DQ

15

DQ

14

V

DDQ

V

SS

DQ

13

DQ

12

DQ

11

DQ

10

V

SS

V

DDQ

DQ

9

DQ

8

V

SS

VDD
V

DD

DQ

7

DQ

6

V

DDQ

V

SS

DQ

5

DQ

4

DQ

3

DQ

2

V

SS

V

DDQ

DQ

1

DQ

0

DP0

DP

2

DQ

16

DQ

17

V

DDQ

V

SS

DQ

18

DQ

19

DQ

20

DQ

21

V

SS

V

DDQ

DQ

22

DQ

23

V

DDQ

V

DD

V

DD

V

SS

DQ

24

DQ

25

V

DDQ

V

SS

DQ

26

DQ

27

DQ

28

DQ

29

V

SS

V

DDQ

DQ

30

DQ

31

DP

3

A6

A7

CE

1CE2

BWS3BWS2BWS1BWS0CE3VDDV

SS

CLK

WE

CEN

OE

A8A

9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

9998979695949392919089

88

87868584838281

A

15

ADV/LD

VSS

MODE

DNU

NC

NC

CY7C1350

100-Pin TQFP

CY7C1350

3

Pin Definitions

Pin Number Name I/O Description

50−44,
81−82, 99,
100, 32−37

A

[16:0]

Input­Synchronous

Address Inputs use d to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.

96−93 BWS

[3:0]

Input­Synchronous

Byte Write Select Inputs, active LOW. Qua li fied with WE to conduct writes to the
SRAM. Sampled on the risi ng edge of CLK. BWS

0

controls DQ

[7:0]

and DP0, BWS1

controls DQ

[15:8]

and DP1, BWS2 controls DQ

[23:16]

and DP2, BWS0 controls

DQ

[31:24]

and DP3. See Write Cycle Description table for details.

88 WE Input-

Synchronous

Write Enable Inp ut, active LO W . Sampled on the rising edge of CLK if CEN is active
LOW. This signa l must be asserted LOW to initiate a write sequence.

85 ADV/LD Input-

Synchronous

Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advance d. When LOW , a new address can be loaded into the de vice f or an access.
After being deselected, ADV/ LD

should be driven LO W in order to load a new

address.

89 CLK Input-Clock Clock input . Used to capture all synchron ous inputs to the dev ice. CLK is qual ified

with CEN

. CLK is only recogniz ed if CEN is active L OW.

98 CE

1

Input­Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

2

, and CE3 to select/deselect the device.

97 CE

2

Input­Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE

1

and CE3 to select/deselect the device.

92 CE

3

Input­Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

1

and CE2 to select/deselect the device .

86 OE Input-

Asynchronous

Output Enabl e, acti ve LO W . Combin ed with the s ynchronous l ogic bl ock insi de the
device t o c ontrol t he di rect ion of the I /O p ins. When LO W , t he I/ O pins ar e all o wed
to behave as outputs. When deasserted HIGH, I /O pins are three- stated, and act
as input data pins. OE

is masked during the data portion of a write sequence,
during the first clock wh en emerging fr om a deselecte d state, when the de vice has
been deselected.

87 CEN Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog­nized by the SRAM. When deas serted HIGH the Clock signal is masked. Since
deasserting CEN

does not deselect the device, CEN can be used to extend the

previous cycle when required.

29−28,
25−22,
19−18,
13−12, 9–6,
3–2, 79−78,
75–72,
69−68, 63−62
59−56, 53−52

DQ

[31:0]

I/O­Synchronous

Bidirectional Data I/O line s. As inputs, they feed into an on-chip data register that
is triggered by t he rising edge of CLK. As output s, the y deliv er the data conta ined
in the memory location specified by A

[16:0]

during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE

and the internal control

logic. When OE

is asserted LOW, the pins can behave as outputs . Wh en HIGH,

DQ

[31:0]

are placed in a three-st ate condition. The outputs are automatically
three-stated d uring the data po rtion of a write sequence, during the firs t clock when
emerging from a de select ed st ate , and when the device is dese lecte d, regar dless
of the state of OE

.

30, 1, 80 51 DP

[3:0]

I/O­Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are ident ical to
DQ

[31:0]

. During write s equen ces , DP0 is controlled b y BWS0, DP1 is controlled by
BWS

1

, DP2 is control l e d by BWS2, and DP3 is controlled by BWS3.

31 MODE Input Strap pin Mode Input. Selec ts the burst order of the de vice. Tied HIGH select s the interleave d

burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floati ng MODE will default HIGH, to an inter­leaved burst order.

15, 16, 41, 65,
66, 91

V

DD

Power Supply Power suppl y i nputs to t he core of the de vice . Sho uld be conn ected t o 3.3V po we r

supply.

4, 11, 14, 20,
27, 54, 61, 70,
77

V

DDQ

I/O Power
Supply

Po wer supply for th e I/O circuitry. Should be connect ed to a 3.3V power supply.

CY7C1350

4

Introduction

Functional Overview

The CY7C1350 is a synchronous-pipelined Burst SRAM de­signed specifically to eliminate wait states during Write/Read
transitions. All synchronous inputs pass through input regis­ters contr olled by th e risin g edge of the c loc k. The cl oc k signal
is qualifie d with the Cl oc k Enab l e input signal (CEN

). If CEN is
HIGH, the clo ck si gnal i s n ot reco gnize d and all i nternal states
are maintained. All synchronous operations are qualified with
CEN

. All data ou tput s pass th rough out put r egist ers contr olle d
by the rising edge of the clock. Maximum access delay from
the clock rise (t

CO

) is 4.0 ns (143-MHz de vice).

Accesses can be initiated by asserting all three Chip Enables
(CE

1

, CE2, CE3) activ e at the rising edge of the clock. If Clock
Enable (CEN

) is active LOW and AD V/ LD is asserted LOW , the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta­tus of the Write Enabl e (WE

). BWS

[3:0]

can be used to conduct

byte write operat ions.
Write operations are qualified by the Write Enable (WE

). All
writes are simpl ifi ed wit h on- chip sy nchr onou s self- tim ed write
circuitry.

Three synchronous Chip Enables (CE

1

, CE2, CE3) and an

asynchronous Output Enable (OE

) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the device has been de-

selected in order to load a ne w addr ess f or the ne x t operat ion.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN

is asserted LOW, ( 2) CE1, CE2,

and CE

3

are ALL asserted active, (3) the Write Enable input

signal WE

is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs (A

0−A16

)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 4.0 ns (143 MHz device) provided OE

is active LOW.
After the first clock of the read access the output buffers are
controlled by OE

and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/De select) can be initia ted. Desel ecting the de vic e
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.

Burst Read Accesses

The CY7C1350 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Acce ss section abov e.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD

will increment the internal bu rst counter regardless of

the state of chip enables inputs or WE

. WE is latched at the
beginning of a burst cycle. Theref ore , the type of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN

is asserted LOW , (2) CE1, CE2,

and CE

3

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to A

0−A16

is loaded
into the Address Register. The write signals are latched into
the C o ntrol Logi c block.

On the subsequent clock rise the data lines are automatically
three-stated r egardless of the s tate of the OE

input signal. This

allows the external logic to present the data on DQ

[31:0]

and

DP

[3:0]

. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ

[31:0]

and

DP

[3:0]

(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.

The data written during the Write operation is controlled by
BWS

[3:0]

signals. The CY7C1350 provides byte write capabil­ity that is described in the Write Cycle Description table. As­serting the Write Enable input (WE

) with the selected Byte

Write Select ( BWS

[3:0]

) input will sele ctively wr ite to on ly the
desired byte s. Bytes not selected during a byt e write opera tion
will remain unal tered. A Synchronous self-timed write mecha­nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim­ple byte write operations.

Because the CY7C1350 is a common I/O device, data should
not be driven into t he device while t he outputs are active. The
Output Enable ( OE

) can be deasserted HIGH before present-

ing data to the DQ

[31:0]

and DP

[3:0]

inputs. Doing so will

three-state the out put driver s . As a safe ty precau tion, DQ

[31:0]

and DP

[3:0]

are automati cally three- stat ed during t he data por-

tion of a write cycle, regardless of the state of OE

.

5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90

V

SS

Ground Ground for the device. Should be connected to ground of t he system.

83, 84 NC - No connects. Reserved for address input s f or d epth e xp ansion. Pin 83 a nd 84 wi ll

be used for 256K and 512K dept hs respectivel y.

38, 39, 42, 43 DNU - Do Not Use pins. These pins should be left floating or tied to VSS.

Pin Definitions

(continued)

Pin Number Name I/O Description