Cypress Semiconductor CY7C1345G Specification Sheet

CY7C1345G

4-Mbit (128K x 36) Flow Through Sync SRAM

Features

■ 128K x 36 common IO

■ 3.3V core power supply (V

■ 2.5V or 3.3V IO supply (V

■ Fast clock-to-output times ❐ 6.5 ns (133 MHz version)

■ Provide high performance 2-1-1-1 access rate

■ User selectable burst counter supporting Intel Pentium inter-

leaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ Available in Pb-free 100-Pin TQFP package, Pb-free and

non-Pb-free 119-Ball BGA package

■ ZZ Sleep Mode option

DD

DDQ

)

Functional Description

The CY7C1345G is a 128K x 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE expansion Chip Enables (CE (ADSC

, ADSP, Global Write (GW Enable (OE

) and the ZZ pin.

ADV), Write Enables (BW

and

). Asynchronous inputs include the Output

and CE3), Burst Control inputs

2

,

x

The CY7C1345G enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP

) inputs.

(ADSC

) or the cache Controller Address Strobe

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP Strobe Controller (

) is active. Subsequent burst addresses

ADSC

are internally generated as controlled by the Advance pin (ADV The CY7C1345G operates from a +3.3V core power supply

while all outputs operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

), depth

1

and BWE

) or Address

), and

).

Selection Guide

Parameter 133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns

Maximum Operating Current 225 205 mA

Maximum Standby Current 40 40 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05517 Rev. *E Revised July 15, 2007

Logic Block Diagram

CY7C1345G

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BWE

GW

CE1

CE2

CE3

ADDRESS REGISTER

BURST

COUNTER

AND LOGIC

CLR

D

DQ

,

D

C

B

A

DQP

BYTE

WRITE REGISTER

DQ

C

DQP

,

BYTE

WRITE REGISTER

B

DQP

DQ

,

BYTE

WRITE REGISTER

DQ

A

DQP

,

BYTE

WRITE REGISTER

ENABLE

REGISTER

C

B

A

[1:0]

A

Q1

Q0

DQ

DQP

D

,

D

BYTE

WRITE REGISTER

DQ

C

DQP

C

,

BYTE

WRITE REGISTER

B

DQP

DQ

,

BYTE

WRITE REGISTER

A

DQP

DQ

,

BYTE

WRITE REGISTER

MEMORY

B

A

ARRAY

SENSE AMPS

OUTPUT BUFFERS

INPUT

REGISTERS

DQP

DQ s

A

B

C

D

OE

ZZ

SLEEP

CONTROL

Document Number: 38-05517 Rev. *E Page 2 of 20

Pin Configurations

CY7C1345G

100-Pin TQFP Pinout

BYTE C

BYTE D

DQP

DQ

V

DDQ

V

SSQ

DQ

V

SSQ

V

DDQ

DQ

V

NC

V

DQ

V

DDQ

V

SSQ

DQ

V

SSQ

V

DDQ

DQ

DQP

NC

DD

SS

A

100

1

C

2

C

3

C

CE

99989796959493929190898887868584838281

2BWDBWC

1

A

4

5

6

C

7

C

8

C

9

C

10

11

12

C

13

C

14

15

16

17

18

D

19

D

20

21

22

D

23

D

24

D

25

D

26

27

28

D

29

D

30

D

3

A

CE

BWBBW

VDDV

CY7C1345G

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQP

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

SS

NC

V

DD

ZZ

DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

DQPA

B

BYTE B

BYTE A

31323334353637383940414243444546474849

AAAAA1A

MODE

Document Number: 38-05517 Rev. *E Page 3 of 20

50

0

NC/72M

SS

V

NC/36M

DD

V

NC/18M

NC/9M

AAAAA

A

Pin Configurations (continued)

CY7C1345G

119-Ball BGA Pinout

A

B

C

D

E

F

G

H

J

K

L

M N

P

R

T

U

V

DDQ

NC/288M

NC/144M

DQ

C

DQ

C

V

DDQ

DQ

C

DQ

C

V

DDQ

DQ

D

DQ

D

V

DDQ

DQ

D

DQ

D

NC

V

DDQ

2

AA AA

CE

2

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

A

345671

ADSP

A

AA

V

SS

V

SS

V

SS

BW

C

V

SS

NC V

V

SS

BW

D

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

GW

DD

CLK

NC

BWE

A1

A0

V

DD

A

V

BW

V

NC

V

BW

V

NC

SS

B

SS

A

SS

AAA

NCNCNCNC

DQP

NC/36MNC/72M

CE

DQ

V

DQ

NC

A

3

AA

B

DD

A

V

DDQ

NC/576M

NC/1G

DQ

B

DQ

B

V

DDQ

DQ

B

DQ

B

V

DDQ

DQ

A

DQ

A

V

DDQ

DQ

A

DQ

A

NC

ZZ

V

DDQ

Document Number: 38-05517 Rev. *E Page 4 of 20

CY7C1345G

Pin Definitions

Name IO Description

A0, A1, A Input

Synchronous

BW

A, BWB

BWC, BW

D

Input

Synchronous

GW Input

Synchronous

BWE

Input

Synchronous

CLK Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

CE

1

Input

Synchronous

Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A the two-bit counter.

[1:0]

feed

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted LOW to conduct a byte write.

counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

2

when a new external address is loaded.

CE

2

3

Input

Synchronous

Input

Synchronous

OE Input

Asynchronous

ADV

Input

Synchronous

ADSP Input

Synchronous

ADSC

Input

Synchronous

ZZ Input

Asynchronous

DQs DQP DQP

V

DD

V

SS

V

DDQ

V

SSQ

A, C,

DQP

B

D

IO

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

IO Power

Supply

IO Ground Ground for the IO circuitry.

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select or deselect the device. CE2 is sampled only when a new external address is

CE

1

loaded.

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE2 to select or deselect the device. CE3 is sampled only when a new external address is

1

loaded.

Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A also loaded into the burst counter. When ADSP nized. ASDP

is ignored when CE1 is deasserted HIGH.

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

nized.

ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin has an internal pull down.

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by DQP

are placed in a tri-state condition.

[A:D]

. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and

OE

Power supply for the IO circuitry.

Document Number: 38-05517 Rev. *E Page 5 of 20

Pin Definitions (continued)

Name IO Description

MODE Input

Static

NC No Connects. Not Internally connected to the die.

NC/9M,

– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/18M, NC/36M NC/72M, NC/144M, NC/288M, NC/576M, NC/1G

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up.

NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the die.

CY7C1345G

or left

DD

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 6.5 ns (133 MHz device).

The CY7C1345G supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable and is determined by sampling the MODE input. Accesses are initiated with either the Processor Address Strobe (ADSP Strobe (ADSC

). Address advancement through the burst sequence is controlled by the ADV around burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Enable (BWE

) and Byte Write Select (BW

Enable (GW

) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE asynchronous Output Enable (OE selection and output tri-state control. ADSP HIGH.

Single Read Accesses

A single read access is initiated when the following conditions are satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active.

1

2. ADSP

The address presented to the address inputs is latched into the address register and the burst counter or control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to t

or ADSC is asserted LOW (if the access is initiated by

ADSC

, the write inputs are deasserted during this first cycle).

after clock rise. ADSP is ignored if CE1 is HIGH.

CDV

) or the Controller Address

input. A two-bit on-chip wrap

) inputs. A Global Write

[A:D]

, CE2, and CE3) and an

1

) provide for easy bank

is ignored if CE1 is

Single Write Accesses Initiated by ADSP

Single write access is initiated when the following conditions are satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active

1

2. ADSP

is asserted LOW.

The addresses presented are loaded into the address register and the burst inputs (GW

, BWE, and BWx) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. During byte writes, BW DQ

C

write. Since this is a common IO device, the asynchronous OE

controls DQA and BWB controls DQB, BWC controls

A

, and BWD controls DQD. All IOs are tri-stated during a byte

input signal is deasserted and the IOs are tri-stated prior to the presentation of data to DQ lines are tri-stated once a write cycle is detected, regardless of the state of OE

.

. As a safety precaution, the data

s

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active.

1

2. ADSC

3. ADSP

4. The write input signals (GW

The addresses presented are loaded into the address register and the burst counter or control logic and delivered to the memory core. The information presented to DQ into the specified address location. Byte writes are allowed. During byte writes, BW controls DQC, and BWD controls DQD. All IOs and even a byte write are tri-stated when a write is detected. Since this is a common IO device, the asynchronous OE deasserted and the IOs are tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless

is asserted LOW.

is deasserted HIGH

access. ADSC

is ignored if ADSP is active LOW.

, BWE, and BWx) indicate a write

[D:A]

controls DQA, BWB controls DQB, BW

A

input signal is

of the state of OE

is written

.

C

Document Number: 38-05517 Rev. *E Page 6 of 20

CY7C1345G

Burst Sequences

The CY7C1345G provides an on-chip two-bit wrap around burst counter inside the SRAM. The burst counter is fed by A follows either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence.

Table 1. Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1, A0

DD

Second

Address

A1, A0

)

Third

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

[1:0]

Fourth

A1, A0

and

Table 2. Linear Burst Address Table (MODE = GND)

First

Address

A

1, A0

Second

Address

A

1, A0

Third

Address

A

1, A0

Fourth

Address

A

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. In this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device is deselected prior to entering the sleep mode. CE ADSC

must remain inactive for the duration of t

ZZ input returns LOW.

s, ADSP, and

ZZREC

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 40 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

1, A0

after the

ns

Document Number: 38-05517 Rev. *E Page 7 of 20

CY7C1345G

Truth Table

The truth table for CY7C1345G follows.

Cycle Description

Address

Deselected Cycle, Power down

Sleep Mode, Power down None X X X H X XXXXXTri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend BurstCurrentXXXLH HHHHL-HTri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend BurstCurrentHXXL X HHHHL-HTri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

[1, 2, 3, 4, 5]

Used

CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

None H X X L X L X X X L-H Tri-State

None LLXLL XXXXL-HTri-State

None LXHL L XXXXL-HTri-State

None L L X L H L X X X L-H Tri-State

None X X X L H L X X X L-H Tri-State

Notes

1. X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.

2. WRITE

3. The DQ pins are controlled by the current cycle and the OE

4. The SRAM always initiates a read cycle when ADSP

5. OE

= L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,

BW

, BWC, BWD), BWE, GW = H.

B

the ADSP the remainder of the write cycle.

or when the device is deselected, and all data bits behave as output when

or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

Document Number: 38-05517 Rev. *E Page 8 of 20

signal. OE is asynchronous and is not sampled with the clock.

is asserted, regardless of the state of GW, BWE, or BW

OE

is active (LOW).

. Writes may occur only on subsequent clocks after

[A: D]

inactive

CY7C1345G

Truth Table for Read or Write

The partial truth table for read or write follows.

Function GW BWE BW

Read HHXXXX

Read H L H H H H

Write Byte (A, DQP

Write Byte (B, DQP

Write Bytes (B, A, DQP

)HLHHHL

A

)HLHHLH

B

, DQPB)HLHHLL

A

Write Byte (C, DQPC)HLHLHH

Write Bytes (C, A, DQP

Write Bytes (C, B, DQP

Write Bytes (C, B, A, DQP

Write Byte (D, DQP

Write Bytes (D, A, DQP

, DQPA)HLHLHL

C

, DQPB)HLHLLH

C

, DQPB, DQPA)HLHLLL

C

) HL LHHH

D

, DQPA)HLLHHL

D

Write Bytes (D, B, DQPD, DQPA)HLLHLH

Write Bytes (D, B, A, DQP

Write Bytes (D, B, DQP

, DQPB, DQPA)HLLHLL

D

, DQPB)HLLLHH

D

Write Bytes (D, B, A, DQPD, DQPC, DQPA)HLLLHL

Write Bytes (D, C, A, DQP

, DQPB, DQPA)HLLLLH

D

Write All Bytes HLLLLL

Write All Bytes L XXXXX

[1, 6]

D

BW

C

BW

B

BW

A

Note

6. This table is only a partial listing of the byte write combinations. Any combination of BW

Document Number: 38-05517 Rev. *E Page 9 of 20

is valid. Appropriate write is done based on the active byte write.

x

CY7C1345G

Maximum Ratings

Exceeding the maximum ratings may shorten the battery life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V

DC Voltage Applied to Outputs

in tri-state.............................................–0.5V to V

Electrical Characteristics

Over the Operating Range

Relative to GND ........–0.5V to +4.6V

DD

Relative to GND.......–0.5V to +V

DDQ

+ 0.5V

DDQ

[7, 8]

DD

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(MIL-STD-883, Method 3015) .................................. >2001V

Latch up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V

Industrial –40°C to +85°C

Ambient

Temperature

V

DD

−5%/+10%

+ 0.5V

DD

V

DDQ

2.5V –5% to V

Parameter Description Test Conditions Min Max Unit

V

DD

DDQ

OH

OL

IH

IL

Power Supply Voltage 3.135 3.6 V

IO Supply Voltage 2.375 V

Output HIGH Voltage for 3.3V IO, I

for 2.5V IO, I

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

DD

Output LOW Voltage for 3.3V, IO, IOL= 8.0 mA 0.4 V

for 2.5V IO, I

= 1.0 mA 0.4 V

OL

Input HIGH Voltage for 3.3V IO 2.0 VDD + 0.3V V

Input LOW Voltage

[7]

for 2.5V IO 1.7 V

for 3.3V IO –0.3 0.8 V

+ 0.3V V

DD

for 2.5V IO –0.3 0.7 V

I

X

I

OZ

I

DD

I

SB1

I

SB2

I

SB3

I

SB4

Input Leakage Current except

GND ≤ VI ≤ V

ZZ and MODE

Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS

DD

SS

DD

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply Current V

Automatic CE Power down Current—TTL Inputs

Automatic CE Power down Current—CMOS Inputs

Automatic CE Power down Current—TTL Inputs

= Max, I

DD

f = f

MAX

= 1/t

Max VDD, Device Deselected,

≥ VIH or VIN ≤ VIL, f = f

V

IN

inputs switching

Max VDD, Device Deselected, V

≥ VDD – 0.3V or VIN ≤ 0.3V,

IN

f = 0, inputs static

Max VDD, Device Deselected, V

≥ V

IN

DDQ

0.3V, f = f

MAX

Max VDD, Device Deselected, V

≥ V

IN

f = 0, inputs static

– 0.3V or VIN ≤ 0.3V,

DD

DDQ

−55µA

–30 µA

–5 µA

30 µA

, Output Disabled –5 5 µA

DDQ

OUT

CYC

= 0 mA,

7.5 ns cycle, 133 MHz 225 mA

10 ns cycle, 100 MHz 205 mA

7.5 ns cycle, 133 MHz 90 mA

,

MAX

10 ns cycle, 100 MHz 80 mA

All speeds 40 mA

7.5 ns cycle, 133 MHz 75 mA

– 0.3V or VIN ≤

, inputs switching

10 ns cycle, 100 MHz 65 mA

All speeds 45 mA

5 µA

DD

V

Notes

7. Overshoot: V

8. T

Power up

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and V

Document Number: 38-05517 Rev. *E Page 10 of 20

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

DDQ

< V

DD.

CYC

/2).

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

C

IN

C

CLK

C

IO

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V.

V

Clock Input Capacitance 5 5 pF

Input or Output Capacitance 5 7 pF

V

DD

DDQ

= 3.3V

100 TQFP

Max

55pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Θ

JA

Thermal Resistance

Θ

JC

Thermal Resistance (Junction to Ambient)

(Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51.

AC Test Loads and Waveforms

100 TQFP

Package

30.32 34.1 °C/W

6.85 14.0 °C/W

119 BGA

Max

119 BGA Package

CY7C1345G

Unit

3.3V I/O Test Load

OUTPUT

Z

0

2.5V I/O Test Load

OUTPUT

Z

0

3.3V

= 50Ω

R

VT= 1.5V

(a) (b)

= 50Ω

= 1.25V

V

T

R

(a) (b)

= 50Ω

L

= 50Ω

L

OUTPUT

INCLUDING

JIG AND

SCOPE

2.5V

OUTPUT

INCLUDING

JIG AND

SCOPE

5pF

R = 317Ω

R = 351Ω

R = 1667Ω

R = 1538Ω

GND

V

DDQ

GND

V

DDQ

≤ 1ns

≤ 1 ns

ALL INPUT PULSES

10%

90%

ALL INPUT PULSES

90%

10%

≤ 1ns

(c)

90%

10%

≤ 1 ns

(c)

Document Number: 38-05517 Rev. *E Page 11 of 20

CY7C1345G

Switching Characteristics

Over the Operating Range

Parameter Description

t

POWER

VDD(Typical) to the first Access

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.5 4.0 ns

Clock LOW 2.5 4.0 ns

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid After CLK Rise 6.5 8.0 ns

Data Output Hold After CLK Rise 2.0 2.0 ns

Clock to Low Z

Clock to High Z

OE LOW to Output Valid 3.5 3.5 ns

OE LOW to Output Low Z

OE HIGH to Output High Z

Setup Times

[9, 10]

[11]

[12, 13, 14]

–133 –100

Unit

Min Max Min Max

11ms

00ns

3.5 3.5 ns

00ns

3.5 3.5 ns

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Address Setup Before CLK Rise 1.5 2.0 ns

ADSP, ADSC Setup Before CLK Rise 1.5 2.0 ns

ADV Setup Before CLK Rise 1.5 2.0 ns

GW, BWE, BWx Setup Before CLK Rise 1.5 2.0 ns

Data Input Setup Before CLK Rise 1.5 2.0 ns

Chip Enable Setup 1.5 2.0 ns

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

Notes

9. Timing reference level is 1.5V when V

10. Test conditions shown in (a) of Latch up Current >200 mA unless otherwise noted.

11. This part has a voltage regulator internally; t initiated.

12. t

, t

CHLZ

13. At any voltage and temperature, t

14. This parameter is sampled and not 100% tested.

CLZ,tOELZ

These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions.

Address Hold After CLK Rise 0.5 0.5 ns

ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns

GW, BWE, BWx Hold After CLK Rise 0.5 0.5 ns

ADV Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.5 0.5 ns

, and t

= 3.3V and is 1.25V when V

DDQ

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is

POWER

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady state voltage.

OEHZ

is less than t

OEHZ

OELZ

and t

CHZ

= 2.5V.

DDQ

is less than t

to eliminate bus contention between SRAMs when sharing the same data bus.

CLZ

Document Number: 38-05517 Rev. *E Page 12 of 20

Timing Diagrams

Figure 1 shows the read cycle timing.

t

CYC

CY7C1345G

[15]

Figure 1. Read Cycle Timing

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

ADV

Data Out (Q)

[A:B]

CE

OE

t

ADS

t

High-Z

AS

CES

A1

t

ADH

t

AH

t

CLZ

CH

CEH

t

CL

t

WES

OEV

CDV

Single READ

t

WEH

t

Q(A1)

OEHZ

t

ADS

A2

t

ADH

t

OELZ

t

ADVS

Q(A2)

t

ADVH

t

CDV

t

DOH

Q(A2 + 1)

DON’T CARE

ADV suspends burst

Q(A2 + 2)

BURST

READ

UNDEFINED

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around to its initial state

Deselect Cycle

t

CHZ

Q(A2 + 2)

Note:

15. On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document Number: 38-05517 Rev. *E Page 13 of 20

Timing Diagrams (continued)

D

Figure 2 shows the write cycle timing.

t

CYC

CY7C1345G

[15, 16]

Figure 2. Write Cycle Timing

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

[A:B]

GW

CE

ADV

OE

t

CL

CH

t

ADH

ADS

t

ADH

ADS

t

AH

AS

A1

Byte write signals are ignored for rst cycle when ADSP initiates burst

t

CEH

CES

t

DS

A2 A3

t

DH

ADSC extends burst

t

WEH

WES

ADV suspends burst

t

ADH

ADS

t

WEH

WES

t

ADVH

ADVS

Data in (D)

ata Out (Q)

Note:

16.

Full width write can be initiated by either GW

Document Number: 38-05517 Rev. *E Page 14 of 20

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

LOW; or by GW HIGH, BWE LOW and BWx LOW.

D(A2)

D(A2 + 1)

DON’T CARE UNDEFINED

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

Extended BURST WRITE

D(A3 + 2)

Timing Diagrams (continued)

Figure 3 shows the read and write timing.

t

CYC

CY7C1345G

[16, 17, 18]

Figure 3. Read/Write Timing

CLK

ADSP

ADSC

ADDRESS

BWE, BW

[A:B]

ADV

Data In (D)

Data Out (Q)

t

CL

CH

t

ADH

ADS

t

AH

AS

A1 A5 A6

A2

t

CEH

CES

A3 A4

t

WEH

WES

CE

OE

t

DH

High-Z

Q(A1)

Back-to-Back READs

Q(A2)

t

OEHZ

DS

D(A3)

Single WRITE

t

OELZ

t

CDV

Q(A4) Q(A4+1)

BURST READ

Q(A4+2)

Q(A4+3)

DON’T CARE UNDEFINED

D(A5) D(A6)

Back-to-Back

WRITEs

Notes:

17. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP

18. GW

is HIGH.

Document Number: 38-05517 Rev. *E Page 15 of 20

or ADSC.

Timing Diagrams (continued)

Figure 4

shows the ZZ mode timing.

CLK

[19, 20]

CY7C1345G

Figure 4. ZZ Mode Timing

t

ZZ

t

ZZREC

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

19. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device.

20. DQs are in high-Z when exiting ZZ sleep mode.

Document Number: 38-05517 Rev. *E Page 16 of 20

CY7C1345G

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

133 CY7C1345G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1345G-133BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1345G-133BGXC 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1345G-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1345G-133BGI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1345G-133BGXI 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

100 CY7C1345G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1345G-100BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1345G-100BGXC 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1345G-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1345G-100BGI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1345G-100BGXI 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

Package

Diagram

Part and Package Type

Operating

Range

Document Number: 38-05517 Rev. *E Page 17 of 20

Package Diagrams

R 0.08 MIN.

0.20 MAX.

0.25

GAUGE PLANE

0°-7°

0.60±0.15

1.00 REF.

Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

1

30

0° MIN.

100

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

DETAIL

A

81

0513

80

0.30±0.08

0.65 TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

12°±1°

(8X)

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

CY7C1345G

1.40±0.05

SEE DETAIL

0.20 MAX.

1.60 MAX.

0.10

51-85050-*B

A

Document Number: 38-05517 Rev. *E Page 18 of 20

Package Diagrams (continued)

A1 CORNER

2165437

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115

Ø1.00(3X) REF.

1.27

19.50

20.32

22.00±0.20

10.16

CY7C1345G

Ø0.05 M C

Ø0.25MCAB

Ø0.75±0.15(119X)

2143657

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

0.70 REF.

12.00

30° TYP.

0.90±0.05

0.25 C

SEATING PLANE

C

0.56

2.40 MAX.

0.15 C

60±0.10

A

B

0.15(4X)

3.81

7.62

14.00±0.20

1.27

51-85115-*B

Document Number: 38-05517 Rev. *E Page 19 of 20

Document History Page

Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM Document Number: 38-05517

REV. ECN NO. Issue Date

** 224365

*A 278513

*B 333626

*C 418633

*D 480124

*E 1274724

See ECN

Orig. of

Change

RKF New datasheet

VBL Deleted 66 MHz

Changed TQFP package to Pb-free TQFP in Ordering Information section Added BG Pb-free package

SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA

Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified V Replaced ‘Snooze’ with ‘Sleep’

OL, VOH

test conditions

Removed 117 MHz speed bin Replaced TBDs for Θ tance table

and ΘJC to their respective values on the Thermal Resis-

JA

Removed comment on the availability of BG Pb-free package Updated the Ordering Information by shading and unshading MPNs as per availability

RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified test condition from V Modified test condition from V Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information

VKN Added the Maximum Rating for Supply Voltage on V

Updated the Ordering Information table.

VKN Corrected Write Cycle timing waveform

Description of Change

< V

IH DDQ

DD to VIH

< V

DD

to V

< V

DDQ

DD.

< V

CY7C1345G

DD

Relative to GND

DDQ

© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-05517 Rev. *E Revised July 15, 2007 Page 20 of 20

Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the tr ademarks of their respective holders.

Cypress Semiconductor CY7C1345G Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual