Cypress Semiconductor CY7C1345-117AC, CY7C1345-100AC Datasheet

128K x 36 Synchronous Flow-Through 3.3V Cache RAM

CY7C1345

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 8, 2000

Features

• Supports 117-MHz m icroprocessor cac he systems with
zero wait states

• 128K by 36 common I/O

• Fast clock-to-output times

—7.5 ns (117-MHz version)

• T wo-bit wrap-aroun d counter supporting either
interleaved or linear burst sequence

• Separate pro cessor and contro ller address strobe s pro­vide direct interface with the processor and extern al
cache controller

• Synchronous self-timed write

• Asynchr onous output enable

• Supports 3.3V & 2.5V I/O levels

• JEDEC-standard pinout

• 100-pin TQFP packag ing

• ZZ “sleep” mode

Functional Description

The CY7C1345 is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap­tures the first address in a burst and increments the address
automatically for the rest of the burst access.

The CY7C1345 allows either interleaved or linear burst se­quences, sele cted by the MODE input pin. A HIGH selects an
interleaved burst sequence, whi le a LOW s elects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP

) or the cache Controller Address

Strobe (ADSC

) inputs. Address advancement is controlled by

the address advancement (ADV

) input.

A synchronous sel f-t imed wri te me chanism i s pro vided to sim ­plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.

Selection G uide

7C1345-117 7C1345-100 7C1345-90 7C1345-50

Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operat ing Current (mA) 350 325 300 250
Maximum Standb y Curr ent (mA) 10.0 10.0 10.0 10.0

Pentium is a registered trademark of Intel Corporation.

CLK
ADV

ADSC

A

[16:0]

GW

BWE

BWS

0

CE

1

CE

3

CE

2

OE

ZZ

BURST

COUNTER

DQ[31:24],DP3

BYTEWRITE
REGISTERS

ADDRESS

REGISTER

D

Q

INPUT

REGISTERS

128K X 36

MEMORY

ARRAY

CLK

Q

0

Q

1

Q

D

CE

CE

CLR

SLEEP

CONTROL

DQ[23:16],DP2

BYTEWRITE
REGISTERS

D Q

DQ

DQ[15:8],DP1

BYTEWRITE
REGISTERS

DQ[7:0],DP0
BYTEWRITE

REGISTERS

D Q

ENABLE

REGISTER

D

Q

CE

CLK

36 36

17

15

15

17

(A0,A1)

2

MODE

ADSP

Logic Block Diagram

DQ

[31:0]

BWS

1

BWS

2

BWS

3

DP

[3:0]

CY7C1345

2

Pin Configuration

100-Lead TQFP

A5A4A3A2A1A

0

DNU

DNU

V

SS

V

DD

DNU

A

10A11A12A13A14A16

DP

1

DQ

14

V

DDQ

V

SSQ

DQ

13

DQ

12

DQ

11

DQ

10

V

SSQ

V

DDQ

DQ

9

DQ

8

V

SS

NC
V

DD

DQ

7

DQ

6

V

DDQ

V

SSQ

DQ

5

DQ

4

DQ

3

DQ

2

V

SSQ

V

DDQ

DQ

1

DQ

0

DP0

DP

2

DQ

16

DQ

17

V

DDQ

V

SSQ

DQ

18

DQ

19

DQ

20

DQ

21

V

SSQ

V

DDQ

DQ

22

DQ

23

V

SSQ

V

DD

NC
V

SS

DQ

24

DQ

25

V

DDQ

V

SSQ

DQ

26

DQ

27

DQ

28

DQ

29

V

SSQ

V

DDQ

DQ

30

DQ

31

DP

3

A6A7CE1CE2BWS3BWS2BWS1BWS0CE3VDDVSSCLKGWBWE

OE

ADSP

A8A

9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99989796959493929190898887868584838281

BYTE0

BYTE2

A

15

ADV

ADSC

ZZ

MODE

DNU

BYTE1

DQ

15

BYTE3

V

SS

100-Pin TQFP

CY7C1345

CY7C1345

3

Pin Descriptions

Pin Number Name I/O Description

85 ADSC Input-

Synchronous

Address Strobe f rom Controller , sampl ed on the rising edge of CLK. When asserted
LOW , A

[15:0]

is capture d in the addr ess register s. A

[1:0]

are also load ed into th e burst

counter. When ADSP

and ADSC are bot h asserted, only ADSP is recognized.

84 ADSP Input-

Synchronous

Address Strobe from Proce ssor , sampl ed on the rising edg e of CLK. Whe n asserted
LOW , A

[15:0]

is capture d in the addr ess register s. A

[1:0]

are also load ed into th e burst

counter . When ADSP

and ADSC are both asserted, onl y ADSP is recogniz ed. ASDP

is ignored when CE

1

is deasserted HIGH.

36, 37 A

[1:0]

Input­Synchronous

A1, A0 Address Input s. These inputs fe ed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.

49 −44,
81–82,
99–100,
32–35

A

[16:2]

Input­Synchronous

Address Inputs used in conjunction with A

[1:0]

to select one of the 64K address

locations. Sample d at t he ris ing edg e of t he CLK, i f CE

1, CE2,

and CE3 are sampled

active, and ADSP

or ADSC is active LOW.

96–93 BW

[3:0]

Input­Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BW

0

controls DQ

[7:0]

and DP0, BW1 controls DQ

[15:8]

and DP

1

, BW2 controls DQ

[23:16]

and DP2, and BW3 controls DQ

[31:24]

and DP3. See

Write Cycle Description table for further details.

83 ADV Input-

Synchronous

Advance Input, used to adv anc e the on-ch ip addres s counter. When LOW the inter­nal burst counter is advanced in a burst sequence. The burst sequence is selected
using the MODE input.

87 BWE Input-

Synchronous

Byte Write Enable I nput, active LO W . Sampled on t he rising edge of CLK. This s ignal
must be asserted LOW to cond uct a byte write.

88 GW Input-

Synchronous

Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to cond uct a g lob al wri te, ind epende nt of the s tate of BW E

and BW

[3:0]

. Global

writes override byte writes.
89 CLK Input-Clock Clock Input. Used to capture all synchronous i nputs to the device.
98 CE

1

Input­Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

2

and CE3 to select/deselect the device. CE1 gates ADSP.

97 CE

2

Input­Synchronous

Chip Enable 2 Input, act ive HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

1

and CE3 to select/deselect the device.

92 CE

3

Input­Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

1

and CE2 to select/deselect the device.

86 OE Input-

Asynchronous

Output Enable, asynchronous input, active LO W. Controls the directi on of the I/O

pins. When LO W, the I/O pins beha ve a s out puts . When deass erted HIGH, I/O pi ns

are three-stated, and act as input data pins.
64 ZZ Input-

Asynchronous

Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a

low-power standby mode in which all other i nputs are ignored, bu t th e data i n the

memory array is mai ntained.Lea ving ZZ float ing or NC will def ault the devi ce into an

active sta te. ZZ pin has an internal pull-down.
31 MODE - Mode Input. Selects t he burs t order of the de vice. Tied HIGH select s the interlea ved

burst order. Pulled LOW selects the linear burst order. When left floating or NC,

defaults to in terl eaved burst order. Mode pin has an internal pull-up.
30–28,

25–22,
19–18,
13–12, 9–6,
3–1, 80–78,
75–72,
69–68,
63–62,
59–56,
53–51

DQ

[31:0]

,

DP

[3:0]

I/O­Synchronous

Bidirectional Data I/O li nes . As inp uts, they feed into an on -chip da ta r egist er that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in

the memory location specified by A

[16:0]

during the previous clock rise of the rea d

cycle. The direction of the pins is controlled by OE

in conjunction with the int ernal

control logic. When OE

is asserted LOW, the pins behave as outp uts. When HIGH,

DQ

[31:0]

and DP

[3:0]

are placed in a three-state condit ion. The outputs are automat-

ically three-s tat ed when a Write cycle is detected .

15, 41, 65, 91V

DD

Po wer Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

CY7C1345

4

Functional Overview

All synchrono us inputs pass throu gh inp ut registe rs con trol led
by the rising edge of the clock. Maximum access delay from
the clock rise (t

CDV

) is 7.5 ns (117-MHz device).

The CY7C1345 sup ports secondary cache in systems utilizin g
either a linear or interleaved burst sequence. The i nterleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The bur st order is user sel ectable, and is de­termined by sampling the MODE input. Accesses can be initi­ated with either the Processor Address Strobe (ADSP

) or the

Controller Address Strobe (ADSC

). Address advancement

through the burst sequence is controlled by the ADV

input. A
two-bit on -chip wraparou nd burs t counter captu res the fi rst ad­dress in a burst sequence and automatically increment s the
addr e s s for the res t of the bu rst acc ess.

Byte write operations are qualified with the Byt e Writ e Enable
(BWE

) and Byte Write Select (BW

[3:0]

) inputs. A Global Write

Enable (GW

) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro­nous self-timed wri te circuitry.

Three synchronous Chip Selects (CE

1

, CE2, CE3) and an

asynchronous Output Enable (OE

) provide for easy bank se-

lection and output three-state control. ADSP

is ignored if CE

1

is HIGH.

Single Read Accesses

A single re ad access is initiated when the following conditions
are satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all as-

serted active, and (2) ADSP

or ADSC is asserted LOW (if the

access is initiated by ADSC

, the write i nputs mus t be de assert­ed during this first cycle). The address presented to the ad­dress inputs is latc hed into the address register and the burst
counter/con trol logic and presented to the memory core . If th e
OE

input is asserted LOW , the requeste d data will be av ailab le

at the data outputs a maximum to t

CDV

after clock rise. ADSP

is ignored if CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when t he following conditions are sat­isfi ed at clock rise: (1) CE

1

, CE2, and CE3 are all asse rted

active, and (2) ADSP

is asserted LOW. The addresses pre-

sented are loaded into the address register and the burst

counter/control logi c and del ive red to the RAM cor e . The write
inputs (GW

, BWE, and BW

[3:0]

) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW

0

controls DQ

[7:0]

, BW1 controls

DQ

[15:8]

, BW2 controls DQ

[23:16]

, and BW3 controls DQ

[31:24]

.
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE

input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ

[31:0]

. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re­gardless of the state of OE

.

Single Write Accesses Initiated by ADSC

This write access is initia ted when t he f ol lowi ng con diti ons are
satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all asserted

active, (2 ) ADSC

is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the wri te input signals (GW

, BWE, and BW

[3:0]

)

indicate a write access. ADSC

is ignored if ADSP is active LOW.

The addresses pres ent ed are l oaded int o the ad dres s regi ster
and the burst counter/control logic and delivered to the RAM
core. The i nformation pres ented to DQ

[31:0]

will be wri tt en into
the specified addr ess locati on. Byte writes ar e allowed . During
byte writes, BW

0

controls DQ

[7:0]

, BW1 controls DQ

[15:8]

, BW

2

controls DQ

[23:16]

, and BWS3 controls DQ

[31:24]

. All I/O s are
three-stated when a write is det ected, e ven a b yte wri te. Since
this is a c ommon I/O de vice , the asyn chronous OE

input signal
must be deasserted and the I/Os m ust be t hree-st ated pri or to
the presentati on of da ta to DQ

[31:0]

. As a saf ety preca ution, t he
data lines are three-stated once a write cycle is detected, re­gardless of the state of OE

.

Burst Sequences

The CY7C1345 provides an on-chip 2-bit wraparound burst
counter inside t he SRAM. The burst counter is fed by A

[1:0]

,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will sele ct a l inear b u rst se quence. A HIG H on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause t he device to defaul t to a interleaved
burst sequence.

17, 40, 67, 90V

SS

Ground Ground for the I/O circu it ry of the de vice. Should be conne cted to ground of the

system.

5, 10, 14, 21,
26, 55, 60,
71, 76

V

SSQ

Ground Ground for the dev ice. Should be connected to ground of the syste m.

4, 11, 20, 27,
54, 61, 70,
77

V

DDQ

I/O Power
Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

1, 16, 30,
50–51, 66,
80

NC - No connects.

38, 39, 42, 43DNU - Do not use pins. Should be left unconnected or tied LOW.

Pin Descriptions

(continued)

Pin Number Name I/O Description

CY7C1345

5

Sleep Mode

The ZZ input pin is an asynchro nous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are req uir ed to enter into or ex it from this “sleep”
mode. While i n this mode, data integ rity is guarant eed. Access­es pending when entering the “sleep” m ode are not considered
valid nor is the completion of the operation guaranteed. The
device m ust be d esel ected p rior t o enteri ng the “sleep” mode.
CE

1

, CE2, CE3, ADSP, and ADSC must remain inactive for the

duration of t

ZZREC

after the ZZ input returns LO W. Leaving ZZ

unconnected defaults the device into an active state.

Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Table 2. Counter Implementation for a Linear Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

CCZZ

Snooze mode stand-

by current

ZZ > V

DD

− 0.2V 3 ns

t

ZZS

Device operation to ZZZZ > VDD − 0.2V 2t

CYC

ns

t

ZZREC

ZZ recovery time ZZ < 0.2V 2t

CYC

mA