Cypress Semiconductor CY7C1338G Specification Sheet

CY7C1338G

A

s

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features

• 128K x 32 common I/O

• 3.3V core power supply (V

• 2.5V or 3.3V I/O supply (V

• Fast clock-to-output times
— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package

• “ZZ” Sleep Mode option

DD

DDQ

)

)

®

Functional Description

The CY7C1338G is a 128K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati­cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC
controlled by the Address Advancement (ADV

, and BWE), and Global Write (GW). Asynchronous

[A:D]

[1]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

) or the cache Controller

) inputs. Address advancement is

) input.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV).

The CY7C1338G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Logic Block Diagram

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW
BWE

BW

C

BW

B

A

GW
CE1

CE2
CE3

OE

ZZ

SLEEP

CONTROL

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

D

BYTE

DQ

C

BYTE

DQ

B

BYTE

DQ

DQ

A

BYTE

ENABLE

REGISTER

A

[1:0]

Q1

Q0

DQ

D

BYTE

WRITE REGISTER

DQ

C

BYTE

WRITE REGISTER

DQ

B

BYTE

WRITE REGISTER

DQ

A

BYTE

WRITE REGISTER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQ

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05521 Rev. *D Revised July 5, 2006

CY7C1338G

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum Standby Current 40 40 mA

Pin Configurations

100-Pin TQFP Pinout

BYTE C

BYTE D

V
V

V
V

V
V

V
V

NC
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

V

NC

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

SS

A

100

CE

CE

99989796959493929190898887868584838281

2BWDBWC

1

A

1
2

C

3

C

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15
16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

3

A

CE

BWBBW

VDDV

CY7C1338G

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
NC

B
B

B
B
B
B

B
B

A
A

A
A
A
A

A
A

BYTE B

BYTE A

31323334353637383940414243444546474849

MODE

Document #: 38-05521 Rev. *D Page 2 of 17

AAAAA1A

0

NC/72M

NC/36M

50

SS

DD

V

V

NC/9M

NC/18M

AAAAA

A

A

Pin Configurations (continued)

A

NC/288M

B

NC/144M

C
D
E
F

G

H

J

K
L

M

N
P

R
T
U

V

DQ

V

DQ
DQ

V

DQ
DQ

V

DQ
DQ

V

DDQ

DDQ

DDQ

DDQ

NC
NC

DDQ

CY7C1338G

119-Ball BGA Pinout

2

AA AA

CE

2

C
C

C
C

D
D

D
D

NCDQ
DQ
DQ
DQ
DQ

V

DQ
DQ

DQ
DQ

NC

C
C
C
C

DD

D
D

D
D

A

345671

ADSP
A
AA

V

SS

V

SS

V

SS

BW

C

V

SS

NC V

V

SS

BW

D

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

GW

DD

CLK

NC

BWE

A1
A0

V

DD

A

V
V
V

BW

V

NC

V

BW

V
V

V

NC

SS
SS
SS

B

SS

SS

A
SS
SS

SS

AAA

NCNCNCNC

A

NC/9M

AA

NC
DQ
DQ
DQ
DQ

V

DD

DQ
DQ

DQ
DQ

NC

A

NC/36MNC/72M

NC

B
B
B
B

A
A

A
A

V

DDQ

NC/576M

NC/1G

DQ

B

DQ

B

V

DDQ

DQ

B

DQ

B

V

DDQ

DQ

A

DQ

A

V

DDQ

DQ

A

DQ

A

NC

ZZ

V

DDQ

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BWA, BW
BWC, BW

B
D

Input-

Synchronous

GW Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

ADV Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP
the 2-bit counter.

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A

[1:0]

feed

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

CE

2

when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

1

loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE2 to select/deselect the device. CE3 is sampled only when a new external address is

CE

1

loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.

Document #: 38-05521 Rev. *D Page 3 of 17

Pin Definitions (continued)

Name I/O Description

ADSP

ADSC

ZZ Input-

DQs I/O-

V

DD

V

SS

V

DDQ

V

SSQ

MODE Input-

NC No Connects. Not Internally connected to the die.
NC/9M,

NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP

Input-

Synchronous

nized. ASDP
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP

is ignored when CE1 is deasserted HIGH

and ADSC are both asserted, only ADSP is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

Asynchronous

condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As input s, they feed into an on-chip data register that is triggered by

Synchronous

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs

are placed in a tri-state condition.

Power

Power supply inputs to the core of the device.

Supply

Ground Ground for the core of the device.

I/O Power

Power supply for the I/O circuitry.

Supply

I/O Ground Ground for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

Static

floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.

– No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,

NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.

CY7C1338G

are

DD

[1:0]

or left

and ADSC are both asserted, only ADSP is recog-

are also loaded

[1:0]

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t

The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP
(ADSC

). Address advancement through the burst sequence is
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW

Document #: 38-05521 Rev. *D Page 4 of 17

) is 6.5 ns (133-MHz device).

C0

) or the Controller Address Strobe

input. A two-bit on-chip wraparound

[A:D]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC

, CE2, and CE3 are all

1

or ADSC is asserted LOW (if

, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE
available at the data outputs a maximum to t
rise. ADSP

input is asserted LOW, the requested data will be

after clock

is ignored if CE1 is HIGH.

CDV

1

CY7C1338G

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP

is asserted LOW. The addresses

, CE2, CE3 are all asserted

1

presented are loaded into the address register and the burst
inputs (GW
clock cycle. If the write inputs are asserted active (see Write

, BWE, and BW[

])are ignored during this first

A:D

Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
BWC

controls DQC, and BWD controls DQD. All I/Os are

controls DQA and BWB controls DQB.

A

tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri -stated
once a write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC

is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC

, CE2, and CE3 are all asserted

1

is ignored if ADSP is active

, BWE, and BW

[A:D]

LOW.
The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are

[A:D]

will be

allowed. During byte writes, BWA controls DQA, BWB controls
DQ

, BWC controls DQC, and BWD controls DQD. All I/Os are

B

tri-stated when a writ e is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE

.

Burst Sequences

The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by

A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter­leaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t

.

LOW.

s, ADSP, and ADSC must remain

after the ZZ input returns

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

)

First

Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Second

Address

A1, A0

DD

)

Third

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A

0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A

0

Third

Address

A1, A

0

Fourth

Address

A1, A0

Fourth

Address

A1, A

0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Document #: 38-05521 Rev. *D Page 5 of 17

Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns

CYC

CYC

CYC

ns
ns
ns

CY7C1338G

Truth Table

[2, 3, 4, 5, 6]

Address

Cycle Description

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power-down None H X X L X L X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L X H L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L H L X X X L-H Tri-State
Deselected Cycle, Power-down None X X X L H L X X X L-H Tri-State
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Cur rent X X X L H H H L X L-H D
Write Cycle, Suspend Burst Cur rent H X X L X H H L X L-H D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE

4. The DQ pins are controlled by the current cycle and the OE

5. The SRAM always initiates a read cycle when ADSP

6. OE

= L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals

(BW

, BWB, BWC, BWD), BWE, GW = H.

A

after the ADSP
don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

signal. OE is asynchronous and is not sampled with the clock.

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW).

Document #: 38-05521 Rev. *D Page 6 of 17

CY7C1338G

Partial Truth Table for Read/Write

Function GW BWE BW

[2, 7]

D

BW

C

BW

B

BW

A

Read HHXXXX
Read HLHHHH
Write Byte A HLHHHL
Write Byte B H L H H L H
Write Bytes B, A H L H H L L
Write Byte C HLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D HLLHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, B H L L L H H
Write Bytes D, B, A H L L L H L
Write Bytes D, C, A HLLLLH
Write All Bytes HLLLLL
Write All Bytes L XXXXX

Note:

7. Table only lists a partial listing of the byte write combinations. A ny combination of BW

is valid. Appropriate write will be done based on which byte write is active.

X

Document #: 38-05521 Rev. *D Page 7 of 17

CY7C1338G

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
Supply Voltage on V
DC Voltage Applied to Outputs

in tri-state............................................ –0.5V to V

Relative to GND........–0.5V to +4.6V

DD

Relative to GND......–0.5V to +V

DDQ

DDQ

DD

+ 0.5V

DC Input Voltage....................... ............–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

T emperature

Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
Industrial –40°C to +85°C

Ambient

]

V

DD

DD

V

to V

+ 0.5V

DDQ

DD

Electrical Characteristics

Over the Operating Range

[8, 9]

Parameter Description Test Conditions Min. Max. Unit

V
V
V

V

V

V

DD
DDQ
OH

OL

IH

IL

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage 2.375 V
Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3V I/O,I

for 2.5V I/O, I

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

DD

Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V

Input LOW Voltage

for 2.5V I/O 1.7 V

[8]

for 3.3V I/O –0.3 0.8 V

+ 0.3V V

DD

for 2.5V I/O –0.3 0.7 V

I

X

I

OZ

I

DD

I

SB1

I

SB2

I

SB3

I

SB4

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE
Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS
DD
SS
DD

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current
Automatic CE

Power-Down
Current—TTL Inputs

Automatic CE
Power-Down
Current—CMOS Inputs

Automatic CE
Power-Down
Current—CMOS Inputs

Automatic CE
Power-Down
Current—TTL Inputs

V

= Max., I

DD

f = f
Max. V

V
inputs switching

= 1/t

MAX

, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = f

IN

Max. VDD, Device Deselected,
V

≥ VDD – 0.3V or VIN ≤ 0.3V,

IN

f = 0, inputs static
Max. VDD, Device Deselected,

≥ V

V

IN

DDQ

0.3V,
f = f

Max. V
V
f = 0, inputs static

, inputs switching

MAX

, Device Deselected,

DD

≥ V

IN

– 0.3V or VIN ≤ 0.3V,

DD

DDQ

−55µA

–30 µA

–5 µA

, Output Disabled –5 5 µA

DDQ
OUT

CYC

= 0 mA,

7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100 MHz 205 mA

7.5-ns cycle, 133 MHz 90 mA

,

MAX

10-ns cycle, 100 MHz 80 mA
All speeds 40 mA

7.5-ns cycle, 133 MHz 75 mA

– 0.3V or VIN ≤

10-ns cycle, 100 MHz 65 mA

All speeds 45 mA

5 µA

30 µA

V

Notes:

8. Overshoot: V

9. T

Power-up

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

Document #: 38-05521 Rev. *D Page 8 of 17

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

DDQ

< VDD.

CYC

/2).

CY7C1338G

Capacitance

[10]

Parameter Description T est Conditions

C

IN

C

CLK

C

I/O

Thermal Resistance

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V.

V

Clock Input Capacitance 5 5 pF
Input/Output Capacitance 5 7 pF

[10]

V

DD
DDQ

= 3.3V

Parameter Description Test Conditions

ΘJA Thermal Resistance

(Junction to Ambient)

ΘJC Thermal Resistance

(Junction to Case)

T est conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

= 50Ω

Z

0

2.5V I/O Test Load

OUTPUT

= 50Ω

Z

0

3.3V

OUTPUT

= 50Ω

R

L

VT= 1.5V

(a) (b)

2.5V

OUTPUT

= 50Ω

R

L

= 1.25V

V

T

(a) (b)

5pF

INCLUDING

JIG AND

SCOPE

5pF

INCLUDING

JIG AND

SCOPE

R = 317Ω

R = 1667Ω

R = 351Ω

R =1538Ω

GND

V

DDQ

GND

V

DDQ

100 TQFP

Max.

119 BGA

Max. Unit

55pF

100 TQFP

Package

119 BGA
Package Unit

30.32 34.1 °C/W

6.85 14.0 °C/W

ALL INPUT PULSES

10%

≤ 1 ns

90%

(c)

ALL INPUT PULSES

10%

≤ 1ns

90%

(c)

90%

10%

≤ 1 ns

90%

10%

≤ 1ns

Note:

10.Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05521 Rev. *D Page 9 of 17

CY7C1338G

Switching Characteristics Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

VDD(Typical) to the first Access

Clock Cycle Time 7.5 10 ns
Clock HIGH 2.5 4.0 ns
Clock LOW 2.5 4.0 ns

Data Output Valid After CLK Rise 6.5 8.0 ns
Data Output Hold After CLK Rise 2.0 2.0 ns
Clock to Low-Z
Clock to High-Z

[12, 13, 14]

[12, 13, 14]

OE LOW to Output Valid 3.5 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z

Address Set-up Before CLK Rise 1.5 2.0 ns
ADSP, ADSC Set-up Before CLK Rise 1.5 2.0 ns
ADV Set-up Before CLK Rise
GW, BWE, BWX Set-up Before CLK Rise 1.5 2.0 ns
Data Input Set-up Before CLK Rise 1.5 1.5 ns
Chip Enable Set-up 1.5 2.0 ns

Address Hold After CLK Rise 0.5 0.5 ns
ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns
GW, BWE, BWX Hold After CLK Rise 0.5 0.5 ns
ADV Hold After CLK Rise 0.5 0.5 ns
Data Input Hold After CLK Rise 0.5 0.5 ns
Chip Enable Hold After CLK Rise 0.5 0.5 ns

[11]

[12, 13, 14]

[12, 13, 14]

[11, 12, 13, 14, 15, 16]

–133 –100

UnitMin. Max. Min. Max.

11ms

00ns

3.5 3.5 ns

00ns

3.5 3.5 ns

1.5 2.0 ns

Notes:

11.This part has a voltage regulator internally; t
can be initiated.

, t

12.t

CHZ

13.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect para meters guaran teed over worst case user con ditions. Device is d esigned
to achieve High-Z prior to Low-Z under the same system conditions.

14.This parameter is sampled and not 100% tested.

15.Timing reference level is 1.5V when V

16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in p art (b) of AC Test Loads. Transition is measured ± 200 mV from ste ady-state vo ltage.

OEHZ

POWER

OEHZ

= 3.3V and is 1.25V when V

DDQ

Document #: 38-05521 Rev. *D Page 10 of 17

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

is less than t

OELZ

and t

is less than t

CHZ

DDQ

= 2.5V.

to eliminate bus contention between SRAMs when sha ring the same

CLZ

Timing Diagrams

G

Read Cycle Timing

[17]

t

CYC

CY7C1338G

CLK

ADSP

ADSC

ADDRESS

W, BWE,BW

[A:D]

CE

ADV

OE

Data Out (Q)

Note:

17.On this diagram, when CE

High-Z

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

t

WES

t

t

CES

CEH

t

WEH

A2

t

ADVS

t

ADVH

Deselect Cycle

ADV suspends burst.

t

DOH

Q(A2)

t

CDV

Q(A2 + 1)

Q(A2 + 2)

BURST

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around
to its initial state

t

OEV

t

CLZ

t

CDV

Single READ

t

OEHZ

Q(A1)

t

OELZ

READ

DON’T CARE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

UNDEFINED

t

CHZ

Q(A2 + 2)

Document #: 38-05521 Rev. *D Page 11 of 17

Timing Diagrams (continued)

D

Write Cycle Timing

[17, 18]

t

CYC

CY7C1338G

ADDRESS

BWE,

BW

CLK

ADSP

ADSC

[A:D]

GW

CE

ADV

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are ignored for first cycle when
ADSP initiates burst

t

t

CEH

CES

A2 A3

t

WES

t

WEH

ADSC extends burst

ADV suspends burst

t

ADS

t

ADH

t

t

ADVS

WES

t

WEH

t

ADVH

OE

Data in (D)

ata Out (Q)

High-Z

BURST READ BURST WRITE

t

OEHZ

Note:

18.

Full width write can be initiated by either GW

t

t

DH

DS

D(A1)

Single WRITE

D(A2)

DON’T CARE UNDEFINED

LOW; or by GW HIGH, BWE LOW and BW

D(A2 + 1)

D(A2 + 1)

[A:D]

D(A2 + 2)

LOW.

D(A2 + 3)

D(A3)

D(A3 + 1)

Extended BURST WRITE

D(A3 + 2)

Document #: 38-05521 Rev. *D Page 12 of 17

Timing Diagrams (continued)

t

Read/Write Timing

[17, 19, 20]

CYC

CY7C1338G

CLK

ADSP

ADSC

ADDRESS

BWE, BW[A:D]

CE

ADV

OE

Data In (D)

Data Out (Q)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

t

CES

A2

t

CEH

A1 A5 A6

High-Z

Q(A1)

Q(A2)

A3 A4

t

OEHZ

t

WES

t

DS

D(A3)

t

t

DH

WEH

t

OELZ

t

CDV

Q(A4) Q(A4+1)

Q(A4+2)

D(A5) D(A6)

Q(A4+3)

Back-to-Back READs

Notes:

19.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP

20.

GW

is HIGH.

Document #: 38-05521 Rev. *D Page 13 of 17

Single WRITE

BURST READ

DON’T CARE UNDEFINED

Back-to-Back

WRITEs

or ADSC.

Timing Diagrams (continued)

A

ZZ Mode Timing

[21, 22]

CLK

CY7C1338G

t

ZZ

t

ZZREC

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05521 Rev. *D Page 14 of 17

CY7C1338G

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed
(MHz) Ordering Code

133 CY7C1338G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1338G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1338G-133BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1338G-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1338G-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1338G-133BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

100 CY7C1338G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1338G-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1338G-100BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1338G-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1338G-100BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1338G-100BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

Package Diagrams

visit www.cypress.com for actual products offered.

Package
Diagram Part and Package Type

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

Operating

Range

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

1.40±0.05

12°±1°

(8X)

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

51-85050-*B

SEE DETAIL

0.20 MAX.

1.60 MAX.

0.10

A

Document #: 38-05521 Rev. *D Page 15 of 17

Package Diagrams (continued)

A1 CORNER

2165437

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

119- Ba ll BGA (14 x 22 x 2.4 mm) (51-85115)

Ø1.00(3X) REF.

1.27

19.50

20.32

22.00±0.20

10.16

CY7C1338G

Ø0.05 M C

Ø0.25MCAB

Ø0.75±0.15(119X)

2143657

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

0.70 REF.

12.00

30° TYP.

0.90±0.05

0.25 C

SEATING PLANE

C

0.56

2.40 MAX.

0.15 C

0±0.10

A

B

0.15(4X)

3.81

7.62

14.00±0.20

51-85115-*B

1.27

Intel and Pentium are registered trademarks and i486 is a tr ademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05521 Rev. *D Page 16 of 17

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change withou t n oti ce. C ypr ess S emi con duct or Corpo ration assu mes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Document History Page

Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM
Document Number: 38-05521

REV. ECN NO. Issue Date

** 224369 See ECN RKF New data sheet

*A 278513 See ECN VBL Deleted 66 MHz

*B 333626 See ECN SYT Removed 117-MHz speed bin

*C 418633 See ECN RXU Converted from Preliminary to Final

*D 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on V

Orig. of
Change Description of Change

Changed TQFP to PB-Free TQFP in Ordering Info section
Added PB-Free BG package

Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accord­ingly
Modified V
Replaced ‘Snooze’ with ‘Sleep’

OL, VOH

test conditions

Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal
Resistance table
Removed comment on the availability of BG lead-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed I
Modified test condition from V
Modified test condition from V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

from Electrical Characteristics table on Page #8

OS

< V

IH

< VDD to V

DDQ

DD to VIH

Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information table

Updated the Ordering Information table.

< V

DDQ

DD

< V

CY7C1338G

DD

Relative to GND.

DDQ

Document #: 38-05521 Rev. *D Page 17 of 17