Cypress Semiconductor CY7C1338-117AC, CY7C1338-100AC Datasheet

CY7C1338

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Features

• Supports 117-MHz m icroprocessor cache systems with
zero wait states

• 128K by 32 common I/O

• Fast clock-to-output times

—7.5 ns (117-MHz version)

• T wo-bit wraparound counter supporting either inter­leaved or linea r burst sequence

• Separate pro cessor and contro ller address strobe s pro­vide direct int erface with the processor and external
cache controller

• Synchro nous self-timed write

• Asynchr onous output enable

•3.3V I/Os

• JEDEC-standard pinout

• 100-pin TQFP packag ing

• ZZ “sleep” mode

Logic Block Diagram

CLK
ADV

ADSC

ADSP

A

BW

BW

BW

BW

[16:0]

GW

BWE

0

CE
CE

CE

3

2

1

1
2

3

17

MODE

(A0,A1)

2

BURST

COUNTER

CE

CLR

ADDRESS

CE

REGISTER

D

15

DQ[31:24]

D

BYTEWRITE
REGISTERS

DQ[23:16]

D Q

BYTEWRITE
REGISTERS

DQ

DQ[15:8]
BYTEWRITE
REGISTERS

D Q

DQ[7:0]
BYTEWRITE
REGISTERS

D

ENABLE

CE

REGISTER

CLK

Functional Description

The CY7C1338 is a 3.3V, 128K by 32 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap­tures the first address in a burst and increments the address
automatically for the rest of the burst access.

The CY7C1338 allows both interleaved and linear burst se­quences, selected by the MODE inp ut pin. A HIGH selects an
interleave d burst sequence, whi le a LOW s elects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP
Strobe (ADSC

) inputs. Address advancement is controlled by

the address advancement (ADV
A synchronous sel f-t imed write me chanism i s provi ded to sim -

plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state contr ol.

Q

0

Q

1

Q

15

Q

Q

) or the cache Controller Address

) input.

17

128K X 32

MEMORY

ARRAY

32 32

INPUT

REGISTERS

CLK

OE

ZZ

SLEEP

CONTROL

Selection G uide

7C1338-117 7C1338-100 7C1338-90 7C1338-50

Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operat ing Current (mA) 350 325 300 250
Maximum Standb y Current (mA) 2.0 2.0 2.0 2.0

Intel and Pentium are registered trademarks of Intel Corporation.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 5, 2000

DQ

[31:0]

Pin Configuration

100-Lead TQFP

A6A7CE1CE2BW3BW2BW1BW0CE3VDDVSSCLKGWBWE

99989796959493929190898887868584838281

100

OE

ADSC

ADSP

CY7C1338

9

ADV

A8A

BYTE2

BYTE3

DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ

DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ

NC

DDQ
SSQ

SSQ
DDQ

NC

V

DD

NC
V

SS

DDQ

SSQ

SSQ

DDQ

NC

1

16
17

2
3
4
5

18
19
20
21

6
7
8
9
10
11

22
23

12
13
14
15

CY7C1338

16
17

24
25

18
19
20
21

26
27
28
29

22
23
24
25
26
27

30
31

28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
NC

15
14

13
12
11
10

9
8

7
6

5
4
3
2

1
0

BYTE1

BYTE0

31323334353637383940414243444546474849

A5A4A3A2A1A

MODE

0

DNU

SS

DD

V

V

DNU

DNU

DNU

10

A11A12A13A

A

15

14

A

2

50

A

16

CY7C1338

Pin Descriptions

Pin Number Name I/O Description

85 ADSC Input-

Synchronous

84 ADSP Input-

Synchronous

36, 37 A

49−44,
81–82,

A

[1:0]

[16:2]

Input­Synchronous

Input-

Synchronous
99–100,
32–35

96–93 BW

[3:0]

Input-

Synchronous

83 ADV Input-

Synchronous

87 BWE Input-

Synchronous
88 GW Input-

Synchronous

89 CLK Input-Clock Cl ock Input. Used to capture all synchronous inputs to the device.
98 CE

Input-

1

Synchronous
97 CE

Input-

2

Synchronous
92 CE

3

Input-

Synchronous
86 OE Input-

Asynchronous

64 ZZ Input-

Asynchronous

31 MODE - Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved

29–28,
25–22,

DQ

[31:0]

I/O-

Synchronous
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68,
63–62,
59–56,
53–52

15, 41, 65, 91V

DD

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

Address Strobe f rom Controller, sampled on the rising edge of CLK. When asserted
LOW, A
counter. When ADSP

is capture d in the address registers . A

[16:0]

and ADSC are both asserted, only ADSP is recognized.

are also loaded into t he burst

[1:0]

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
counter. When ADSP
is ig no red when CE

is capture d in the address registers . A

[16:0]

and ADSC are both as serted, onl y ADSP is r ecogni ze d. ASDP

is deasserted HIGH.

1

are also loaded into t he burst

[1:0]

A1, A0 Address Inputs. These inputs feed the on- chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.

Address Inputs used in conjunction with A
tions. Sampl ed at the rising edge of the CLK, if CE
and ADSP

or ADSC is active LO W.

to select one of the 64K address loca-

[1:0]

and CE3 are sampled activ e,

1, CE2,

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge . BW
DP

, BW2 controls DQ

1

Cycle Descriptions table for further details.

[23:16]

controls DQ

0

and DP0, BW1 controls DQ

[7:0]

and DP2, and BW3 controls DQ

and DP3. See Write

[31:24]

[15:8]

and

Advance Input use d to advan ce the on-chip address counter . When LOW the internal
burst count er is adv anced in a burs t s equence . Th e bur st sequence i s s elect ed using
the MODE input.

Byte Write Enab le I nput, a ctiv e LO W. Sampled on the rising edge of CLK. Thi s sign al
must be asserted LOW to conduct a byte write.

Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE
writes override byte writes.

and BW

[3:0]

. Global

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con­junction with CE

and CE3 to select/deselect the device. CE1 gates ADSP.

2

Chip Enable 2 Input, act ive HIGH. Sampled on the rising edge of CLK. Used in con­junction with CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con­junction with CE

and CE2 to select/deselect the device.

1

Output Enable , asynchronous i nput, active LO W . Controls the dir ection of the I/O pins .
When LOW, the I/O pins behave as outpu ts. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.

Snooze Input . Activ e HIGH asynchron ous. When HIGH, the de vice enter s a low-po wer
standby m ode in which all other i nputs are ignored, but the data i n the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.

burst order. Pulled LOW selects the linear burst order. When left floating or NC, de­faults to int erl eaved burst order. Mode pin has an internal pull-up.

Bidirectional Data I/O lines. As inputs , they feed into an on-chip data register t hat is
triggered b y the rising edge of CLK. As out puts, the y deliver the data contained i n the
memory location specified by A
The direction of the pi ns is controlled by OE
logic. When OE
and DP
three-stated when a WRI TE cycle is detected.

[3:0]

is asserted LOW, the pins behav e as outputs. When HIGH, DQ

are placed in a three-state condition. The outputs are automatically

during the pre vious clock ris e of the read cycle.

[16:0]

in conjunction wit h the internal control

[31:0]

supply.

3

CY7C1338

Pin Descriptions

(continued)

Pin Number Name I/O Description

17, 40, 67, 90V

5, 10, 21,
26, 55, 60,

V

SS

SSQ

Ground Ground for the I/O circuit ry of the device. Should be connected to ground of the

system.

Ground Ground for the device. Should be connect ed to ground of the system.
71, 76

4, 11, 20,
27, 54, 61,

V

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

70, 77
1,14, 16, 30,

NC - No connects.
50–51, 66,
80

38, 39, 42, 43DNU - Do not use pins. Should be left unconnected or tied LOW.

Functional Overview

All synchrono us inputs pass throu gh inp ut regi sters con trol led
by the rising edge of the clock. Maximum access delay from
the clock ris e (t

The CY7C1338 sup ports secondary cache in systems utilizin g
either a linear or interleaved burst sequence. The interleaved
burst order supports Pen ti um and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user selectable, and i s de­termined by sampling the MODE input. Accesses can be initi­ated with either the Processor Address Strobe (ADSP
Controller Address Strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on -chip wraparou nd burs t counter ca ptures the fi rst ad­dress in a burst sequence and automatically increments the
addr ess for the res t of the bu rst acc e ss.

Byte write operations are qualified with the Byt e Writ e Enable
(BWE

) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip synchro­nous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
lection and output three-state control. ADSP
is HIGH.

Single Read Accesses

A single re ad access is ini ti ated when the following conditions
are satisfied at clock rise: (1) CE
serted active, and (2) ADSP
access is initiated by ADSC

) is 7.5 ns (117-MHz de vice).

CDV

) or the

). Address advancement

input. A

) inputs. A Global Write

) overrides all byte write inpu ts and writes data to

[3:0]

, CE2, CE3) and an

1

) provide for easy bank se-

is ignored if CE

, CE2, and CE3 are all as-

1

or ADSC is asserted LOW (if the

, the write i nputs mus t be de assert-

counter/control logi c and delive red to the RAM cor e . The write
inputs (GW
clock cycle. If the write inputs are asserted active (see Write

, BWE, and BW

[3:0]

Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
DQ
All I/Os are three-stated during a byte write. Since this is a

, BW2 controls DQ

[15:8]

controls DQ

0

[23:16]

common I/O device, the asynchronous OE
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ
data lines are three-stated once a write cycle is detected, re­gardless of the state of OE

[31:0]

.

Single Write Accesses Initiated by ADSC

This write access is init iated when the f ol low ing con diti ons are
satisfied at clock rise: (1) CE
active, (2 ) ADSC

is asserted LOW, (3) ADSP is deasserted

1

HIGH, and (4) t he wri te input signals (GW
indicate a write access . ADSC

The addresses pres ent ed are l oaded int o the ad dres s regi ster
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ
the specified addr ess locati on. Byte writes ar e allowed . During

1

byte w rites, BW
controls DQ
three-stated when a write is det ected, e ven a b yte wri te. Since

controls DQ

0

, and BWS3 controls DQ

[23:16]

[7:0]

this is a c ommon I/O de vice , the asyn chronous OE
must be deasserted and the I/Os m ust be t hree-st ated pri or to
the presentat ion of da ta to DQ

[31:0]

data lines are three-stated once a write cycle is detected, re­gardless of the state of OE

.

ed during this first cycle). The address presented to the ad­dress inputs is latc hed into the address register and th e burst

Burst Sequences

counter/con trol logic and presented to the memory core . If th e
OE

input is asserted LOW , the requeste d data will be av ailab le
at the data outputs a maximum to t
is ignored if CE1 is HIGH.

after clock rise. ADSP

CDV

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are sat­isfi ed at clock rise: (1) CE
active, and (2) ADSP

, CE2, and CE3 are all asse rted

1

is asserted LOW. The addresses pre-

The CY7C1338 provides an on- chi p 2-bit wraparound burst
counter inside t he SRAM. The burst counter is fed by A
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will sele ct a l inear b u rst se quence. A HI GH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.

sented are loaded into the address register and the burst

) are ignored during this first

, BW1 controls

, and BW3 controls DQ

[7:0]

[31:24]

input signal must

. As a safety precaution, the

, CE2, and CE3 are all asserted

, BWE, and BW

[3:0]

is ignored if ADSP is active LOW.

will be wri tt en into

[31:0]

, BW1 controls DQ

[31:24]

, BW

[15:8]

. All I/O s are

input signal

. As a saf ety preca ution, t he

[1:0]

.

)

2

,

4

Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence

First

Address
A

X + 1, Ax

Second

Address
A

X + 1, Ax

Third

Address
A

X + 1, Ax

Fourth

Address
A

X + 1, Ax

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Table 2. Counter Implementation for a Linear Sequence

First

Address
A

, A

X + 1

x

Second

Address
A

, A

X + 1

Third

Address
A

x

X + 1

, A

x

Fourth

Address
A

, A

X + 1

x

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

ZZ Mode Electrical Characteristics

CY7C1338

Sleep Mode

The ZZ input pin is an as ynchrono us input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exi t from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac­cesses pending when entering the “sleep” mode are not con­sidered valid nor is the completion of the operation guaran­teed. The device must be deselected prior to entering the
“sleep” mode. CE
inactive for the duration of t
LOW. Leaving ZZ unconnected defaul ts the device into an ac­tive stat e.

, CE2, CE3, ADSP, and ADSC must remain

1

after the ZZ input returns

ZZREC

Parameter Description Test Conditions Min. Max. Unit

I

CCZZ

t

ZZS

t

ZZREC

Snooze mode

ZZ > V

standby cu rrent

Device operat ion to ZZZZ > VDD − 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

− 0.2V 10 mA

DD

CYC

CYC

ns

ns

5