Datasheet CY7C133-35JC, CY7C133-25JI, CY7C133-25JC, CY7C133-55JC, CY7C133-35JI Datasheet (Cypress Semiconductor)
CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
• 2K x 16 organizat ion
• 0.65-micron CMOS for optimum sp eed/power
• High-speed access: 25/35/55 ns
• Low op e rating pow er: I
= 150 mA (typ.)
CC
• Fully asy nchronous operation
• Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
• BUSY input flag on CY7C133; BUSY output flag on
CY7C143
• Available in 68-pin PLCC
• Pin-compati ble and f unction all y equiva len t to IDT713 3
and IDT7143
Logic Block Diagram
CE
L
R/W
LUB
R/W
LLB
OE
L
Functional Description
The CY7C133 and CY7C143 are high- speed CMOS 2K b y 16
dual-port static RAMs. Tw o ports are provided permitti ng independent access to any locat ion in memory. T he CY7C133 can
be utilized as either a stand-alone 16-bit dual-port static RAM
or as a master dual-port RAM in conjunct ion with the CY7C143
slave dual-port device in systems requiring 32-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; Chip Enable (CE
Write Enable (R/W
signals that the port is trying to access the sam e location currently being accessed by the other port. An automatic power-down feature is controlled independently on each port by
the Chip Enable (CE
The CY7C133 and CY7C143 are available in 68-pin PLCC.
, R/WLB), and Output Enab le (OE). BUSY
UB
) pin.
CE
R
R/W
RUB
R/W
RLB
OE
R
),
I/O8L– I/O
15L
I/O0L– I/O
7L
[1]
BUSY
L
A
10L
A
0L
Note:
1. CY7C133 (Master): BUSY
is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
ADDRESS
DECODER
Cypress Semiconductor Corporation
I/O8R– I/O
I/O0R– I/O
[]
1
BUSY
R
A
10R
A
0R
15R
7R
C133-1
R/W
R/W
CONTROL
CE
L
OE
L
LUB
LLB
I/O
MEMORY
ARRAY
ARBITRATION
LOGIC
(CY7C133ONLY)
I/O
CONTROL
ADDRESS
DECODER
CE
R
OE
R
R/W
RUB
R/W
RLB
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 14, 1999
Pin Configuration
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10L
11L
12L
13L
14L
15L
CY7C133
CY7C143
68-Pin
LCC/PLCC
Top View
LLB
I/O
I/O
1L
15R
I/O
GND
LUB
0L
CC
V
R/W
L
10L
R/W
OE
R/W
67
R
10R
RLB
RUB
OE
A
R/W
7LA8LA9L
A
A
A
60
6L
A
59
5L
A
58
4L
A
57
3L
A
56
2L
A
55
1L
A
54
0L
BUSY
53
52
51
50
49
48
47
46
45
44
6R
7RA8RA9R
A
A
CE
CE
BUSY
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
L
L
R
R
C133-2
8L
7L
6L
5L
4L
3L
I/O
I/O
I/O
987 6
9L
10
11
12
13
14
15
16
CC
17
18
0R
19
1R
20
2R
21
3R
22
4R
23
5R
24
6R
25
7R
26
2728 29 30
9R
8R
10R
I/O
I/O
I/O
2L
I/O
I/O
I/O
I/O
5432168 666564636261
7C133
7C143
3132 33 34 35 36 37 38 39 40 41 42 43
14R
13R
12R
11R
I/O
I/O
I/O
I/O
Selection G uide
7C133-25
7C143-25
Maximum Access Time (ns) 25 35 55
Typical Operating Current ICC (mA) 170 160 150
Typical Standby Current for I
Maximum Ratings
(Abov e which the useful life m ay be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Po wer Applied..................................................−55°C to +125°C
(mA) 40 30 20
SB1
DC Input Voltage.................................................−3.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ................................... .. ..... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .......................... ............. >200 mA
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial
7C133-35
7C143-35
7C133-55
7C143-55
Ambient
Temperature V
−40°
C to +85°C 5V ± 10%
CC
2
CY7C133
CY7C143
Electrical Characteristics
Over the Operating Range
Parameter Description Test Co ndit ions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
2. BUSY
3. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
5. At f=f
MAX
Output HIGH Voltage VCC = Min.,
I
= –4.0 mA
OH
Output LOW Voltage IOL = 4.0 mA 0.4 V
IOL = 16.0 mA
[2]
Input HIGH Voltage 2.2 V
Input LOW Voltage 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled
Output Short Circuit
[3,4]
Current
VCC Operating Supply Cur-
rent
Standby Curr ent Both Ports,
VCC = Max.,
V
= GND
OUT
CE = VIL,
Outputs Open,
f = f
MAX
[5]
CEL and CER > VIH, f = f
TTL Inputs
Standby Current One Port,
TTL Inputs
Standby Curr ent Both Ports,
CMOS Inputs
Standby Current One Port,
CMOS Inputs
pin only .
, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
CEL or CER > VIH, Active Port Outputs Open, f = f
MAX
[5]
Both Ports CEL and CER > VCC –
0.2V , V
f = 0
> VCC – 0.2V or VIN < 0.2V ,
IN
One Port CEL or CER > VCC – 0.2V,
V
> VCC – 0.2V or
IN
V
< 0.2V, Active P ort Outputs Open,
IN
[5]
f = f
MAX
MAX
7C133-25
7C143-25
2.4 V
−5
−5
Com’l 170 250 mA
Ind. 170 290
[5]
Com’l 40 60 mA
Ind. 40 75
Com’l 100 140 mA
Ind. 100 160
Com’l 3 15 mA
Ind. 3 15
Com’l 90 120 mA
Ind. 90 140
0.5
+5
+5
−200
UnitMin. Typ. Max.
µA
µA
mA
3
CY7C133
CY7C143
Electrical Characteristics
Over the Operating Range (continued)
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
Output HIGH Voltage VCC = Min.,
I
= –4.0 mA
OH
Output LOW Voltage IOL = 4.0 mA 0.4 0.4 V
I
= 16.0 mA
OL
[2]
Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Curr ent GND < VI < V
Output Leakage
GND < VO < VCC, Output Disabled −5+5−5 −5 µA
CC
Current
I
OS
I
CC
I
SB1
Output Short Circuit
[3,4]
Current
VCC Operating Supply
Current
Standby Current Both
VCC = Max.,
V
= GND
OUT
CE = VIL,
Outputs Open,
f = f
MAX
[5]
CEL and CER > VIH, f = f
Ports, TTL I nputs
I
SB2
I
SB3
I
SB4
Standby Current One
Port, TTL Inputs
Standby Current Both
Ports, CMOS Inputs
Standby Current One
Port, CMO S In p ut s
CEL or CER > VIH, Activ e P ort
Outputs Open, f = f
MAX
Both Ports CEL and CER >
V
- 0.2V, VIN > VCC – 0.2V
CC
or V
< 0.2V, f = 0
IN
One Port CEL or CER > VCC –
0.2V, V
V
Open, f = f
> VCC – 0.2V or
IN
< 0.2V , A c tive Port O u tp u t s
IN
MAX
[5]
7C133-35
7C143-35
7C133-55
7C143-55
UnitMin. Typ. Max. Min. Typ. Max.
2.4 2.4 V
0.5 0.5
−5+5−5+5µA
−200 −200 mA
Com’l 160 230 150 220 mA
Ind. 160 260 150 250
[5]
Com’l30502040mA
MAX
Ind. 30 65 20 55
Com’l 85 125 75 110 mA
[5]
Ind. 85 140 75 125
Com’l315315mA
Ind. 3 15 3 15
Com’l 80 105 70 90 mA
Ind. 80 120 70 105
Capacitance
[4]
Parameter Description Te st Condi tions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 10 pF
Output Capacitance 10 pF
AC Test Loads and Waveforms
5V
OUTPUT
30pF
INCLUDING
JIG AND
SCOPE
Equivalent to: TH ÉVENIN
OUTPUT 1.40V
R1893
(a)
Ω
R2
347
Ω
C133-2
EQUIVALENT
250
Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5pF
R1893
(b)
3.0V
GND
<
3 ns
Ω
R2
347
10%
Ω
C133-3
ALL INPUT PULSES
90%
BUSY
OR
INT
90%
10%
< 3 ns
5V
281
30
pF
BUSY Output Load
(CY7C133ONLY)
C133-4
Ω
4
CY7C133
CY7C143
Switching Characteristics
Over the Operati n g Range
Parameter Description
[6]
7C133-25
7C143-25
7C133-35
7C143-35
7C133-55
7C143-55
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6. T est conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL/IOH,
7. AC Test Conditions use V
8. At any given temperature and voltage condition for any given device, t
9. t
LZCE
voltage.
10. This parameter is guaranteed but not tested.
11. The internal write time of the memory is defined by the overlap of CS
can terminat e a wri te by goi ng HI GH. Th e data i np ut set -up an d hold timing sho ul d be re f ere nc ed to th e risin g edg e of th e si gn al th at te rmin at es the writ e .
Read Cycle Time 25 35 55 ns
Address to Data Valid
[7]
25 35 55 ns
Data Hold from Address Change 0 0 0 ns
CE LOW to Data Va lid
OE LOW to Data Valid
OE LOW to Lo w Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to H ig h Z
CE LOW to Po wer-Up
CE HIGH to Power-Down
[11]
[7]
[7]
[8, 9,10]
[8, 9,10]
[8, 9,1 0]
[8, 9,10]
[10]
[10]
25 35 55 ns
20 25 30 ns
3 3 3 ns
15 20 25 ns
3 5 5 ns
15 20 20 ns
0 0 0 ns
25 25 25 ns
Write Cycle Time 25 35 55 ns
CE LOW to Write End 20 25 40 ns
Address Set-Up to Write End 20 25 40 ns
Address Hold from Write End 2 2 2 ns
Address Set-Up to Write Start 0 0 0 ns
R/W Pulse Wi dth 20 25 35 ns
Data Se t- U p to Write End 15 20 20 ns
Data Hold from Write End 0 0 0 ns
and t
[9,10]
[9,10]
are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state
HZWE
0 0 0 ns
is less than t
LZCE
LOW and R/W LOW. Both signals m ust be LOW to initiate a write and either signal
15 20 20 ns
HZCE
and t
is less than t
LZOE
HZOE
.
R/W LOW to High Z
R/W HIGH to Low Z
and 30-pF load capacitance.
, t
, t
LZWE
HZOE
= 1.6V and VOL = 1.4V.
OH
, t
, t
LZOE
HZCE
5
Switching Characteristics
Over the Operati n g Range
[6]
(continued )
CY7C133
CY7C143
Parameter Description
BUSY/INTERRUPT TIMING (For Master CY7C133)
t
BLA
t
BHA
t
BLC
t
BHC
t
WDD
t
DDD
t
BDD
t
PS
BUSY Low from Address Match 25 35 50 ns
BUSY High from Address Mismat ch 20 30 40 ns
BUSY Low from CE LOW 20 25 35 ns
BUSY High from CE HIGH 20 20 30 ns
Write Pulse to Data Delay
Write Data Valid to Read Data
[12]
Valid
BUSY High to Valid Data
Arbitration Priority Set Up Time
[12]
[13]
[14]
BUSY TIMING (For Slave CY7C143)
t
WB
t
WH
t
WDD
t
DDD
Write to BU SY
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data
[17]
Valid
[15]
[16]
[17]
7C133-25
7C143-25
7C133-35
7C143-35
7C133-55
7C143-55
UnitMin. Max. Min. Max. Min . Max.
50 60 80 ns
35 45 55 ns
Note 13 Note 13 Note 13 ns
5 5 5 ns
0 0 0 ns
20 25 30 ns
50 60 80 ns
35 45 55 ns
Switching Wave f o rms
Read Cycle No.1
ADDRESS
DATA OUT
Notes:
12. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY
13. t
14. To ensure that the earlier of the two ports wins.
15. To ensure that write cycle is inhibited during contention.
16. To ensure that a write cycle is completed after contention.
17. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with Port-to-port Delay.”
18. R/W
19. De vice is continuously selected, CE = VIL and OE = VIL.
is a calculated parameter and is greater of 0,t
BDD
is HIGH for read cycle.
[18, 19]
t
OHA
Either Port Address Access
t
RC
t
AA
WDD–tWP
(actua l ) or t
DDD–tDW
(actual).
DATA VALIDPREVIOUS DATA VALID
, Master: CY 7C 13 3 .”
C133-5
6
CY7C133
CY7C143
Switching Wave f o rms
SB
R
[18, 20]
t
PU
[19]
R
Read Cycle No. 2
CE
OE
DATA O UT
I
CC
I
Read Cycle No. 3
ADDRESS
R/W
D
INR
(continued)
t
LZOE
t
LZCE
Either Port CE/OE Access
t
ACE
t
DOE
DATA VALID
Read with BUSY (For Master CY7C133)
t
RC
ADDRESS MATCH
t
PWE
VALID
t
HZOE
t
HZCE
t
PD
C133-6
t
HD
ADDRESS
Note:
20. Address valid prior to or coincidence with CE
BUSY
DOUT
L
L
L
t
PS
transition LOW.
t
BLA
ADDRESS MATCH
t
WDD
t
DDD
t
BHA
t
BDD
VALID
C133-7
7
CY7C133
CY7C143
Switching Wave f o rms
(continued)
Timing Waveform of Read with Port-to-port Delay No. 4 (For Slave CY7C143)
t
WC
ADDRESS
ADDRESS
R/W
D
INR
DOUT
R
R
L
L
Write Cycle No. 1 (OE Three-States Data I/Os - Either Port)
MATCH
[14, 24]
t
WP
MATCH
EitherPort
t
WC
[21, 22, 23]
t
DW
t
WDD
VALID
t
DDD
t
DH
VALID
C133-8
ADDRESS
t
SCE
CE
t
t
SA
AW
R/W
DAT A
IN
OE
t
HZOE
D
OUT
Notes:
21. Assume BUSY
22. Write cycle parameters should be adhered to in order to ensure proper writing.
23. De vice is continuously enabled for both ports.
24. If OE
impeda n c e an d for dat a to be pl a ced on the bus for th e req ui re d t
input at VIH for the writing port and at VIL for the reading port.l
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
.
SD
t
PWE
t
SD
DATA VALID
HIGH IMPEDANCE
PWE
t
HA
t
HD
or t
+ tSD to allow the data I/O pins to enter high
HZWE
C133-9
8
CY7C133
CY7C143
Switching Wave f o rms
(continued)
Write Cycle No. 2 (R/W Three-States Data I/Os—Either P ort)
Either Port
t
WC
ADDRESS
t
SCE
CE
t
t
SA
AW
R/W
DAT A
IN
t
HZWE
DAT A
OUT
Busy Timing Diagram No. 1 (CE Arbitratio n)
[20, 25]
t
PWE
VALID
t
HD
t
LZWE
t
SD
DA TA
HIGH IMPEDANCE
t
HA
C133-10
CELValid First:
ADDRESS
CE
CE
BUSY
L,R
L
R
R
CERValid First:
ADDRESS
CE
CE
BUSY
L,R
R
L
L
ADDRESS MAT CH
t
PS
ADDRESS MATCH
t
PS
t
BLC
t
BLC
t
BHC
t
BHC
C133-11
Note:
25. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
9
CY7C133
CY7C143
Switching Wave f o rms
(continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
or t
t
RC
WC
ADDRESS MATCH
ADDRESS
ADDRESS
BUSY
L
R
R
t
PS
t
BLA
Right Address Valid First:
tRCor t
WC
ADDRESS
ADDRESS
BUSY
R
L
L
ADDRESS MATCH ADDRESS MISMATCH
t
PS
t
BLA
ADDRESS MISMATCH
t
BHA
t
BHA
C133-12
Busy Timing Diagram No. 3
Write wit h BU SY (For Slave CY7C143)
CE
R/W
t
WB
BUSY
t
PWE
t
WH
C133-13
10
CY7C133
Data Rete ntion Mode
7C133–13
4.5V
4.5V
V
CC
>
2.0V
V
CC
to VCC– 0.2V
V
CC
CE
t
RC
V
IH
CY7C143
Architecture
The CY7C133 (master) and CY7C143 (slave) consist of an
array of 2K words of 16 bits each of dual-port RAM cells, I/O
and address lines, and control signals (CE
, OE, R/W). These
control pins permit independent access for reads or writes to any location in memory . To handle simultaneous writes/reads to the same
location, a BUSY
pin is provided on each port. The CY7C133 and
CY7C143 have an automatic power-down feature controlled by CE
Each port is provided with its own output enable control (OE
), which
allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W
in order to guarantee a valid write. A write operation is controlled by either the R/W
CE
pin (see Write Cycle No. 2 waveform). T wo R/W pins (R/WUB and
R/W
) are used to separate the upper and lower bytes of IO. Re-
LB
pin (see Write Cycle No. 1 waveform) or the
quired inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read t hat location, a port-to-port flow-through
delay m ust occur before t he data is read on the output; othe rwise the data read is not det erministic. Data will be v alid on the
port t
after the data is presented on the other port.
DDD
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted.
ACE
before the rising edge
SD
after CE or t
DOE
after OE is
input of the slave. Writing to slave devices must be delayed until after
the BUSY
may begin a write cycle during a contention situation.
input has settled (t
BLC
or t
). Otherwise, the slav e chip
BLA
Flow-Through Operation
The CY7C133/143 has a flow-through architecture that facilitates repeating (actually extending) an operation when a
BUSY
.
is recei ved b y a losi ng port. The BUSY si gnal should be
interpreted as a NO T READY . I f a BUSY
port should wait for BUSY
to go inactive, and then extend the
to a port is activ e , the
operation it was performing for another cycle. The timing diagram titled, “Timing wavef orm with port to port delay” illustrates
the case where the right port is writing to an address and the
left port reads the same address. The data that the right port
has just written flows through to the left, and is valid either t
after the fal ling ed ge of the write st robe of t he left port, or t
after the data being written becomes stable.
Data Retention Mode
The CY7C133/143 is designed with battery backup in mind.
Data retent ion voltage and suppl y cur r ent ar e guaran tee d ov e r
temperature. The following rules insure data retenti on:
1. Chip enable (C E
in V
to VCC – 0.2V .
CC
must be kept between VCC – 0.2V and 70% of VCC
2. CE
) must be held HIGH during data retention, with-
during the power-up and power-down tra nsitions.
3. The RAM can begin operation >t
after VCC reaches the
RC
minimum operating voltage (4.5 volts).
Timing
DDD
DDD
Busy
The CY7C133 (master) pr ovid es on- chip arbit r ation to reso lv e
simultaneous memory location access (contention). Ta b l e 2
shows a summery of conditions w here BUSY
ports’ CE
s are asserted and an address match occurs within tPS of
each other, the busy logic will determine which port has access. If t
is asserted . I f b o t h
PS
is violated, one port will definitely gain permission to the location, but
which one is not predi ctable. BUSY
address match or t
afte r CE is taken LOW . The results of all eight
BLC
arbitration possibilities are summarized in Table 3. BUSY
will be asser ted t
after an
BLA
is an open
drain output and requires a pull-up resistor.
One master and as many slaves as necessary may be con-
nected in parallel to expand the data bus width i n 16 bit increments. The BUSY
output of the master is connected to the BU SY
Parameter Test Conditions
ICC
DR1
Note:
26. CE
= VCC, Vin = GND to VCC, TA = 25°C. This parameter is guara nteed b ut not
tested.
@ VCCDR = 2V 1.5 mA
[26]
Max. Unit
11
T able 1. Non-Contending Read/Write Control
Control I/O
R/W
LB
R/W
UB
CE OE I/O0–I/O
8
I/O9–I/O
17
Operation
X X H X High Z High Z Deselected: Power-Do wn
L L L X Data In Data In Write to Both Bytes
L H L L Data In Data Out Write Lo wer Byte, Read Upper Byte
H L L L Data Out Data In Read Lower Byte, Write Upper Byte
L H L H Data In High Z Write to Lower Byte
H L L H High Z Data In Write to Upper Byte
H H L L Data Out Data Out Read to Bot h By te s
H H L H High Z High Z High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs Outputs
CY7C133
CY7C143
L
CE
R
Address
Address
L
R
BUSY
L
BUSY
R
X X No Match H H Normal
H X Match H H N o rmal
X H Match H H Normal
L L Match Note 27 Note 27 Write Inhibit
Notes:
27. The loser of the port arbitration will receive BUSY
28. Writes are inhibited to the left port when BUSY
= “L” (BUSYL or BUSYR = “L”). BUSYL and BUSYR cannot both be LOW simultaneously.
is LOW. Writes are inhibited to the right port when BUSYR is LOW.
L
32-Bit Master/Slave D u al -Port Memo r y Systems
R/W
BUSY
LEFT
CY7C133
5V
R/W
CY7C143
BUSY BUSY
R/W
5V
RIGHT
FunctionCE
[28]
R/W
BUSY
C133-14
12
Table 3. Arbitration Results
CY7C133
CY7C143
Port
Case
1 Read Read L Both ports read
2 Read Read R Both ports read
3 Read Write L L port reads OK R port write inhibited
4 Read Write R R port writes OK L port data may be invalid
5 Write Read L L port writes OK R port data may be invalid
6 Write Read R R port reads OK L port write inhibited
7 Write Write L L port writes OK R port write inhibited
8 Write Write R R port writes OK L port write inhibited
Winning
Port ResultLeft Right
Ordering Information
2K x16 Master Dual-Port SRAM
Speed
(ns) Ordering Code
25 CY7C133-25JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
CY7C133-25JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
35 CY7C133-35JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
CY7C133-35JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
55 CY7C133-55JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
CY7C133-55JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
Package
Name Package Type
Operating
Range
2K x16 Slave Dual-Port SRAM
Speed
(ns)
25 CY7C143-25JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
35 CY7C143-35JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
55 CY7C143-55JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
Document #: 38-00414-B
Ordering Code
CY7C143-25JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
CY7C143-35JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
CY7C143-55JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
Package
Name
Packag e Type
Operating
Range
13
Package Diagram
CY7C133
CY7C143
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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