Cypress Semiconductor CY7C1334H Specification Sheet

CY7C1334H

s

C

2-Mbit (64K x 32) Pipelined SRAM with

NoBL™ Architecture

Features

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use OE

• Byte Write capability

• 64K x 32 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed write

• Asynchronous output enable (OE

)

• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Logic Block Diagram

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADDRESS

ADV/LD

C

WRITE ADDRESS

REGISTER 2

A1

D1

A0

BURST

D0

LOGIC

CLK

A0, A1, A

MODE

EN

C

Functional Description

[1]

The CY7C1334H is a 3.3V/2.5V, 64K x 32
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)

Write operations are controlled by the four Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:D]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.

A1'

Q1

A0'

Q0

) signal,

ADV/LD

BWA

BW

B

BW

C

BW

D

WE

CE1
CE2
CE3

OE

ZZ

READ LOGIC

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05678 Rev. *B Revised February 6, 2006

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

SLEEP

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O

S

U
T

E

P

N

U
T

S
E

R
E
G

A

M

E

I
S

T

P

E

S

R

S

E

INPUT

REGISTER 0

O

D

U
T

A

P

T

U

A

T
B

S

U

T

F

E

F

E

E

R

R

S

I

E

N
G

E

DQ

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CY7C1334H

.

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time (tCO) 3.5 4.0 ns
Maximum Operating Current (IDD) 240 225 mA
Maximum CMOS Standby Current 40 40 mA

Pin Configuration

100-Pin TQFP Pinout

BYTE C

BYTE D

V
V

V
V

V
V

V
V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V
NC

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

NC

DD

SS

1CE2

A

A

99989796959493

100

BWDBWCBWBBWACE3VDDV

CE

9291908988

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13

CY7C1334H

14
15
16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

SS

CLKWECEN

OE

ADV/LD

NC/18M

A

NC/9M

A

87868584838281

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V

ZZ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

BYTE B

B
B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

A

A

MODE

Document #: 38-05678 Rev. *B Page 2 of 13

50

A1A

0

A

A

NC/144M

NC/288M

SS

DD

V

V

NC/36M

NC/72M

A

A

A

A

A

A

NC/4M

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CY7C1334H

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

[A:D]

Input-

Synchronous

WE Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

CEN Input-

Synchronous

ZZ Input-

Asynchronous

DQs I/O-

Synchronous

MODE Input

Strap pin

V
V

V
V

DD
DDQ

SS
SSQ

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Ground Ground for the device.

I/O Ground Ground for the I/O circuitry. Should be connected to the ground of the system

NC No Connects. Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN

is asserted LOW) the internal burst counter is advanced. When LOW , a
new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.

CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE

is masked during the data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected to
V

or left floating.

SS

Bidirectional Data I/O Lines. As input s, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
by OE

and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ
during the data portion of a write sequence, during the first clock when emerging from a
deselected state, and when the device is deselected, regardless of the state of OE

during the clock rise of the read cycle. The direction of the pins is controlled

[16:0]

are placed in a tri-state condition. The outputs are automatically tri-stated

s

.

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V
leaved burst sequence.

or left floating selects inter-

DD

Power supply for the I/O circuitry.

1G are address expansion pins and are not internally connected to the die.

Document #: 38-05678 Rev. *B Page 3 of 13

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CY7C1334H

Functional Overview

The CY7C1334H is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).

Accesses can be initiated by asserting all three Chip Enables
(CE

, CE2, CE3) active at the rising edge of the clock. If Clock

1

Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:D]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted

and the internal control logic. OE

will increment the internal burst counter regardless of

the state of Chip Enables inputs or WE

. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs

are ALL asserted active, and (3) the write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQs
DQP
(Read/Write/Deselect) is latched into the Address Register

. In addition, the address for the subsequent access

[A:D]

input signal. This

and

(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs

for Byte Write operations, see Write Cycle Description table for

(or a subset

details) inputs is latched into the device and the write is
complete.

The data written during the Write operation is controlled by
BW
capability that is described in the Write Cycle Description table.

signals. The CY7C1334H provides Byte Write

[A:D]

Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
desired bytes. Bytes not selected during a Byte Write

) input will selectively write to only the

[A:D]

operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.

Because the CY7C1334H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE

) can be deasserted HIGH
before presenting data to the DQs. Doing so will tri-state the
output drivers. As a safety precaution, DQs are automatically
tri-stated during the data portion of a Write cycle, regardless of
the state of OE.

Burst Write Accesses

The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.

inputs must be driven in each cycle of the burst write

[A:D]

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Document #: 38-05678 Rev. *B Page 4 of 13

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