CY7C1334H
s
C
2-Mbit (64K x 32) Pipelined SRAM with
NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable (OE
)
• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
Logic Block Diagram
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADDRESS
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1
A0
BURST
D0
LOGIC
CLK
A0, A1, A
MODE
EN
C
Functional Description
[1]
The CY7C1334H is a 3.3V/2.5V, 64K x 32
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
) and a Write Enable (WE) input. All writes are
[A:D]
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
) signal,
ADV/LD
BWA
BW
B
BW
C
BW
D
WE
CE1
CE2
CE3
OE
ZZ
READ LOGIC
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05678 Rev. *B Revised February 6, 2006
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
SLEEP
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
M
E
I
S
T
P
E
S
R
S
E
INPUT
REGISTER 0
O
D
U
T
A
P
T
U
A
T
B
S
U
T
F
E
F
E
E
R
R
S
I
E
N
G
E
DQ
[+] Feedback
CY7C1334H
.
Selection Guide
166 MHz 133 MHz Unit
Maximum Access Time (tCO) 3.5 4.0 ns
Maximum Operating Current (IDD) 240 225 mA
Maximum CMOS Standby Current 40 40 mA
Pin Configuration
100-Pin TQFP Pinout
BYTE C
BYTE D
V
V
V
V
V
V
V
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
V
NC
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
NC
NC
NC
DD
SS
1CE2
A
A
99989796959493
100
BWDBWCBWBBWACE3VDDV
CE
9291908988
1
C
C
2
3
4
5
C
C
C
C
6
7
8
9
10
11
C
C
12
13
CY7C1334H
14
15
16
17
D
D
18
19
20
21
D
D
D
D
22
23
24
25
26
27
D
D
28
29
30
SS
CLKWECEN
OE
ADV/LD
NC/18M
A
NC/9M
A
87868584838281
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC
DDQ
SSQ
SSQ
DDQ
SS
DD
DDQ
SSQ
SSQ
DDQ
B
B
BYTE B
B
B
B
B
B
B
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243444546474849
A
A
MODE
Document #: 38-05678 Rev. *B Page 2 of 13
50
A1A
0
A
A
NC/144M
NC/288M
SS
DD
V
V
NC/36M
NC/72M
A
A
A
A
A
A
NC/4M
[+] Feedback
CY7C1334H
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
BW
[A:D]
Input-
Synchronous
WE Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CE
CE
CE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
OE Input-
Asynchronous
CEN Input-
Synchronous
ZZ Input-
Asynchronous
DQs I/O-
Synchronous
MODE Input
Strap pin
V
V
V
V
DD
DDQ
SS
SSQ
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Ground Ground for the device.
I/O Ground Ground for the I/O circuitry. Should be connected to the ground of the system
NC No Connects. Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW , a
new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select/deselect the device.
1
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE
is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected to
V
or left floating.
SS
Bidirectional Data I/O Lines. As input s, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ
during the data portion of a write sequence, during the first clock when emerging from a
deselected state, and when the device is deselected, regardless of the state of OE
during the clock rise of the read cycle. The direction of the pins is controlled
[16:0]
are placed in a tri-state condition. The outputs are automatically tri-stated
s
.
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
leaved burst sequence.
or left floating selects inter-
DD
Power supply for the I/O circuitry.
1G are address expansion pins and are not internally connected to the die.
Document #: 38-05678 Rev. *B Page 3 of 13
[+] Feedback
CY7C1334H
Functional Overview
The CY7C1334H is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN
). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
) is active LOW and ADV/LD is asserted LOW,
). BW
can be used to
[A:D]
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
and the internal control logic. OE
will increment the internal burst counter regardless of
the state of Chip Enables inputs or WE
. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQs
DQP
(Read/Write/Deselect) is latched into the Address Register
. In addition, the address for the subsequent access
[A:D]
input signal. This
and
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs
for Byte Write operations, see Write Cycle Description table for
(or a subset
details) inputs is latched into the device and the write is
complete.
The data written during the Write operation is controlled by
BW
capability that is described in the Write Cycle Description table.
signals. The CY7C1334H provides Byte Write
[A:D]
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
desired bytes. Bytes not selected during a Byte Write
) input will selectively write to only the
[A:D]
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Because the CY7C1334H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
) can be deasserted HIGH
before presenting data to the DQs. Doing so will tri-state the
output drivers. As a safety precaution, DQs are automatically
tri-stated during the data portion of a Write cycle, regardless of
the state of OE.
Burst Write Accesses
The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD
must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.
inputs must be driven in each cycle of the burst write
[A:D]
is driven HIGH on the subsequent clock
, CE2, and CE3) and WE inputs are
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Document #: 38-05678 Rev. *B Page 4 of 13
[+] Feedback
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A0
Cycle Description Truth Table
DD
)
Third
Address
A1, A0
[2, 3, 4, 5, 6, 7, 8]
Fourth
Address
A1, A0
CY7C1334H
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Operation
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H Sleep MODE None X H X X X X X X Tri-State
Address
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW. CE
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQ pins are controlled by the current cycle and the OE
6. CEN
= H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
8. OE
OE is inactive or when the device is deselected, and DQs = data when OE is active.
, and WE. See Write Cycle Descriptions table.
[A:D]
stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
signal. OE is asynchronous and is not sampled with the clock.
.
= Tri-State when
[A:D]
Document #: 38-05678 Rev. *B Page 5 of 13
[+] Feedback
CY7C1334H
Write Cycle Description
Function WE BW
[2, 3]
D
BW
C
BW
B
BW
A
Read H X X X X
Write − No bytes written L H H H H
Write Byte A − (DQA) LHHHL
Write Byte B − (DQ
)LHHLH
B
Write Bytes A, B L H H L L
Write Byte C − (DQ
)LHLHH
C
Write Bytes C,A L H L H L
Write Bytes C, B L H L L H
Write Bytes C, B, A L H L L L
Write Byte D − (DQ
)LLHHH
D
Write Bytes D, A L L H H L
Write Bytes D, B L L H L H
Write Bytes D, B, A L L H L L
Write Bytes D, C L L L H H
Write Bytes D, C, A L L L H L
Write Bytes D, C, B L L L L H
Write All Bytes L L L L L
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 40 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ inactive to exit sleep current This parameter is sampled 0 ns
ns
ns
ns
Document #: 38-05678 Rev. *B Page 6 of 13
[+] Feedback
CY7C1334H
Maximum Rating
(Above which the useful life may be impaired. For user guidelines not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on V
Supply Voltage on V
Relative to GND......... −0.5V to +4.6V
DD
Relative to GND.......−0.5V to +V
DDQ
DD
DC Voltage Applied to Outputs
in Tri-State................................................ −0.5V to V
DDQ
+ 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage....................................... −0.5V to V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l 0°C to +70°C 3.3V - 5%/+10% 2.5V - 5% to
Ind’l –40°C to +85°C
[9, 10]
Ambient
Temperature (TA) V
DD
+ 0.5V
DD
V
DDQ
V
DD
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625 V
V
OH
V
OL
V
IH
V
IL
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
Output LOW Voltage for 3.3V I/O, I
for 2.5V I/O, I
Input HIGH Voltage
[9]
for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V
Input LOW Voltage
[9]
for 3.3V I/O –0.3 0.8 V
= –4.0 mA 2.4 V
OH
= –1.0 mA 2.0
OH
= 8.0 mA 0.4 V
OL
= 1.0 mA 0.4
OL
+ 0.3V
DD
for 2.5V I/O –0.3 0.7
I
X
I
OZ
I
DD
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
9. Overshoot: V
10.T
Power-up
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply
Current
Automatic CE
Power-Down
Current—TTL Inputs
Automatic CE
Power-Down
Current—CMOS Inputs
Automatic CE
Power-Down
Current—CMOS Inputs
Automatic CE
Power-Down
Current—TTL Inputs
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
V
= Max., I
DD
f = f
MAX
V
= Max, Device
DD
Deselected,
≥ VIH or VIN ≤ V
V
IN
f = f
MAX
V
= Max, Device
DD
Deselected, V
> V
V
IN
V
= Max, Device
DD
Deselected, or V
V
> V
IN
f = f
MAX
V
= Max, Device
DD
Deselected,
V
≥ VIH or VIN ≤ VIL, f = 0
IN
(min.) within 200 ms. During this time VIH < VDD and V
DD
DDQ
SS
DD
SS
DD
Output Disabled −5 5 µA
DDQ,
= 1/t
OUT
CYC
= 0 mA,
6-ns cycle, 166 MHz 240 mA
7.5-ns cycle, 133 MHz 225 mA
6-ns cycle, 166 MHz 100 mA
7.5-ns cycle, 133 MHz 90 mA
= 1/t
IL
CYC
All speeds 40 mA
≤ 0.3V or
IN
– 0.3V, f = 0
DDQ
6-ns cycle, 166 MHz 85 mA
≤ 0.3V or
DDQ
= 1/t
– 0.3V
CYC
IN
7.5-ns cycle, 133 MHz 75 mA
All Speeds 45 mA
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
DDQ
< V
DD
–5 5 µA
−30 µA
−5 µA
/2).
CYC
.
5 µA
30 µA
V
Document #: 38-05678 Rev. *B Page 7 of 13
[+] Feedback
CY7C1334H
Capacitance
[11]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Thermal Resistance
Clock Input Capacitance 5 pF
Input/Output Capacitance 5 pF
[11]
V
V
DD
DDQ
= 3.3V,
= 2.5V
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
0
3.3V
= 50Ω
R
VL= 1.5V
(a) (b)
= 50Ω
L
OUTPUT
INCLUDING
JIG AND
5pF
SCOPE
R = 317Ω
R = 351Ω
V
DDQ
GND
≤ 1 ns
100 TQFP
100 TQFP
Package Unit
ALL INPUT PULSES
10%
90%
Max. Unit
5pF
30.32 °C/W
6.85 °C/W
90%
10%
≤ 1 ns
(c)
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
= 50Ω
L
2.5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R =1538Ω
(a) (b)
Notes:
11.Tested initially and after any design or process changes that may affect these parameters.
V
GND
DDQ
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Document #: 38-05678 Rev. *B Page 8 of 13
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CY7C1334H
Switching Characteristics Over the Operating Range
[12, 13]
166 MHz 133 MHz
Parameter Description Min. Max. Min. Max. Unit
t
POWER
VDD (typical) to the First Access
[14]
11ms
Clock
t
CYC
t
CH
t
CL
Clock Cycle Time 6.0 7.5 ns
Clock HIGH 2.5 3.0 ns
Clock LOW 2.5 3.0 ns
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Data Output Valid after CLK Rise 3.5 4.0 ns
Data Output Hold after CLK Rise 1.5 1.5 ns
Clock to Low-Z
Clock to High-Z
[15, 16, 17]
[15, 16, 17]
00ns
3.5 4.0 ns
OE LOW to Output Valid 3.5 4.0 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
[15, 16, 17]
[15, 16, 17]
00ns
3.5 4.0 ns
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Address Set-up before CLK Rise 1.5 1.5 ns
ADV/LD Set-up before CLK Rise 1.5 1.5 ns
GW, BW
Set-up before CLK Rise 1.5 1.5 ns
[A:D]
CEN Set-up before CLK Rise 1.5 1.5 ns
Data Input Set-up before CLK Rise 1.5 1.5 ns
Chip Enable Set-Up before CLK Rise 1.5 1.5 ns
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Notes:
12.Test conditions shown in (a), (b) and (c) of AC Test Loads.
13.Timing reference level is 1.5V when V
14.This part has a voltage regulator internally; t
can be initiated.
, t
15.t
16.At any given voltage and temperature, t
17.This parameter is sampled and not 100% tested.
, t
CHZ
CLZ
OELZ
data bus. These specifications do not imply a bus contention condition, but ref lect p arame te rs guarant eed over worst case user condit ions. Device is d esigned
to achieve Tri-State prior to Low-Z under the same system conditions
Address Hold after CLK Rise 0.5 0.5 ns
ADV/LD Hold after CLK Rise 0.5 0.5 ns
GW, BW
Hold after CLK Rise 0.5 0.5 ns
[A:D]
CEN Hold after CLK Rise 0.5 0.5 ns
Data Input Hold after CLK Rise 0.5 0.5 ns
Chip Enable Hold after CLK Rise 0.5 0.5 ns
, and t
= 3.3V and 1.25V when V
DDQ
are specified with AC test conditions shown in p art (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
OEHZ
is the time that the power needs to be supplie d above V
POWER
is less than t
OELZ
and t
= 2.5V.
DDQ
is less than t
CHZ
minimum initially before a Read or Write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
Document #: 38-05678 Rev. *B Page 9 of 13
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Switching Waveforms
123456789
10
I
t
CENS
t
CES
[18, 19, 20]
t
CENH
t
CEH
Read/Write Timing
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
CY7C1334H
t
CYC
t
t
CL
CH
ADDRESS
Data
n-Out (DQ)
OE
A1 A2
t
t
AH
AS
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
D(A2+1)
READ
Q(A4)
CLZ
t
BURST
READ
Q(A4+1)
DOH
A5 A6 A7
t
OEHZ
t
WRITE
D(A5)
OEV
t
OELZ
t
CHZ
Q(A4+1)
t
DOH
READ
Q(A6)
DON’T CARE UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
18.
19.When CE
20.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are opt ional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
WRITE
D(A7)
Q(A6)
DESELECT
Document #: 38-05678 Rev. *B Page 10 of 13
[+] Feedback
Switching Waveforms (continued)
45678910
123
A
NOP, STALL, and Deselect Cycles
[18, 19, 21]
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
CY7C1334H
ADDRESS
A1
A2
Data
In-Out (DQ)
READ
ZZ Mode Timing
CLK
D(A1)
[22, 23]
Q(A2)
t
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
ZZ
t
ZZI
I
DDZZ
A3 A4
D(A1) Q(A2) Q(A3)
STALL NOP READ
READ
Q(A3)
WRITE
D(A4)
STALLWRITE
A5
D(A4)
Q(A5)
Q(A5)
DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
t
ZZREC
t
RZZI
DESELECT or READ Only
t
CHZ
Outputs (Q)
Notes:
21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN
22.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23.I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05678 Rev. *B Page 11 of 13
High-Z
DON’T CARE
being used to create a pause. A write is not performed during this cycle.
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CY7C1334H
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com
Speed
(MHz) Ordering Code
Package
Diagram Package Type
166 CY7C1334H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1334H-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
133 CY7C1334H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1334H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
Package Diagram
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
for actual products offered”.
Operating
Range
1.40±0.05
81
80
0.30±0.08
20.00±0.10
22.00±0.20
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0.25
0°-7°
0.60±0.15
1.00 REF.
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
12°±1°
(8X)
0.10
51-85050-*B
0.20 MAX.
1.60 MAX.
SEE DETAIL
A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05678 Rev. *B Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1334H
Document History Page
Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05678
REV. ECN NO. Issue Date
** 347357 See ECN PCI New Data Sheet
*A 424820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
*B 459347 See ECN NXR Converted from Preliminary to Final
Orig. of
Change Description of Change
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
Replaced Package Name column with Package Diagram in the Ordering
DDQ
< V
DD to VDDQ
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Included 2.5V I/O option
Updated the Ordering Information table.
< V
DD
Document #: 38-05678 Rev. *B Page 13 of 13
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