Cypress Semiconductor CY7C133-35JC, CY7C133-25JI, CY7C133-25JC, CY7C133-55JC, CY7C133-35JI Datasheet

CY7C133
CY7C143

2K x 16 Dual-Port Static RAM

Features

• True dual-ported memory cells which allow
simultaneous reads of the same memory location

• 2K x 16 organizat ion

• 0.65-micron CMOS for optimum sp eed/power

• High-speed access: 25/35/55 ns

• Low op e rating pow er: I

= 150 mA (typ.)

CC

• Fully asy nchronous operation

• Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143

• BUSY input flag on CY7C133; BUSY output flag on
CY7C143

• Available in 68-pin PLCC

• Pin-compati ble and f unction all y equiva len t to IDT713 3
and IDT7143

Logic Block Diagram

CE

L

R/W

LUB

R/W

LLB

OE

L

Functional Description

The CY7C133 and CY7C143 are high- speed CMOS 2K b y 16
dual-port static RAMs. Tw o ports are provided permitti ng inde­pendent access to any locat ion in memory. T he CY7C133 can
be utilized as either a stand-alone 16-bit dual-port static RAM
or as a master dual-port RAM in conjunct ion with the CY7C143
slave dual-port device in systems requiring 32-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.

Each port has independent control pins; Chip Enable (CE
Write Enable (R/W
signals that the port is trying to access the sam e location cur­rently being accessed by the other port. An automatic pow­er-down feature is controlled independently on each port by
the Chip Enable (CE

The CY7C133 and CY7C143 are available in 68-pin PLCC.

, R/WLB), and Output Enab le (OE). BUSY

UB

) pin.

CE

R

R/W

RUB

R/W

RLB

OE

R

),

I/O8L– I/O

15L

I/O0L– I/O

7L

[1]

BUSY

L

A

10L

A

0L

Note:

1. CY7C133 (Master): BUSY

is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.

ADDRESS

DECODER

Cypress Semiconductor Corporation

I/O8R– I/O

I/O0R– I/O

[]

1

BUSY

R

A

10R

A

0R

15R

7R

C133-1

R/W

R/W

CONTROL

CE

L

OE

L

LUB

LLB

I/O

MEMORY

ARRAY

ARBITRATION

LOGIC

(CY7C133ONLY)

I/O

CONTROL

ADDRESS

DECODER

CE

R

OE

R

R/W

RUB

R/W

RLB

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 14, 1999

Pin Configuration

I/O
I/O
I/O
I/O
I/O
I/O

I/O

V

GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

10L
11L
12L
13L
14L
15L

CY7C133
CY7C143

68-Pin

LCC/PLCC

Top View

LLB

I/O

I/O

1L

15R

I/O

GND

LUB

0L

CC

V

R/W

L

10L

R/W

OE

R/W

67

R

10R

RLB

RUB

OE

A

R/W

7LA8LA9L

A

A

A

60

6L

A

59

5L

A

58

4L

A

57

3L

A

56

2L

A

55

1L

A

54

0L

BUSY

53
52
51
50
49
48

47
46
45
44

6R

7RA8RA9R

A

A

CE

CE

BUSY
A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

L

L

R

R

C133-2

8L

7L

6L

5L

4L

3L

I/O

I/O

I/O

987 6

9L

10
11
12
13
14
15
16

CC

17
18

0R

19

1R

20

2R

21

3R

22

4R

23

5R

24

6R

25

7R

26

2728 29 30

9R

8R

10R

I/O

I/O

I/O

2L

I/O

I/O

I/O

I/O

5432168 666564636261

7C133
7C143

3132 33 34 35 36 37 38 39 40 41 42 43

14R

13R

12R

11R

I/O

I/O

I/O

I/O

Selection G uide

7C133-25
7C143-25

Maximum Access Time (ns) 25 35 55
Typical Operating Current ICC (mA) 170 160 150
Typical Standby Current for I

Maximum Ratings

(Abov e which the useful life m ay be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Po wer Applied..................................................−55°C to +125°C

(mA) 40 30 20

SB1

DC Input Voltage.................................................−3.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ................................... .. ..... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............. .......................... ............. >200 mA

Operating Range

Supply Voltage to Ground Potential

(Pin 48 to Pin 24).................................................−0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial

7C133-35
7C143-35

7C133-55
7C143-55

Ambient

Temperature V

−40°

C to +85°C 5V ± 10%

CC

2

CY7C133
CY7C143

Electrical Characteristics

Over the Operating Range

Parameter Description Test Co ndit ions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

OS

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

2. BUSY

3. Duration of the short circuit should not exceed 30 seconds.

4. Tested initially and after any design or process changes that may affect these parameters.

5. At f=f

MAX

Output HIGH Voltage VCC = Min.,

I

= –4.0 mA

OH

Output LOW Voltage IOL = 4.0 mA 0.4 V

IOL = 16.0 mA

[2]

Input HIGH Voltage 2.2 V
Input LOW Voltage 0.8 V
Input Leakage Current GND < VI < V

CC

Output Leakage Current GND < VO < VCC, Output Disabled
Output Short Circuit

[3,4]

Current
VCC Operating Supply Cur-

rent

Standby Curr ent Both Ports,

VCC = Max.,
V

= GND

OUT

CE = VIL,
Outputs Open,
f = f

MAX

[5]

CEL and CER > VIH, f = f

TTL Inputs
Standby Current One Port,

TTL Inputs
Standby Curr ent Both Ports,

CMOS Inputs

Standby Current One Port,
CMOS Inputs

pin only .

, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.

CEL or CER > VIH, Active Port Out­puts Open, f = f

MAX

[5]

Both Ports CEL and CER > VCC –

0.2V , V
f = 0

> VCC – 0.2V or VIN < 0.2V ,

IN

One Port CEL or CER > VCC – 0.2V,
V

> VCC – 0.2V or

IN

V

< 0.2V, Active P ort Outputs Open,

IN

[5]

f = f

MAX

MAX

7C133-25
7C143-25

2.4 V

−5

−5

Com’l 170 250 mA
Ind. 170 290

[5]

Com’l 40 60 mA
Ind. 40 75
Com’l 100 140 mA
Ind. 100 160
Com’l 3 15 mA
Ind. 3 15

Com’l 90 120 mA

Ind. 90 140

0.5

+5
+5

−200

UnitMin. Typ. Max.

µA
µA

mA

3

CY7C133
CY7C143

Electrical Characteristics

Over the Operating Range (continued)

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

Output HIGH Voltage VCC = Min.,

I

= –4.0 mA

OH

Output LOW Voltage IOL = 4.0 mA 0.4 0.4 V

I

= 16.0 mA

OL

[2]

Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Curr ent GND < VI < V
Output Leakage

GND < VO < VCC, Output Disabled −5+5−5 −5 µA

CC

Current

I

OS

I

CC

I

SB1

Output Short Circuit

[3,4]

Current
VCC Operating Supply

Current

Standby Current Both

VCC = Max.,
V

= GND

OUT

CE = VIL,
Outputs Open,
f = f

MAX

[5]

CEL and CER > VIH, f = f

Ports, TTL I nputs

I

SB2

I

SB3

I

SB4

Standby Current One
Port, TTL Inputs

Standby Current Both
Ports, CMOS Inputs

Standby Current One
Port, CMO S In p ut s

CEL or CER > VIH, Activ e P ort
Outputs Open, f = f

MAX

Both Ports CEL and CER >
V

- 0.2V, VIN > VCC – 0.2V

CC

or V

< 0.2V, f = 0

IN

One Port CEL or CER > VCC –

0.2V, V
V
Open, f = f

> VCC – 0.2V or

IN

< 0.2V , A c tive Port O u tp u t s

IN

MAX

[5]

7C133-35
7C143-35

7C133-55
7C143-55

UnitMin. Typ. Max. Min. Typ. Max.

2.4 2.4 V

0.5 0.5

−5+5−5+5µA

−200 −200 mA

Com’l 160 230 150 220 mA
Ind. 160 260 150 250

[5]

Com’l30502040mA

MAX

Ind. 30 65 20 55
Com’l 85 125 75 110 mA

[5]

Ind. 85 140 75 125
Com’l315315mA
Ind. 3 15 3 15

Com’l 80 105 70 90 mA

Ind. 80 120 70 105

Capacitance

[4]

Parameter Description Te st Condi tions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 10 pF
Output Capacitance 10 pF

AC Test Loads and Waveforms

5V

OUTPUT

30pF

INCLUDING

JIG AND

SCOPE

Equivalent to: TH ÉVENIN

OUTPUT 1.40V

R1893

(a)

Ω

R2
347

Ω

C133-2

EQUIVALENT

250

Ω

5V

OUTPUT

INCLUDING

JIG AND

SCOPE

5pF

R1893

(b)

3.0V

GND

<

3 ns

Ω

R2
347

10%

Ω

C133-3

ALL INPUT PULSES

90%

BUSY

OR
INT

90%

10%

< 3 ns

5V

281

30

pF

BUSY Output Load

(CY7C133ONLY)

C133-4

Ω

4

CY7C133
CY7C143

Switching Characteristics

Over the Operati n g Range

Parameter Description

[6]

7C133-25
7C143-25

7C133-35
7C143-35

7C133-55
7C143-55

UnitMin. Max. Min. Max. Min. Max.

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

Notes:

6. T est conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I

OL/IOH,

7. AC Test Conditions use V

8. At any given temperature and voltage condition for any given device, t

9. t

LZCE

voltage.

10. This parameter is guaranteed but not tested.

11. The internal write time of the memory is defined by the overlap of CS
can terminat e a wri te by goi ng HI GH. Th e data i np ut set -up an d hold timing sho ul d be re f ere nc ed to th e risin g edg e of th e si gn al th at te rmin at es the writ e .

Read Cycle Time 25 35 55 ns
Address to Data Valid

[7]

25 35 55 ns
Data Hold from Address Change 0 0 0 ns
CE LOW to Data Va lid
OE LOW to Data Valid
OE LOW to Lo w Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to H ig h Z
CE LOW to Po wer-Up
CE HIGH to Power-Down

[11]

[7]
[7]

[8, 9,10]

[8, 9,10]

[8, 9,1 0]

[8, 9,10]

[10]

[10]

25 35 55 ns

20 25 30 ns

3 3 3 ns

15 20 25 ns

3 5 5 ns

15 20 20 ns

0 0 0 ns

25 25 25 ns

Write Cycle Time 25 35 55 ns
CE LOW to Write End 20 25 40 ns
Address Set-Up to Write End 20 25 40 ns
Address Hold from Write End 2 2 2 ns
Address Set-Up to Write Start 0 0 0 ns
R/W Pulse Wi dth 20 25 35 ns
Data Se t- U p to Write End 15 20 20 ns
Data Hold from Write End 0 0 0 ns

and t

[9,10]
[9,10]

are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state

HZWE

0 0 0 ns

is less than t

LZCE

LOW and R/W LOW. Both signals m ust be LOW to initiate a write and either signal

15 20 20 ns

HZCE

and t

is less than t

LZOE

HZOE

.

R/W LOW to High Z
R/W HIGH to Low Z

and 30-pF load capacitance.

, t

, t

LZWE

HZOE

= 1.6V and VOL = 1.4V.

OH

, t

, t

LZOE

HZCE

5