Cypress Semiconductor CY7C1325L-80AC, CY7C1325L-50AC, CY7C1325L-117AC, CY7C1325L-100AC, CY7C1325-80AC Datasheet

256K x 18 Synchronous

3.3V Cache RAM

CY7C1325

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 10, 2000

Features

• Supports 117-MHz m icroprocessor cac he systems with
zero wait states

• 256K by 18 common I/O

• Fast clock-to-output times

—7.5 ns (117-MHz version)

• T wo-bit wrap-around counter supporting either inter­leaved or linear burst sequence

• Separate pro cessor and contro ller address strobe s pro­vides direct interface with the processor and external
cache controller

• Synchronous self-timed write

• Asynchr onous output enable

• I/Os capable of 2.5–3.3V operation

• JEDEC-standard pinout

• 100-pin TQFP packag ing

• ZZ “sleep” mode

Functional Description

The CY7C1325 is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap­tures the first address in a burst and increments the address
automatically for the rest of the burst access.

The CY7C1325 allows both an interleaved or linear burst se­quences, sele cted by the MODE input pin. A HIGH selects an
interleaved burst sequence, whi le a LOW s elects a linear burst
sequence. Burst accesses can be initiated wi th the Processor
Address Strobe (ADSP

) or the Cache Controller Address

Strobe (ADSC

) inputs. Address advancement is controlled by

the Address Advancement (ADV

) input.

A synchronous sel f-t imed wri te me chanism i s pro vided to sim ­plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.

CLK
ADV

ADSC

A

[17:0]

GW

BWE

BW

0

CE

1

CE

3

CE

2

OE

ZZ

BURST

COUNTER

ADDRESS

REGISTER

INPUT

REGISTERS

256K X 18

MEMORY

ARRAY

CLK

Q

0

Q

1

Q

D

CE

CE

CLR

SLEEP

CONTROL

DQ

DQ[15:8]
BYTEWRITE
REGISTERS

DQ[7:0]
BYTEWRITE
REGISTERS

D Q

ENABLE

REGISTER

D

Q

CE

CLK

18 18

18

16

16

18

(A0,A1)

2

MODE

ADSP

Logic Block Diagram

DQ

[15:0]

BW

1

DP

[1:0]

Selection Guide

7C1325-117 7C1325-100 7C1325-80 7C1325-50

Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operat ing Current (mA) 350 325 300 250
Maximum Standb y Curr ent (mA) 10.0 10.0 10.0 10.0

Intel and Pentium are registered trademarks of Intel Corporation.

CY7C1325

2

Pin Configurations

A5A4A3A2A1A

0

DNU

DNU

V

SS

V

DD

DNU

A

11

A12A13A14A

15

A

17

A10
NC
NC
V

DDQ

V

SS

NC
DP

0

DQ

7

DQ

6

V

SS

V

DDQ

DQ

5

DQ

4

V

SS

NC
V

DD

DQ

3

DQ

2

V

DDQ

V

SS

DQ

1

DQ

0

NC
NC
V

SS

V

DDQ

NC
NC
NC

NC

NC
NC

V

DDQ

V

SS

NC
NC

DQ

8

DQ

9

V

SS

V

DDQ

DQ

10

DQ

11

NC

V

DD

NC
V

SS

DQ

12

DQ

13

V

DDQ

V

SS

DQ

14

DQ

15

DP

1

NC

V

SS

V

DDQ

NC
NC
NC

A6

A7

CE

1CE2

NC

NC

BWS

1

BWS0CE3VDDV

SS

CLKGWBWEOEADSP

A8A

9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99989796959493929190898887868584838281

BYTE0

BYTE1

A

16

ADV

ADSC

ZZ

MODE

DNU

CY7C1325

100-Lead TQFP

CY7C1325

3

Pin Descriptions

Pin Number Name I/O Description

85 ADSC Input-

Synchronous

Address Strobe from Contro ller , sampled on t he rising edge of CLK. When asserted
LOW , A

[17:0]

is captured in the ad dress regis ters. A

[1:0]

are also loaded int o the bu rst

counter. When ADSP

and ADSC are both asserted, only ADSP is recognized.

84 ADSP Input-

Synchronous

Address Strobe f rom Processor , sampled on the rising edge of CLK. When asserted
LOW , A

[17:0]

is captured in the ad dress regis ters. A

[1:0]

are also loaded int o the bu rst

counter . When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP

is ignored when CE

1

is deasserted HIGH.

36, 37 A

[1:0]

Input-

Synchronous

A1, A0 address inputs , These inputs f eed the on-chip burs t counter as the LSBs as
well as being used to access a particular memory location in the memory arra y.

50–44,
80–82, 99,
100, 32–35

A

[17:2]

Input-

Synchronous

Address Inputs used in conjunction with A

[1:0]

to select one of the 256K address

locations. Sampl ed at the rising edge of the CLK, if CE

1, CE2,

and CE3 are sampled

active, and ADSP

or ADSC is active LOW.

94, 93 BWS

[1:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct b yte writes.
Sampled on the rising edg e. BWS

0

controls DQ

[7:0]

and DP0, BWS1 controls DQ

[15:8]

and DP

1

. See Write Cycle Descriptions table for further detai ls.

83 ADV Input-

Synchronous

Advance input used to advan ce the on-chip address counter . When L OW the internal
burst counter is advanced in a burst sequence . The burst sequence is selected using
the MODE input.

87 BWE Input-

Synchronous

Byte Write Enable Input , active LOW. Sampled on the rising edge of CLK. This si gnal
must be asserted LOW to conduct a byte write.

88 GW Input-

Synchronous

Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE

and BWS

[1:0]

. Global

writes override byte writes.
89 CLK Input-Clock Clock input. Used to capture all synchronous i nputs to the device .
98 CE

1

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

2

and CE3 to select/deselect the device . CE1 gates ADSP.

97 CE

2

Input-

Synchronous

Chip Enable 2 Input, act ive HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

1

and CE3 to select/des elect the device .

92 CE

3

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

1

and CE2 to select/deselect the device.

86 OE Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

pins. When LO W, the I/O pins behav e as output s. W hen deasserted HIGH, I/ O pins

are three-stated, and act as input data pins.
64 ZZ Input-

Asynchronous

Snooze Input. Active HIGH a synchronous. Whe n HIGH, the de vice enters a lo w-pow-

er standby mode in whic h all other inputs are ignored, but the data in the memory

array is mai ntained. Leaving ZZ floa ti ng or NC will default the device into an active

state. ZZ has an internal pull down.
31 MODE - Mode Input. Selects the burs t order of the devi ce. Tied HIGH select s the interlea ved

burst order. Pulled LOW selects the linear b urst order. Whe n lef t floating or NC,

defaults to interleaved burst order . Mode pin has an internal pull up.
23, 22, 19,

18, 13, 12, 9,
8, 73, 72, 69,
68, 63, 62,
59, 58

DQ

[15:0]

I/O-

Synchronous

Bidirectional Data I/O lines . As input s, t hey f e ed into an on- chip data register t hat is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in

the memory location specifi ed by A

[17:0]

during the previous clock rise of the read

cycle. The dir ection of the pins is controlled by OE

in conjunction with the int ernal

control logic. When OE

is asserted LOW, the pins behave as outputs. When HIGH,

DQ

[15:0]

and DP

[1:0]

are placed in a three-state condition. The outputs are automat-

ically three-s tat ed when a WRI TE cycle is detected.
74, 24 DP

[1:0]

I/O-

Synchronous

Bidirectional Data Parity li nes. These behave identical to DQ

[15:0]

described above.

These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65, 91V

DD

Pow er Supply Power supply inputs to the core of t he device. Should be connected to 3.3V power

supply.

CY7C1325

4

Functional Overview

All synchrono us inputs pass throu gh inp ut registe rs con trol led
by the rising edge of the clock. Maximum access delay from
the clock rise (t

CDV

) is 7.5 ns (117-MHz device).

The CY7C1325 sup ports secondary cache in systems utilizin g
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user select able, and is de­termined by sampling the MODE input. Accesses can be initi­ated with either the processor address strobe (ADSP

) or the

controller address strobe (ADSC

). Address advancement

through the burst sequence is controlled by the ADV

input. A
two-bit on -chip wraparou nd burs t counter captu res the fi rst ad­dress in a burst sequence and automatically increments the
addr e s s for the rest of the burst acce ss.

Byte write operations are qualified with the Byte Writ e Enable
(BWE

) and Byte Write Select (BWS

[1:0]

) inputs. A Global Write

Enable (GW

) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified wi th on-chip synchro­nous self-timed wri te circuitry.

Three synchronous chi p selects (CE

1

, CE2, CE3) and an asyn-

chronous output enable (OE

) provide for easy bank selection

and output three-state control. ADSP

is ignored if CE1 is

HIGH.

Single Read Accesses

A single re ad access is initiated when the following conditions
are satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all as-

serted active, and (2) ADSP

or ADSC is asserted LOW (if the

access is initiated by ADSC

, the write i nputs mus t be de assert­ed during this first cycle). The address presented to the ad­dress inputs is latc hed into the address register and the burst
counter/con trol logic and presented to the memory core . If th e
OE

input is asserted LOW , the requeste d data will be av ailab le

at the data outputs a maximum to t

CDV

after clock rise. ADSP

is ignored if CE1 is HIGH.

Single Write Accesses Initiat ed by ADSP

This access is initiated when the following conditions are sat­isfied at clock rise: (1) CE

1

, CE2, and CE3 are all asserted

active, and (2) ADSP

is asserted LOW. The addresses pre­sented are loaded into the address register and the burst
counter/control logi c and del ive red to the RAM cor e . The write
inputs (GW

, BWE, and BWS

[1:0]

) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS

0

controls DQ

[7:0]

and DP0 while

BWS

1

controls DQ

[15:8]

and DP1. All I/Os are three-stat ed dur­ing a byte write . Since thes e are common I/O de vic e, the asyn ­chronous OE

input signal must be deasserted and the I/Os
must be three-stated prior to the presentation of data to
DQ

[15:0]

and DP

[1:0]

. As a safety precaut ion, the data li nes are
three-stated once a write cycle is detected, regardless of the
state of OE

.

Single Write Accesses Initiated by ADSC

This write access is initia ted when t he f ol lowi ng con diti ons are
satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all asserted

active, (2 ) ADSC

is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input sign als (GW

, BWE, and BWS

[1:0]

)

indicate a write access. ADSC

is ignored if ADSP is active LOW.

The addresses pre sented are l oaded into the address register,
burst count er/co ntrol logi c and de liv er ed to the RAM co re. The
information presented to DQ

[15:0]

and DP

[1:0]

will be written
into the specified address location. Byte writes are allowed,
with BWS

0

controlling DQ

[7:0]

and DP0 while BWS1 controlling

DQ

[15:8]

and DP1. All I/Os are three-stated when a write is
detected, even a byte write. Since these are common I/O de­vice, the asynchronous OE

input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ

[15:0]

and DP

[1:0]

. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regard­less of the state of OE

.

5, 10, 17, 21,
26, 40, 55,
60, 67, 71,
76, 90

V

SS

Ground Ground for the device. Should be connected to ground of the system.

4, 11, 20, 27,
54, 61, 70,
77

V

DDQ

I/O Power

Supply

Pow er supply for the I/O circu itry . Should be connected to a 2.5 or 3.3V pow er supply .

1–3, 6, 7, 14,
16, 25,
28–30,
51–53, 56,
57, 66, 75,
78, 79,
95–96

NC - No connects.

38, 39, 42, 43DNU - Do not use pins. Shoul d be left unconnected or tied LOW.

Pin Descriptions

(continued)

Pin Number Name I/O Description

CY7C1325

5

Burst Sequences

This family of devices provide a 2-bit wrap-around burst
counter inside the SRAM. The burst counter is fed by A

[1:0]

,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will sel ect a l inear b urst sequence . A HIGH on
MODE will select an interleaved bur st order. Leaving MODE
unconnected will cause the devic e to defau lt to a i nter leaved
burst sequence.

Sleep Mode

The ZZ input pin is an as ynchrono us input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac­cesses pending when entering the “sleep” mode are not con­sidered valid nor is the completion of the operation guaran­teed. The device must be deselected prior to entering the
“sleep” mode. CE

1

, CE2, CE3, ADSP, and ADSC must remain

inactive for the duration of t

ZZREC

after the ZZ input returns

LOW.

Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

T able 2. Counter Implementation for a Linear Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10