Cypress Semiconductor CY7C1324L-80AC, CY7C1324L-50AC, CY7C1324L-117AC, CY7C1324L-100AC, CY7C1324-80AC Datasheet

3.3V 128K x 18 Synchronous
Cache RAM

CY7C1324

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 4, 1999

Features

• Supports 117-MHz m icroprocessor cac he systems with
zero wait states

• 128K by 18 common I/O

• Fast clock-to-output times

—7.5 ns (117 MHz)

• T wo-bit wrap-aroun d counter supporti ng either inter­leaved or linear burst sequence

• Separate pro cessor and contro ller address strobe s pro­vides direct interface with the processor and external
cache controller

• Synchronous self-timed write

• Asynchr onous output enable

• I/Os capable of 2.5–3.3V operation

• JEDEC-standard pinout

• 100-pin TQFP packag ing

• ZZ “sleep” mode

Functional Description

The CY7C1324 is a 3.3V, 128K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-c hip counter cap­tures the first address in a burst and increments the address
automatically for the rest of the burst access.

The CY7C1324 allows both interleaved or linear burst se­quences, selected by the MODE input pin. A HIGH input on
MODE selects an interleaved burst sequence, while a LOW
selects a linear b ur st sequenc e. Burst acc esses can be i ni tiat­ed with the Processor Address Strobe (ADSP

) or the cache

Controller Address Strobe (ADSC

) inputs. Address advance-

ment is controlled by the Address Advancement (ADV

) input.

A synchronous sel f-t imed wri te me chanism i s pro vided to sim ­plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.

Pin

CLK
ADV

ADSC

A

[16:0]

GW

BWE

BW

0

CE

1

CE

3

CE

2

OE

ZZ

BURST

COUNTER

ADDRESS

REGISTER

INPUT

REGISTERS

128K X 18

MEMORY

ARRAY

CLK

Q

0

Q

1

Q

D

CE

CE

CLR

SLEEP

CONTROL

DQ

DQ[15:8]
BYTEWRITE
REGISTERS

DQ[7:0]
BYTEWRITE
REGISTERS

D Q

ENABLE

REGISTER

D

Q

CE

CLK

18 18

17

15

15

17

(A0,A1)

2

MODE

ADSP

Logic Block Diagram

DQ

[15:0]

BW

1

DP

[1:0]

Selection G uide

7C1324–117 7C1324–100 7C1324–80 7C1324–50

Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operat ing Current (mA) 350 325 300 250
Maximum Standb y Curr ent (mA) 1.0 1.0 1.0 1.0
Pentium is a registered trademark of Intel Corporation.

CY7C1324

2

Pin Configuration

100-Lead TQFP

A5A4A3A2A1A

0

DNU

DNU

V

SS

V

DD

DNU

A

11

A12A13A14A

15

NC

A10
NC
NC
V

DDQ

V

SS

NC
DP

0

DQ

7

DQ

6

V

SS

V

DDQ

DQ

5

DQ

4

V

SS

NC
V

DD

DQ

3

DQ

2

V

DDQ

V

SS

DQ

1

DQ

0

NC
NC
V

SS

V

DDQ

NC
NC
NC

NC

NC
NC

V

DDQ

V

SS

NC
NC

DQ

8

DQ

9

V

SS

V

DDQ

DQ

10

DQ

11

NC

V

DD

NC
V

SS

DQ

12

DQ

13

V

DDQ

V

SS

DQ

14

DQ

15

DP

1

NC

V

SS

V

DDQ

NC
NC
NC

A6

A7

CE

1CE2

NC

NC

BWS

1

BWS0CE3VDDV

SS

CLKGWBWE

OE

ADSP

A8A

9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99989796959493929190898887868584838281

BYTE0

BYTE1

A

16

ADV

ADSC

ZZ

MODE

DNU

CY7C1324

CY7C1324

3

Functional Description

(continued)

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are sat­isfi ed at clock rise: (1) CE

1

, CE2, and CE3 are all asse rted

active, and (2) ADSP

is asserted LOW. The addresses pre­sented are loaded into the address register and the burst
counter/con trol log ic and del iv er ed to th e RAM core. The writ e
inputs (GW

, BWE, and BWS

[1:0]

) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS

0

controls DQ

[7:0]

and DP0 while

BWS

1

controls DQ

[15:8]

and DP1. All I/Os ar e thr ee-st ate d dur­ing a byte write. Since these are common I/O devices, the
asynchronous OE

input signal must be deasser ted and the
I/Os must be three-stated prior to the presentation of data to
DQ

[15:0]

and DP

[1:0]

. As a safety precaut ion , the data li nes are
three-stated once a write cycle is detected, regardless of the
state of OE

.

Single Write Accesses Initiated by ADSC

This write access i s ini tiated when the f ol lowi ng condi t ions ar e
satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all asserted

active, (2) ADSC

is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input signals (GW

, BWE, and BWS

[1:0]

)

indicate a write acces s. ADSC

is ignored if ADSP is active LOW .

The addresses pr esented are loaded int o the ad dress regist er ,
burst co unte r/contr ol logic and del iv ere d to t he RAM cor e. Th e
information presented to DQ

[15:0]

and DP

[1:0]

will be w ritten
into the specified address location. Byte writes are allowed,
with BWS

0

controlling DQ

[7:0]

and DP0 while BWS1 controllin g

DQ

[15:8]

and DP1. All I/Os are three-stated when a write is
detected, even a byte write. Since these are common I/O de­vices, the asynchronous OE

input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ

[15:0]

and DP

[1:0]

. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regard­less of the state of OE

.

Single Read Accesses

A single re ad access is initiated when the following conditions
are satisfied at clock rise: (1) CE

1

, CE2, and CE3 are all as-

serted active, and (2) ADSP

or ADSC is asserted LOW (if the

access is initiated by ADSC

, the write i nputs mus t be de assert­ed during this first cycle). The address presented to the ad­dress inputs is latc hed into the Address Register , burst count er
/control logic and presented to the memory core. If the OE

input is asserted LOW, the requested data will be available at
the data outputs a maximum to t

CDV

after cl ock r is e. ADSP is

ignored if CE

1

is HIGH.

Burst Sequences

This family of devices provide a 2-bit wrap around burst
counter inside t he SRAM. The burst counter is fed by A

[1:0]

,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will sele ct a l inear b u rst se quence. A HIG H on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause t he device to defaul t to a interleaved
burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous inpu t. Asserting a HIGH
input on ZZ pl aces the SRAM in a power conservation “sleep”
mode. Two clock cycles are required to enter into or exit from
this “sleep” mode . While in th is mode , dat a integ rity is guar an -
teed. Accesses pending when entering the “sleep” mode are
not considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE

1

, CE2, CE3, ADSP, and ADSC must re-

main inactive for the duration of t

ZZREC

after the ZZ input re-

turns low

T able 1. Counter Implementation for the Int el
Pentium®/80486 Processor’s Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

A

X + 1, Ax

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

T able 2. Counter Implementation for a Linear Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

A

X + 1

, A

x

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

CY7C1324

4

Cycle Description Table

[1, 2, 3]

Cycle Description

ADD

Used CE1CE3CE2ZZ ADSP ADSP ADV WE OE CLK DQ

Deselected Cycle, Power-down None H X X L X L X X X L-H High-Z
Deselected Cycle, Power-down None L X L L L X X X X L-H Hi gh-Z
Deselected Cycle, Power-down None L H X L L X X X X L-H High-Z
Deselected Cycle, Power-down None L X L L H L X X X L-H High-Z
Deselected Cycle, Power-down None X X X L H L X X X L-H High-Z
SNOOZE MODE, Power-down None X X X H X X X X X X HIGH-Z
READ Cycle, Begin Burst External L L H L L X X X L L-H Q
READ Cycle, Begin Burst External L L H L L X X X H L-H High-Z
WRITE Cycle, Begin Burst External L L H L H L X L X L-H D
READ Cycle, Begin Burst External L L H L H L X H L L-H Q
READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z
READ Cycle, Continue Burs t Next X X X L H H L H L L-H Q
READ Cycle, Continue Burs t Next X X X L H H L H H L-H High-Z
READ Cycle, Continue Burs t Next H X X L X H L H L L-H Q
READ Cycle, Continue Burs t Next H X X L X H L H H L-H High-Z
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Cur rent X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Cur rent X X X L H H H H H L-H High-Z
READ Cycle, Suspend Burst Cur rent H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Cur rent H X X L X H H H H L-H High-Z
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.

2. The SRAM always initiates a read cycle when ADSP

asserted, regardless of the state of GW, BWE, or BWS

[1:0].

Writes may occur only on subsequent clocks

after the ADSP

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE

is a “Don't Care” for the remainder of the write cycle.

3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.

CY7C1324

5

Pin Descriptions

TQFP Pin

Number

Name I/O Description

85 ADSC Input-

Synchronous

Address Strobe from Controller, sam pled on the rising edge of CLK. When asserted
LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also load ed into the burst

counter. When ADSP

and ADSC are both asserted, only ADSP is r e c o gnized.

84 ADSP Input-

Synchronous

Address Strobe f rom Processor, sampled on the rising edge of CLK. When asserted
LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also load ed into the burst

counter . When ADSP

and ADSC are both asserted, onl y ADSP is recogniz ed. ASDP

is ignored when CE

1

is deasserted HIGH.

36, 37 A

[1:0]

Input-

Synchronous

A1, A0 Address Inputs, These i nputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.

49–44,
80–82, 99,
100,
32–35

A

[16:2]

Input-

Synchronous

Address Inputs used i n conjunction with A

[1:0]

to select one of the 128K address

locations. Sampled at the rising edge of the CLK, if CE

1

, CE2, and CE3 are sampled

active, and ADSP

or ADSC is active LOW.

94, 93 BWS

[1:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge . BWS

0

controls DQ

[7:0]

and DP0, BWS1 controls DQ

[15:8]

and DP

1

. See Write Cycle Descriptions table for further details.

83 ADV Input-

Synchronous

Advance Input use d to advance the on-chip address cou nte r . When LO W t he int ernal
burst counte r is adv an ced in a bu rst sequ ence . The b urs t sequence is se lected using
the MODE input.

87 BWE Input-

Synchronous

Byte Write Enable In put, act iv e LO W. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.

88 GW Input-

Synchronous

Global Write Input, active LO W . Sampled on the rising edge of CLK. Thi s signal is used
to conduct a global write, independent of the state of BWE

and BWS

[1:0]

. Global writ es

override b yte writes.
89 CLK Input-Clock Clo ck Input. Used to capture all synchronous inputs to the device.
98 CE

1

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-

junction with CE

2

and CE3, to select/desele ct the device. CE1 gates ADSP.

97 CE

2

Input-

Synchronous

Chip Enable 2 Input, act ive HIGH. Sampled on the rising edge of CLK. Used in con-

junction with CE

1

and CE3 to select/deselect the device.

92 CE

3

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-

junction with CE

1

and CE2 to select/d eselect the de vice.

86 OE Input-

Asynchronous

Output Enabl e, async hronous input, a ctive LOW. Controls the di rection of the I/ O pins .

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are

three-stated, and act as input data pins.
64 ZZ Input-

Asynchronous

Snooze Input. Active HIGH a synchronous. When HIGH, the de vice enters a low-power

standby mo de in which all other inputs are ignored, but the data i n the memory arra y

is maintained. Leaving ZZ floating or NC will default the device into an active state.
31 MODE - Mode Input. Selects the bur st or der of the device. Tied HIGH selects the interleaved

burst order . Pulled LOW select s the linear burst or der. When left fl oating or NC, defaul ts

to interleaved burst order.
23, 22, 19,

18, 13, 12,
9, 8, 73,
72, 69, 68,
63, 62, 59,
58

DQ

[15:0]

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As output s , the y d elive r t he data co ntaine d in the

memory location specified by A

[17:0]

during the prev ious clock rise of the read cycle.

The direction of the pins is controlled by OE

in conjunction with the internal control

logic. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQ

[15:0]

and DP

[1:0]

are placed in a three-state condition. The outputs are automatically

three-stated when a WRITE cycle is detected.
74, 24 DP

[1:0]

I/O-

Synchronous

Bidirectional Data Parity lines. These behav e identical to DQ

[15:0]

described above.

These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65, 91V

DD

Po wer Supply Power supply inputs to the core of t he device. Should be connected to 3.3V power

supply.