Cypress Semiconductor CY7C1324H Specification Sheet

A

A
B

CY7C1324H

2-Mbit (128K x 18) Flow-Through Sync SRAM

Features

• 128K x 18 common I/O

• 3.3V core power supply

• 3.3V/2.5V I/O supply

• Fast clock-to-output times
— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

®

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP
package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1324H is a 128K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

Logic Block Diagram

first address in a burst and increments the address automati­cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW

[A:B]

nputs include the Output Enable

i

,

and

BWE

, ADSP,

ADV), Write Enables

and

), and Global Write (GW). Asynchronous

(OE)

and the ZZ pin

. The
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) or the cache Controller

) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

The CY7C1324H operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V or +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

0,A1,A

MODE

ADV

CLK

ADSC
ADSP

B

BW

BW

A

BWE

GW

CE

1

CE

2

CE

3

OE

ZZ

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS
REGISTER

DQB,DQP

B

WRITE REGISTER

A

,DQP

A

DQ

WRITE REGISTER

ENABLE

REGISTER

SLEEP

CONTROL

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

A[1:0]

DQB,DQP

B

WRITE DRIVER

A

,DQP

A

DQ

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

DQs
DQP
DQP

INPUT

REGISTERS

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00208 Rev. *B Revised April 26, 2006

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CY7C1324H

Selection Guide

133 MHz Unit

Maximum Access Time 6.5 ns
Maximum Operating Current 225 mA
Maximum Standby Current

Pin Configurations

100-pin TQFP Pinout

40 mA

BYTE B

V

DDQ

V

DQ
DQ

V

V

DDQ

DQ
DQ

V
NC

V
DQ
DQ

V

DDQ

V
DQ
DQ

DQP

V

V

DDQ

NC
NC
NC

SS

NC
NC

SS

NC

DD

SS

SS

NC

SS

NC
NC
NC

A

100

CE

CE

NC

NC

99989796959493929190898887868584838281

2

1

A

1
2
3
4
5
6
7
8

B

9

B

10
11
12

B

13

B

14
15
16
17
18

B

19

B

20
21
22

B

23

B

24

B

25
26
27
28
29
30

3

BBWA

CE

BW

VDDV

CY7C1324H

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A
NC

NC
V

DDQ

V

SS

NC
DQP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

B
A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

MODE

Document #: 001-00208 Rev. *B Page 2 of 15

AAAAA1A

50

0

NC/72M

NC/36M

SS

DD

V

V

NC/18M

NC/9M

AAAAA

A

NC/4M

[+] Feedback

CY7C1324H

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BWA,BW

B

Input-

Synchronous

GW Input-

Synchronous

BWE Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP Input-

Synchronous

ADSC Input-

Synchronous

ZZ Input-

Asynchronous

DQs
DQP

V

DD

V

SS

V

DDQ

A,

DQP

B

I/O-

Synchronous

Power

Supply

Ground Ground for the device.

I/O Power

Supply

MODE Input-

Static

NC No Connects. Not Internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and

Address Inputs used to select one of the 128K address locations. Sampled at the rising
edge of the CLK if ADSP
A

feed the 2-bit counter.

[1:0]

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:B]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.

burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device. ADSP is ignored

2

if CE1 is HIGH

CE1

.

is sampled

only when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in co njunction

with CE

and CE3 to select/deselect the device. CE

1

is sampled only when a new external

2

address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE
address is loaded.

and CE2 to select/deselect the device. CE3 is sampled only when a new external

1

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted,

[1:0]

only ADSP

is recognized. ASDP is ignored when

CE1 is deasserted HIGH

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted,

[1:0]

only ADSP

is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE
When HIGH, DQs and DQP

[A:B]

. When OE is asserted LOW, the pins behave as outputs.

are placed in a tri-state condition.

Power supply inputs to the core of the device.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode Pin has an internal pull-up.

1G are address expansion pins and are not internally connected to the die.

Document #: 001-00208 Rev. *B Page 3 of 15

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CY7C1324H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t

The CY7C1324H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP

). Address advancement through the burst sequence is

(ADSC
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP is ignored if CE
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP

is ignored if CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
presented are loaded into the address register and the burst
inputs (GW

, BWE, and BW
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During Byte Writes, BWA
DQB. All I/Os are tri-stated during a Byte Write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE

) is 6.5 ns (133-MHz device).

CDV

) or the Controller Address Strobe

input. A two-bit on-chip wraparound

) inputs. A Global Write

) overrides all byte write inputs and writes data to

[A:B]

, CE2, CE3) and an

1

) provide for easy bank

, CE2, and CE3 are all

1

or ADSC is asserted LOW (if

, the write inputs must be

after clock

CDV

, CE2, CE3 are all asserted

1

is asserted LOW. The addresses

) are ignored during this first

[A:B]

controls DQA and BWB controls

.

, CE2, and CE3 are all asserted

1

active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC

is asserted LOW, (3) ADSP is deasserted

, BWE, and BW[A:B])

is ignored if ADSP is active

LOW.
The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BWA

controls DQA and BWB
controls DQB. All I/Os are tri-stated when a Write is detected,
even a Byte Write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a
Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1324H provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A

, and can follow either a linear or interleaved burst order.

[1:0]

The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to an
interleaved burst sequence.

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP
inactive for the duration of t
LOW.

, and ADSC must remain

after the ZZ input returns

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A

0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A0

Second

Address

A1, A

0

DD

)

Third

Address

A1, A0

Third

Address

A1, A

0

.

Fourth

Address

A1, A0

Fourth

Address

A1, A

0

Document #: 001-00208 Rev. *B Page 4 of 15

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CY7C1324H

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Cycle Description

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-S tate
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Curre nt X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Curre nt X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Curre nt H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Curre nt H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW.

3. WRITE

4. The SRAM always initiates a Read cycle when ADSP

5. OE

= L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB),

BWE

, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

after the ADSP
don't care for the remainder of the Write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE

is inactive or when the device is deselected, and all data bits behave as output when OE

Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ns
ns
ns

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5]

ADDRESS

Used CE1CE2CE3ZZ ADSP ADSC ADV WE OE CLK DQ

None H X X L X L X X X L-H Tri-State

None L L X L L X X X X L-H Tri-State

None L X H L L X X X X L-H Tri-State

None L L X L H L X X X L-H Tri-State

None X X X L H L X X X L-H Tri-State

or with the assertion of ADSC. As a result, OE must be driven HI GH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a

is asserted, regardless of the state of GW , BWE, or BW

is active (LOW)

. Writes may occur only on subsequent clocks

[A: B]

Document #: 001-00208 Rev. *B Page 5 of 15

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CY7C1324H

Truth Table for Read/Write

Function GW BWE BW

Read H H X X
Read H L H H
Write Byte (A, DQP
Write Byte (B, DQP
Write All Bytes H L L L
Write All Bytes L X X X

)HLHL

A

)HLLH

B

[2, 3]

B

BW

A

Document #: 001-00208 Rev. *B Page 6 of 15

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CY7C1324H

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ........ ... .. ... .................–65°C to +150°C

Ambient Temperature with

Power Applied..................................... ........–55°C to +125°C

Supply Voltage on V
Supply Voltage on V
DC Voltage Applied to Outputs

in Tri-State........................................ ...–0.5V to V

Electrical Characteristics

Relative to GND........–0.5V to +4.6V

DD

Relative to GND......–0.5V to +V

DDQ

+ 0.5V

DDQ

Over the Operating Range

DD

DC Input Voltage...................................–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V
Industrial –40°C to +85°C

[6, 7]

Ambient

Temperature V

−5%/+10%

DD

+ 0.5V

DD

V

DDQ

2.5V –5%
to V

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

DD
DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

V

OL

V

IH

Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3V I/O, I

for 2.5V I/O, I

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4

OL

Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V

V

IL

Input LOW Voltage

[6]

for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7

I

X

I

OZ

I

DD

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

6. Overshoot: V

7. T

Power-up

Input Leakage Current
except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V
V

Operating Supply

DD

Current
Automatic CE

Power-Down
Current—TTL Inputs

Automatic CE
Power-Down
Current—CMOS Inputs

Automatic CE
Power-Down
Current—CMOS Inputs

Automatic CE
Power-Down
Current—TTL Inputs

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and V

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

Max. V
V

≥ VIH or VIN ≤ VIL, f = f

IN

inputs switching

DDQ

SS
DD
SS
DD

, Output Disabled –5 5 µA

DDQ

= 0 mA,

OUT

= 1/t

CYC

, Device Deselected,

DD

MAX,

Max. VDD, Device Deselected,
V

≥ VDD – 0.3V or VIN ≤ 0.3V,

IN

f = 0, inputs static
Max. VDD, Device Deselected,

≥ V

V

IN

0.3V,
f = f

MAX

Max. V
V

≥ V

IN

f = 0, inputs static

– 0.3V or VIN ≤

DDQ

, inputs switching

, Device Deselected,

DD

– 0.3V or VIN ≤ 0.3V,

DD

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

7.5-ns cycle, 133 MHz 225 mA

7.5-ns cycle, 133 MHz 90 mA

7.5-ns cycle, 133 MHz 40 mA

7.5-ns cycle, 133 MHz 75 mA

7.5-ns cycle, 133 MHz 45 mA

DDQ

< VDD.

−55µA

–30 µA

5 µA

–5 µA

30 µA

/2).

CYC

V

Document #: 001-00208 Rev. *B Page 7 of 15

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CY7C1324H

Capacitance

[8]

Parameter Description Test Conditions

C

IN

C

CLK

C

I/O

Thermal Resistance

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V.

Clock Input Capacitance 5 pF
Input/Output Capacitance 5 pF

[8]

V

DD

DDQ

= 2.5V

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

T est conditions follow standard test methods and proce­dures for measuring thermal impedance, per
EIA/JESD51

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

= 50Ω

0

3.3V

OUTPUT

= 50Ω

R

L

VL= 1.5V

(a) (b)

5pF

INCLUDING

JIG AND

SCOPE

R = 317Ω

R = 351Ω

V

GND

DD

≤ 1 ns

ALL INPUT PULSES

10%

90%

100 TQFP

Max. Unit

5pF

100 TQFP

Package Unit

30.32 °C/W

6.85 °C/W

90%

10%

≤ 1 ns

(c)

2.5V I/O Test Load

OUTPUT

= 50Ω

Z

0

V

T

R

= 1.25V

= 50Ω

L

2.5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R =1538Ω

(a) (b)

Notes:

8. Tested initially and after any design or proc ess change that may affect these parameters.

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1 ns

(c)

Document #: 001-00208 Rev. *B Page 8 of 15

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CY7C1324H

Switching Characteristics Over the Operating Range

[9, 10]

-133

Parameter Description

t

POWER

VDD(Typical) to the First Access

[11]

1ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 7.5 ns
Clock HIGH 2.5 ns
Clock LOW 2.5 ns

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid after CLK Rise 6.5 ns
Data Output Hold after CLK Rise 2.0 ns
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z

[12, 13, 14]

[12, 13, 14]

[12, 13, 14]

[12, 13, 14]

0ns

3.5 ns

3.5 ns

0ns

3.5 ns

Set-up Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Address Set-up before CLK Rise 1.5 ns
ADSP, ADSC Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW

Set-up before CLK Rise 1.5 ns

[A:B]

1.5 ns

1.5 ns

Data Input Set-up before CLK Rise 1.5 ns
Chip Enable Set-up 1.5 ns

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

Notes:

9. Timing reference level is 1.5V when V

10.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

11.This part has a voltage regulator internally; t
can be initiated.

, t

12.t

CHZ

13.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

14.This parameter is sampled and not 100% tested.

Address Hold after CLK Rise 0.5 ns
ADSP, ADSC Hold after CLK Rise 0.5 ns
GW, BWE, BW

Hold after CLK Rise 0.5 ns

[A:B]

ADV Hold after CLK Rise 0.5 ns
Data Input Hold after CLK Rise 0.5 ns
Chip Enable Hold after CLK Rise 0.5 ns

CLZ

, t

OELZ

, and t

= 3.3V and 1.25V when V

DDQ

is the time that the power needs to be supplied above VDD(minimum) initially before a Read or W rite operation

POWER

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV fr om steady-state voltage.

OEHZ

is less than t

OEHZ

OELZ

and t

= 2.5V

DDQ

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

UnitMin. Max.

Document #: 001-00208 Rev. *B Page 9 of 15

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G

Timing Diagrams

Read Cycle Timing

[15]

t

CY7C1324H

CYC

CLK

ADSP

ADSC

ADDRESS

W, BWE,BW

[A:B]

CE

ADV

OE

Data Out (Q)

t

ADS

t

AS

t

CES

High-Z

t

t

CL

CH

t

ADH

t

t

ADH

ADS

t

AH

A1

t

t

CLZ

CEH

t

OEV

t

CDV

t

WES

Q(A1)

t

WEH

t

OEHZ

A2

t

t

ADVH

ADVS

t

OELZ

t

CDV

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

Single READ BURST

DON’T CARE

ADV suspends burst.

READ

UNDEFINED

Deselect Cycle

Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A2 + 3)

Burst wraps around
to its initial state

t

CHZ

Note:

15.On this diagram, when CE

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 001-00208 Rev. *B Page 10 of 15

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Timing Diagrams (continued)

D

Write Cycle Timing

[15, 16]

t

CYC

CY7C1324H

ADSP

ADSC

ADDRESS

BWE,

BW

[A:B]

GW

CE

CLK

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

A2 A3

Byte write signals are ignored for first cycle when
ADSP initiates burst.

t

t

CEH

CES

t

WES

t

WEH

ADSC extends burst.

t

ADS

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

ADV

OE

Data in (D)

ata Out (Q)

Note:

16.

Full width Write can be initiated by either GW

High-Z

t

OEHZ

BURST READ BURST WRITE

t

t

DH

DS

D(A1)

D(A2) D(A2 + 1) D(A2 + 1)

Single WRITE

DON’T CARE UNDEFINED

LOW; or by GW HIGH, BWE LOW and BW

ADV suspends burst.

D(A2 + 2)

LOW.

[A:B]

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 001-00208 Rev. *B Page 11 of 15

[+] Feedback

Timing Diagrams (continued)

t

Read/Write Timing

[15, 17, 18]

CYC

CY7C1324H

CLK

ADSP

ADSC

ADDRESS

BWE, BW[A:B]

CE

ADV

OE

Data In (D)

Data Out (Q)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

t

CES

A2

t

CEH

A1 A5 A6

High-Z

Q(A1)

Q(A2)

A3 A4

t

t

t

OEHZ

WES

DS

D(A3)

t

t

DH

WEH

t

OELZ

t

CDV

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Notes:

17.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP
is HIGH.

18.GW

Document #: 001-00208 Rev. *B Page 12 of 15

Single WRITE

BURST READBack-to-Back READs

DON’T CARE UNDEFINED

, ADSC, or ADV cycle is performed.

Back-to-Back

WRITEs

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Timing Diagrams (continued)

A

ZZ Mode Timing

[19, 20]

CLK

CY7C1324H

t

ZZ

t

ZZREC

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

19.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

20.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 001-00208 Rev. *B Page 13 of 15

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Ordering Information

CY7C1324H

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered”.

Speed

(MHz) Ordering Code

Package
Diagram Package Type

Operating

Range

133 CY7C1324H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1324H-133AXI 51-85050 100-pin Thin Quad Fl at Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

Package Diagram

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

1.40±0.05

SEE DETAIL

0.20 MAX.

20.00±0.10

22.00±0.20

14.00±0.10

100

1

30

31 50

81

80

0.30±0.08

0.65
TYP.

51

12°±1°

(8X)

A

1.60 MAX.

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

0.10

51-85050-*B

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

A

Intel and Pentium are registered trademarks and i486 is a tr ademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.

Document #: 001-00208 Rev. *B Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change withou t n oti ce. C ypr ess S emi con duct or Corpo ration assu mes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM
Document Number: 001-00208

REV. ECN NO. Issue Date

** 347377 See ECN PCI New Data Sheet

*A 428408 See ECN NXR Converted from Preliminary to Final.

*B 459347 See ECN NXR Included 2.5V I/O option

Orig. of

Change Description of Change

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information table.

IH

< V

DD to VIH

< V

CY7C1324H

DD

Document #: 001-00208 Rev. *B Page 15 of 15

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