Cypress Semiconductor CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 Specification Sheet

CY7C1310AV18

Logic Block Di

(CY7C1310AV18)

CY7C1312AV18

PRELIMINARY

CY7C1314AV18

18-Mb QDR™-II SRAM 2-Word Burst Architecture

Features

• Separate independent Read and Write data ports — Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167MHz

• Two input clocks (K and K — SRAM uses rising edges only

• Two output clocks (C and C and flight time mismatching

• Echo clocks (CQ and CQ speed systems

• Single multiplexed address input bus latches address inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x18, and x36 configurations

• Full data coherancy , providing most current data

• Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd

• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball (11x15 matrix)

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1310AV18 – 2M x 8 CY7C1312AV18 – 1M x 18 CY7C1314AV18 – 512K x 36

agram

D

[7:0]

A

(19:0)

20

) for precise DDR timing

) account for clock skew

) simplify data capture in high

8

Write

Address

Register

Reg

Functional Description

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are

1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310AV18) or 18-bit words (CY7C1312AV18) or 36-bit words (CY7C1314AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K is maximized while simplifying system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Write Reg

1M x 8 Array

input clocks. All data outputs pass through output

1M x 8 Array

and C and C), memory bandwidth

(or K or K in a single clock

Address Register

20

A

clock.

(19:0)

K K

DOFF

V

REF

WPS

BWS

[1:0]

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05497 Rev. *A Revised June 1, 2004

CLK

Gen.

Control

Logic

Write Add. Decode

Read Data Reg.

16

Control

Reg.

Logic

Reg.

Read Add. Decode

8

RPS

C C

8

CQ

Q

[7:0]

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Logic Block Diagram (CY7C1312AV18)

D

[17:0]

18

PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Address

A

(18:0)

19

K K

Register

CLK

Gen.

DOFF

V

REF

WPS

BWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1314AV18)

D

[35:0]

36

Address

A

(17:0)

18

Register

Write Reg

512K x 18 Array

Write Add. Decode

Read Data Reg.

Write Reg

512K x 18 Array

Read Add. Decode

36

18

Write Reg

256K x 36 Array

Reg.

Address Register

Control

Logic

Reg.

Address Register

18

19

C C

18

RPS

18

A

(18:0)

Q

[17:0]

(17:0)

CQ

36

RPS

C C

36

Q

[35:0]

DOFF

V

REF

WPS

BWS

K K

[3:0]

CLK Gen.

Control

Logic

Write Add. Decode

Read Data Reg.

72

Read Add. Decode

36

Reg.

Control

Logic

Reg.

Selection Guide

167 MHz 133 MHz Unit

Maximum Operating Frequency 167 133 MHz

Maximum Operating Current 800 700 mA

CQ

Document #: 38-05497 Rev. *A Page 2 of 21

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Pin Configurations

PRELIMINARY

CY7C1310AV18 (2M × 8) – 11 × 15 BGA

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

A

B C D

E F G

H

K L M N P

R

A

B C D

E F G

H

K L M N P

R

1

CQ NC

NC

DOFF

J

NC

TDO

23

/72M A

V

SS

NC

D4 V

NC

D5

V

REF

NC

Q6

NC

D7

NC

TCK

NC

NC V

Q4

NC

Q5 V

V

DDQ

NC

D6

NC

Q7

A

4567

BWS

A NC/288M

AAA

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A

V

SS

V

SS

DDQ

V

SS

V

SS

A

1

V

V V

V

KWPS

K

SS

A

C

NC/144M

BWS

0

SS

VSS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A

891011

RPS

A NC

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

AV

NC NC D3

NC

NC NC

NC

V

DDQ

NC

NC D0

NC

A

SS

V

/36M

NC

D2

NC

REF

Q1

NC

CQ

Q3

NC

Q2

NC ZQ

D1V

NC

Q0

NC

TDITMS

CY7C1312AV18 (1M × 18) – 11 × 15 BGA

234 56 71

/144M NC/36M

V

CQ

NC

NC V

NC

DOFF

J

NC

TDO

SS

Q9

NC

D11 V

NC

Q12

D13

V

REF

NC

Q15

NC

D17

NC

TCK

D9

D10

Q10 V

Q11

D12

Q13 V

V

DDQ

D14

Q14

D15

D16

Q16

Q17

A

WPS

BWS

A NC

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

1

AAA

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

V V

V

A

K

SS

A

C

NC/288M

BWS

0

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A

AC

891011

RPS

A NC

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

AV

NC Q7 D8

NC

NC Q5

NC

V

DDQ

NC

NC D2

NC

A

SS

V

/72M

NC

D6

NC

REF

Q4

D3

NC

Q1

NC

D0

CQ

Q8

D7

Q6

D5

ZQ

D4V

Q3

Q2

D1

Q0

TDITMS

Document #: 38-05497 Rev. *A Page 3 of 21

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Pin Configurations (continued)

PRELIMINARY

CY7C1314AV18 (512k × 36) – 11 × 15 BGA

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

A

B C D

E

G H

K

M N P

R

1

CQ

Q27

D27

D28

Q29

F

J

L

Q30

D30

DOFF

D31

Q32

Q33

D33

D34

Q35

TDO

23

/288M NC/72M

V

SS

Q18

Q28

D20 V

D29

Q21

D22

V

REF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19 V

Q20

D21

Q22 V

V

DDQ

D23

Q23

D24

D25

Q25

Q26

A

4

WPS

A

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

567

BWS

2

BWS

3

AAA

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A

K

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

C

BWS

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A

1

0

Pin Definitions

Pin Name I/O Pin Description

D

[x:0]

WPS Input-

BWS

, BWS1,

0

BWS

, BWS

2

3

A Input-

Input-

Synchronous

Input-

Synchronous

Data input signals, sampled on the rising edge of K and K clocks during valid write operations.

CY7C1310AV18 - D CY7C1312AV18 - D CY7C1314AV18 - D

[7:0] [17:0] [35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D

[x:0]

Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K

clocks during write operations. Used to select which byte is written into the device

during the current portion of the write operations. Bytes not written remain unaltered. CY7C1310AV18 − BWS CY7C1312AV18 − BWS CY7C1314AV18 − BWS0 controls D and BWS All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte

controls D

3

controls D

0

controls D

0

[35:27].

and BWS1 controls D

[3:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

Write Select will cause the corresponding byte of data to be ignored and not written into the device.

Address Inputs. Sampled on the rising edge of the K (read address) and K address) clocks during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.

891011

RPS

A D17

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

to be ignored.

NC/36M V

D16 Q7 D8

Q16

Q15

D14 Q5

Q13

VDDQ

D12

Q12

D11

D10 D2

Q10

Q9

A

[7:4]

[17:9].

, BWS2 controls D

[17:9]

/144M

SS

Q17

D15

D6

Q14

D13

V

REF

Q4

D3

Q11

Q1

D9

D0

.

(write

CQ

Q8

D7

Q6

D5

ZQ

D4V

Q3

Q2

D1

Q0

TDITMS

[26:18]

Document #: 38-05497 Rev. *A Page 4 of 21

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CY7C1310AV18 CY7C1312AV18

PRELIMINARY

Pin Definitions (continued)

Pin Name I/O Pin Description

Q

[x:0]

RPS Input-

C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data

C

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

K

CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized

CQ

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the

DOFF

TDO Output TDO for JTAG.

TCK Input TCK pin for JTAG.

TDI Input TDI pin for JTAG.

TMS Input TMS pin for JTAG.

NC N/A Not connected to the die. Can be tied to any voltage level.

NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any

NC/72M N/A Address expansion for 72M. This is not connected to the die and so can be tied to any

V

/72M Input Address expansion for 72M. This must be tied LOW on the 18M devices.

SS

/144M Input Address expansion for 144M. This must be tied LOW on the 18M devices.

V

SS

V

288M Input Address expansion for 288M. This must be tied LOW on the 18M devices.

SS/

Outputs-

Synchronous

Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented

Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized

Input DLL Turn Off – Active LOW. Connecting this pin to ground will turn off the DLL inside

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C operations or K and K Q

are automatically tri-stated.

[x:0]

CY7C1310AV18 − Q CY7C1312AV18 − Q CY7C1314AV18 − Q

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.

from the device. C and C devices on the board back to the controller. See application example for further details.

to the device and to drive out data through Q are initiated on the rising edge of K.

to the device and to drive out data through Q

to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table.

to the output clock(C respect to K

system data bus impedance. CQ,CQ where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDR-II.”

voltage level.

. The timings for the echo clocks are shown in the AC timing table.

when in single clock mode. When the Read port is deselected,

[7:0] [17:0] [35:0]

can be used together to deskew the flight times of various

when in single clock mode. All accesses

[x:0]

when in single clock mode.

[x:0]

) of the QDR-II. In the single clock mode, CQ is generated with

and Q

output impedance are set to 0.2 x RQ,

[x:0]

CY7C1314AV18

clocks during Read

Document #: 38-05497 Rev. *A Page 5 of 21

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PRELIMINARY

Pin Definitions (continued)

Pin Name I/O Pin Description

V

REF

DD

SS

DDQ

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Introduction

Functional Overview

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read Port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 8-bit data transfers in the case of CY7C1310AV18, two 18-bit data transfers in the case of CY7C1312AV18 and two 36-bit data transfers in the case of CY7C1314AV18, in one clock cycles.

Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K and all output timings are referenced to the rising edge of output clocks (C and C

All synchronous data inputs (D registers controlled by the input clocks (K and K synchronous data outputs (Q registers controlled by the rising edge of the output clocks (C and C

or K and K when in single clock mode).

All synchronous control (RPS through input registers controlled by the rising edge of the input clocks (K and K

CY7C1312AV18 is described in the following sections. The same basic descriptions apply to CY7C1310AV18 and CY7C1314AV18.

Read Operations

The CY7C1312AV18 is organized internally as two arrays of 512Kx18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS

active at the rising edge of the Positive Input Clock (K). The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto the Q rising edge of the output clock (C and C

. The requested data will be valid 0.45 ns from the

[17:0]

single clock mode).

Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Output Clocks (C/C

). This will allow for a seamless transition between

or K and K when in single clock mode).

) inputs pass through input

[x:0]

) outputs pass through output

[x:0]

, WPS, BWS

) inputs pass

[x:0]

). All

).

or K and K when in

devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D into the lower 18-bit Write Data register provided BWS

is latched and stored

[17:0]

both asserted active. On the subsequent rising edge of the Negative Input Clock (K mation presented to D Register provided BWS bits of data are then written into the memory array at the

), the address is latched and the infor-

is stored into the Write Data

[17:0]

are both asserted active. The 36

[1:0]

specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1312AV18. A write operation is initiated as described in the Write

)

Operation section above. The bytes that are written are determined by BWS data word. Asserting the appropriate Byte Write Select input

and BWS1 which are sampled with each 18-bit

0

during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1312AV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K

) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C

HIGH at power on. This function is

a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1312AV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.

[1:0]

are

Document #: 38-05497 Rev. *A Page 6 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Depth Expansion

The CY7C1312AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V output driver impedance. The value of RQ must be 5x the

to allow the SRAM to adjust its

SS

value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω V

= 1.5V.The output impedance is adjusted every 1024

DDQ

cycles upon powerup to account for drifts in supply voltage and temperature.

Application Example

DATA IN

DATA OUT

Address

BUS

MASTER

(CPU

or

ASIC)

RPS#

WPS#

BWS#

CLKIN/CLKIN#

Source K

Source K#

[1]

SRAM #1

R

Vt

R

D A

W

P

S

#

, with

B

W

S #

CQ/CQ#

CC#

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ

is referenced with respect to C. These are free-running clocks and are synchronized to the output clock(C/C generated with respect to K and CQ to K

) of the QDR-II. In the single clock mode, CQ is

is generated with respect

. The timings for the echo clocks are shown in the AC

Timing table.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF

pin. The DLL can also be reset by slowing the cycle time

of input clocks K and K

\

R = 250ohms

ZQ

Q

K#

K

to greater than 30 ns.

SRAM #4

R

W

B

P

D A

R

W

S

#

Vt Vt

ZQ

CQ/CQ#

S

CC#

Q

K#

K

R = 250ohms

Delayed K

Truth Table

Delayed K#

[ 2, 3, 4, 5, 6, 7]

R

R = 50ohms

Vt = Vddq/2

Operation K RPS WPS DQ DQ

Write Cycle: Load address on the rising edge of K on K and K

rising edges.

Read Cycle:

clock; input write data

L-H X L D(A + 0)at K(t) ↑ D(A + 1) at K

L-H L X Q(A + 0) at C

(t + 1)↑ Q(A + 1) at C(t + 2) ↑

(t) ↑

Load address on the rising edge of K clock; wait one and a half cycle; read data on C

NOP: No Operation L-H H H D=X

and C rising edges.

Q=High-Z

D=X Q=High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

Notes:

1. The above application shows 4 QDRII being used.

2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,

3. Device will power-up deselected and the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K charging symmetrically.

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS write cycle, as long as the set-up and hold requirements are achieved.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

↑represents rising edge.

, BWS1, BWS2, and BWS3 can be altered on different portions of a

0

Document #: 38-05497 Rev. *A Page 7 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Write Cycle Descriptions

(CY7C1310AV18 and CY7C1312AV18)

[2, 8]

BWS0BWS1KK Comments

L L L-H – During the Data portion of a Write sequence :

CY7C1310AV18 − both nibbles (D CY7C1312AV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L L – L-H During the Data portion of a Write sequence :

CY7C1310AV18 − both nibbles (D CY7C1312AV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L H L-H – During the Data portion of a Write sequence :

CY7C1310AV18 − only the lower nibble (D CY7C1312AV18 − only the lower byte (D

) is written into the device. D

[3:0]

) is written into the device. D

[8:0]

L H – L-H During the Data portion of a Write sequence :

CY7C1310AV18 − only the lower nibble (D CY7C1312AV18 − only the lower byte (D

) is written into the device. D

[3:0]

) is written into the device. D

[8:0]

H L L-H – During the Data portion of a Write sequence :

CY7C1310AV18 − only the upper nibble (D CY7C1312AV18 − only the upper byte (D

) is written into the device. D

[7:4]

) is written into the device. D

[17:9]

H L – L-H During the Data portion of a Write sequence :

CY7C1310AV18 − only the upper nibble (D CY7C1312AV18 − only the upper byte (D

) is written into the device. D

[7:4]

) is written into the device. D

[17:9]

H H L-H – No data is written into the devices during this portion of a write operation.

H H – L-H No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions

(CY7C1314AV18)

[2, 8]

will remain unaltered,

[7:4]

will remain unaltered.

[17:9]

will remain unaltered,

[7:4]

will remain unaltered.

[17:9]

will remain unaltered,

[3:0]

will remain unaltered.

[8:0]

will remain unaltered,

[3:0]

will remain unaltered.

[8:0]

BWS0BWS1BWS2BWS3KK Comments

L L L L L-H - During the Data portion of a Write sequence, all four bytes (D

the device.

L L L L - L-H During the Data portion of a Write sequence, all four bytes (D

the device.

) are written into

[35:0]

) are written into

[35:0]

L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D

into the device. D

will remain unaltered.

[35:9]

L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D

into the device. D

H L H H L-H - During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H L H H - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H H L H L-H - During the Data portion of a Write sequence, only the byte (D

the device. D

[17:0]

H H L H - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[17:0]

H H H L L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[26:0]

H H H L - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[26:0]

will remain unaltered.

[35:9]

and D

will remain unaltered.

[35:18]

will remain unaltered.

[35:18]

will remain unaltered.

[35:27]

will remain unaltered.

[35:27]

will remain unaltered.

) is written into

[17:9]

) is written into

[17:9]

) is written into

[26:18]

) is written into

[26:18]

) is written into

[35:27]

) is written into

[35:27]

H H H H L-H - No data is written into the device during this portion of a write operation.

H H H H - L-H No data is written into the device during this portion of a write operation.

) is written

[8:0]

) is written

[8:0]

Document #: 38-05497 Rev. *A Page 8 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Maximum Ratings

(Above which useful life may be impaired.)

Storage Temperature .................................–65°C to +150°C

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V

DC Voltage Applied to Outputs

in High-Z State .................................... –0.5V to V

DC Input Voltage

[12]

............................ –0.5V to V

DDQ

+ 0.5V

DC Electrical Characteristics Over the Operating Range

Operating Range

Range

Temperature(TA) V

Com’l 0°C to +70°C 1.8 ± 0.1 V 1.4V to V

[9,14]

Ambient

DD

[14]

V

DDQ

[14]

Parameter Description Test Conditions Min. Typ. Max. Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

V

IN

I

X

I

OZ

V

REF

I

DD

I

SB1

Power Supply Voltage 1.7 1.8 1.9 V

I/O Supply Voltage 1.4 1.5 V

Output HIGH Voltage [10] V

Output LOW Voltage [11] V

Output HIGH Voltage I

= −0.1 mA, Nominal Impedance V

OH

Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V

Input HIGH Voltage

Input LOW Voltage

[12]

[12, 13]

/2 –0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

SS

V

+ 0.1 V

REF

–0.3 V

Clock Input Voltage –0.3 V Input Load Current GND ≤ VI ≤ V Output Leakage Current GND ≤ VI ≤ V

Input Reference Voltage

VDD Operating Supply V

Automatic Power-down Current

[15]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max., I

DD

f = f

MAX

= 1/t

Max. VDD, Both Ports Deselected, V V

≤ VIL f = f

IN

Inputs Static

DDQ

Output Disabled −55µA

DDQ,

OUT

CYC

= 0 mA,

133 MHz 700 mA

167 MHz 800 mA

133 MHz 450 mA

≥ VIH or

IN

MAX

= 1/t

167 MHz 470 mA

CYC,

−55µA

DD

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

0.2 V

+0.3 V

DDQ

– 0.1 V

REF

+ 0.3 V

DDQ

DD

V

AC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ . Max. Unit

V

IH

V

IL

Notes:

9. All Voltage referenced to Ground.

10. Output are impedance controlled. Ioh=-(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

11. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

12. Overshoot: V

13. This spec is for all inputs except C and C

14. Power-up: Assumes a linear ramp from 0v to V

15. V

REF

Document #: 38-05497 Rev. *A Page 9 of 21

Input High (Logic 1) Voltage V

+ 0.2 – – V

REF

Input Low (Logic 0) Voltage – – V

IH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2).

(Min.) = 0.68V or 0.46V

DDQ

clocks. For C and C clocks, VIL(Max.) = V

, whichever is larger, V

DD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD

(Max.) = 0.95V or 0.54V

REF

– 0.2V.

REF

, whichever is smaller.

DDQ

– 0.2 V

REF

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Switching Characteristics Over the Operating Range

Cypress Consortium

Description

t

CYC

t

KH

t

KL

t

KHKH

t

KHCH

t

KHKH

t

KHKL

t

KLKH

t

KHKH

t

KHCH

K Clock and C Clock Cycle Time 6.0 7.9 7.5 8.4 ns

Input Clock (K/K and C/C) HIGH 2.4 – 3.0 – ns

Input Clock (K/K and C/C) LOW 2.4 – 3.0 – ns

K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge)

K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.8 0.0 3.55 ns

[16,17]

167 MHz 133 MHz

UnitParameter Parameter Min. Max. Min. Max.

2.7 – 3.38 – ns

Set-up Times

t

SA

t

SC

t

SCDDR

t

SD

t

SA

SC

SD

Address Set-up to K Clock Rise 0.5 – 0.5 – ns

Control Set-up to Clock (K, K) Rise (RPS, WPS) 0.5 – 0.5 – ns

Double Data Rate Control Set-up to Clock (K, K) Rise (BWS

, BWS1, BWS3, BWS4)

0

D

Set-up to Clock (K and K) Rise 0.5 – 0.5 – ns

[X:0]

0.5 – 0.5 – ns

Hold Times

t

HA

t

HC

t

HCDDR

t

HD

t

HA

HC

HD

Address Hold after Clock (K and K) Rise 0.5 – 0.5 – ns

Control Hold after Clock (K and K) Rise (RPS, WPS) 0.5 – 0.5 – ns

Double Data Rate Control Hold after Clock (K and K) Rise

, BWS1 , BWS3, BWS4)

(BWS

0

D

Hold after Clock (K and K) Rise 0.5 – 0.5 – ns

[X:0]

0.5 – 0.5 – ns

Output Times

t

CO

t

DOH

t

CCQO

t

CQOH

t

CQD

t

CQDOH

t

CHZ

t

CLZ

t

CHQV

t

CHQX

t

CHCQV

t

CHCQX

t

CQHQV

t

CQHQX

t

CHZ

t

CLZ

C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid – 0.50 – 0.50 ns

Data Output Hold after Output C/C Clock Rise (Active to

–0.50 – –0.50 – ns

Active)

C/C Clock Rise to Echo Clock Valid – 0.50 – 0.50 ns

Echo Clock Hold after C/C Clock Rise –0.50 – –0.50 – ns

Echo Clock High to Data Valid – 0.40 – 0.40 ns

Echo Clock High to Data Invalid –0.40 – –0.40 – ns

Clock (C and C) Rise to High-Z (Active to High-Z)

Clock (C and C) Rise to Low-Z

[18,19]

– 0.50 – 0.50 ns

–0.50 – –0.50 – ns

DLL Timing

t

KC Var

t

KC lock

t

KC ResettKC Reset

Thermal Resistance

t

KC Var

t

KC lock

Clock Phase Jitter – 0.20 – 0.20 ns

DLL Lock Time (K, C) 1024 – 1024 - cycl

es

K Static to DLL Reset 30 30 ns

[20]

Parameter Description Test Conditions 165 FBGAPackage Unit

Θ

JA

Θ

JC

Notes:

16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.

17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I

, t

18. t

CHZ

19. At any given voltage and temperature t

Thermal Resistance (Junction to Ambient)

Thermal Resistance

Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51.

(Junction to Case)

and load capacitance shown in (a) of AC test loads.

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CLZ

is less than t

CHZ

CLZ

and t

OL/IOH

less than tCO.

CHZ

16.7 °C/W

2.5 °C/W

= 1.5V, input

DDQ

Document #: 38-05497 Rev. *A Page 10 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Capacitance

[20]

Parameter Description Test Conditions Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

O

Clock Input Capacitance 6 pF

Output Capacitance 7 pF

V V

= 1.8V

DD DDQ

= 1.5V

5pF

AC Test Loads and Waveforms

= 0.75V

V

REF

(a)

0.75V

Z

0

RQ = 250Ω

= 50Ω

V

REF

= 50Ω

R

L

= 0.75V

V

REF

OUTPUT

Device Under

ZQ

Te st

INCLUDING

JIG AND

SCOPE

0.75V

RQ = 250Ω

(b)

R = 50Ω

5pF

0.25V

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2V / ns

V

REF

OUTPUT

Device Under Te st

ZQ

Note:

20. Tested initially and after any design or process change that may affect these parameters.

[12]

Document #: 38-05497 Rev. *A Page 11 of 21

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PRELIMINARY

W

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Switching Waveforms

[21,22,23]

Read/Write/Deselect Sequence

READ READ WRITE WRITEWRITE

12345 8 10

K

t

KH

K

RPS

PS

A0

A

tSAt

D

Q

t

KHCH

C

CQ

t

KH

t

KL

tt

SC

tSAt

HA

D30 D50 D51 D61

t

KL

t

KHCH

t

CYC

t

HC

A3 A4A1 A2

D31D11D10 D60

t

SD

t

CLZ

t

CO

t

KHKH

t

CCQO

t

CQOH

t

HD

t

READ WRITE NOP

6

t

KHKH

t

SD

Q00 Q01 Q20

t

DOH

t

CO

t

CCQO

CQOH

t

DOH

t

CYC

NOP

7

A6A5

t

HD

Q21

t

CQD

9

Q40 Q41

t

CHZ

Notes:

21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

22. Output are disabled (High-Z) one clock cycle after a NOP.

23. In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.,

Document #: 38-05497 Rev. *A Page 12 of 21

DON’T CARE UNDEFINED

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP R e gisters

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the

TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction

Document #: 38-05497 Rev. *A Page 13 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

and tCH). The SRAM clock input might not be

CS

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47. When this scan cell, called the "extest output bus tristate", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 38-05497 Rev. *A Page 14 of 21

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CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

TAP Controller State Diagram

1

TEST-LOGIC RESET

0

TEST-LOGIC/

1

IDLE

[24]

SELECT DR-SCAN

0

1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

1

SELECT

1

IR-SCAN

0

1

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

0

1

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

0

1

0

Document #: 38-05497 Rev. *A Page 15 of 21

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TAP Controller Block Diagram

Selection Circuitry

TDI

PRELIMINARY

Bypass Register

Instruction Register

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

0

Selection

012

Circuitry

TDO

29

3031

012..

Identification Register

106

.

012..

Boundary Scan Register

TCK

TAP Controller

TMS

DD

[9,12,25]

V

DD

−55µA

+ 0.3 V

DD

TAP Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

Note:

25. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

Output HIGH Voltage I

Output LOW Voltage IOL = 2.0 mA 0.4 V

Output LOW Voltage IOL = 100 µA0.2V

Input HIGH Voltage 0.65V

Input LOW Voltage –0.3 0.35V Input and OutputLoad Current GND ≤ VI ≤ V

= −2.0 mA 1.4 V

OH

= −100 µA1.6V

OH

V

Document #: 38-05497 Rev. *A Page 16 of 21

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PRELIMINARY

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

TAP AC Switching Characteristics Over the Operating Range

[26, 27]

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 100 ns

TCK Clock Frequency 10 MHz

TCK Clock HIGH 40 ns

TCK Clock LOW 40 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

TMS Set-up to TCK Clock Rise 10 ns

TDI Set-up to TCK Clock Rise 10 ns

Capture Set-up to TCK Rise 10 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 10 ns

TDI Hold after Clock Rise 10 ns

Capture Hold after Clock Rise 10 ns

Output Times

t

TDOV

t

TDOX

TAP Timing and Test Conditions

TCK Clock LOW to TDO Valid 20 ns

TCK Clock LOW to TDO Invalid 0 ns

[27]

0.9V

50

Ω

TDO

Z

= 50

Ω

0

C

L

= 20 pF

0V

ALL INPUT PULSES

1.8V

0.9V

GND

t

TH

t

TL

(a)

Test Clock TCK

t

TMSS

t

TMSH

Test Mode Select TMS

t

TDIS

t

TDIH

Test Data-In TDI

Test Data-Out TDO

t

TDOV

26. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

27. Test conditions are specified using the load in TAP AC test conditions. t

R/tF

= 1 ns.

t

TCYC

t

TDOX

Document #: 38-05497 Rev. *A Page 17 of 21

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Identification Register Definitions

CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Instruction Field

Revision Number (31:29) 000 000 000 Version number.

Cypress Device ID (28:12) 11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM.

Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 Allows unique identification of

ID Register Presence (0) 1 1 1 Indicates the presence of an

Scan Register Sizes

Register Name Bit Size

Instruction 3

Bypass 1

ID 32

Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

CY7C1314AV18

Description2M x 8 1M x 18 512K x 36

SRAM vendor.

ID register.

Boundary Scan Order

Bit # Bump ID

06R

16P

26N

37P

47N

57R

68R

78P

89R

911P

10 10P

11 10N

12 9P

13 10M

14 11N

Document #: 38-05497 Rev. *A Page 18 of 21

Boundary Scan Order (continued)

Bit # Bump ID

15 9M

16 9N

17 11L

18 11M

19 9L

20 10L

21 11K

22 10K

23 9J

24 9K

25 10J

26 11J

27 11H

28 10G

29 9G

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Boundary Scan Order (continued)

Bit # Bump ID

30 11F

31 11G

32 9F

33 10F

34 11E

35 10E

36 10D

37 9E

38 10C

39 11D

40 9C

41 9D

42 11B

43 11C

44 9B

45 10B

46 11A

47 Internal

48 9A

49 8B

50 7C

51 6C

52 8A

53 7A

54 7B

55 6B

56 6A

57 5B

58 5A

59 4A

60 5C

61 4B

62 3A

63 1H

64 1A

65 2B

66 3B

67 1C

68 1B

69 3D

70 3C

71 1D

72 2C

73 3E

Boundary Scan Order (continued)

Bit # Bump ID

74 2D

75 2E

76 1E

77 2F

78 3F

79 1G

80 1F

81 3G

82 2G

83 1J

84 2J

85 3K

86 3J

87 2K

88 1K

89 2L

90 3L

91 1M

92 1L

93 3N

94 3M

95 1N

96 2M

97 3P

98 2N

99 2P

100 1P

101 3R

102 4R

103 4P

104 5P

105 5N

106 5R

Document #: 38-05497 Rev. *A Page 19 of 21

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Ordering Information

Speed (MHz) Ordering Code

167 CY7C1310AV18-167BZC BB165D 13 x 15 x 1.4 mm FBGA Commercial

CY7C1312AV18-167BZC

CY7C1314AV18-167BZC

133 CY7C1310AV18-133BZC BB165D 13 x 15 x 1.4 mm FBGA Commercial

CY7C1312AV18-133BZC

CY7C1314AV18-133BZC

Package Diagram

Package

Name Package Type

165 FBGA 13 x 15 x 1.40 mm BB165D

CY7C1314AV18

Operating

Range

QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05497 Rev. *A Page 20 of 21

51-85180-**

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Document History Page

Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05497

REV. ECN No. Issue Date

** 208405 see ECN DIM New Data Sheet

*A 230396 see ECN VBL Upload datasheet to the internet

Orig. of

Change Description of Change

CY7C1314AV18

Document #: 38-05497 Rev. *A Page 21 of 21

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Cypress Semiconductor CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual