Cypress Semiconductor CY7C1314V18-167BZC, CY7C1314V18-133BZC, CY7C1312V18-200BZC, CY7C1312V18-167BZC, CY7C1312V18-133BZC Datasheet
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PRELIMINARY
18-Mb QDR™-II SRAM Two-word
Burst Architecture
CY7C1310V18
CY7C1312V18
CY7C1314V18
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05180 Rev. *A Revised August 2, 2002
Features
• Separate Independent Read and Write Data Ports
—Supports concurrent transactions
• 167-MHz Clock for High Bandwidth
• Two-word Burst on all accesses
• Double Data Rate (DDR) interfaces on bo th Read & Write
Ports (data transferred at 333 MHz) @ 167MHz
• Two input cloc ks (K and K ) for precise DDR timing
—SRAM uses rising edges only
• Two output clocks (C and C
) accounts for clock skew
and flight time mismatches
• Echo clocks (CQ and CQ
) simplify data ca pture in high
speed systems
• Single multiplexed ad dress i nput bus l atches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x18, and x36 configurations
• 1.8V core power supply with HSTL Inputs and Outputs
• 13x15 mm 1.0-mm pitch FBGA p ackage, 165 ball (1 1x15
matrix)
• Variable drive HSTL output buffers
• Extended HSTL output voltage (1.4V–V
DD
)
•JTAG Interface
• On-chip Delay Lock Loop (DLL)
Configurations
CY7C1310V18 – 2M x 8
CY7C1312V18 – 1M x 18
CY7C1314V18 – 512K x 36
Functional Description
The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V
Synchronous Pipeline d SRAMs, equipped with QDR
™
-II archi-
tecture. QD R
TM
-II architecture consists of two separate ports
to access the memory array. The Read port has dedicated
Data Outputs to support Read operations and the Write Port
has dedicated Data Inputs to support Write operations.
QDR
TM
-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latc hed on the rising edge of the K cloc k a nd
the Write address is latched on the rising edge of the K
clock.
Accesses to the QDRTM-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput , both Read and Writ e ports a re equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 8-bit words (CY7C1310V18) or 18-bit
words (CY7C1312V18) or 36-bit words (CY7C1314V18) that
burst sequentially into or out of the device. Since data can be
transferred into and out of the device on every rising edge of
both input clocks (K/K
and C/C), memory bandwidth is
maximized while s impl ifyin g sys tem de sign by el imina ting bu s
“turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inp ut s pa ss thro ugh inp ut regis ters c ont rolled
by the K or K
input clocks. All data o utputs pa ss through output
registers controlled by the C/C (or K/K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1310V18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
20
8
16
8
BWS
[1:0]
V
REF
Write Add. Decode
8
A
(19:0)
20
C
C
8
1M x 8 Array
1M x 8 Array
Write
Reg
Write
Reg
CQ
CQ
8
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 2 of 25
Selection Guide
[1]
200 MHz 167 MHz 133 MHz Unit
Maximum Operating Frequency 200 167 133 MHz
Maximum Operating Current
TBD TBD TBD mA
Note:
1. Shaded cells indicate advanced information.
Logic Block Diagram (CY7C1312V18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
A
(18:0)
19
C
C
18
512K x 18 Array
512K x 18 Array
Write
Reg
Write
Reg
CQ
CQ
18
Logic Block Diagram (CY7C1314V18)
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
A
(17:0)
18
C
C
36
256K x 36 Array
256K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 3 of 25
Pin Configurations
CY7C1310V18 (2M x 8) - 11 x 15 BGA
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
V
SS
/72M A BWS
1
KWPS
NC
NC
NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC
A NC
K
BWS
0
V
SS
AAA
NC V
SS
V
SS
V
SS
VSS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q4
NC
V
DDQ
NC
NC
NC
NC
Q7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
AC
V
SS
A
A
A
D4 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC
Q6
NC
D7
D6
V
DD
A
891011
NC
AV
SS
/36MRPS
CQ
A NC
NC
Q3
V
SS
NC NC D3
NC
V
SS
NC
Q2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D1V
DDQ
NC
Q1
NC
V
DDQ
V
DDQ
NC
V
SS
NC D0
NC
TDITMS
V
SS
A
NC
A
NC
D2
NC
ZQ
NC
Q0
NC
NC
NC
NC
A
CY7C1312V18 (1M x 18) - 11 x 15 BGA
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
V
SS
/144M NC/36M BWS
1
KWPS
NC
Q9
D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10
A NC
K
BWS
0
V
SS
AAA
Q10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q11
D12
V
DDQ
D14
Q14
D16
Q16
Q17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
AC
V
SS
A
A
A
D11 V
SS
NC V
SS
Q12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC
Q15
NC
D17
D15
V
DD
A
891011
Q0
AV
SS
/72MRPS
CQ
A NC
NC
Q8
V
SS
NC Q7 D8
NC
V
SS
NC
Q6
D5
NC
NC
V
REF
NC
Q3
V
DDQ
NC
V
DDQ
NC Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
NC
Q4
NC
V
DDQ
V
DDQ
NC
V
SS
NC D2
NC
TDITMS
V
SS
A
NC
A
D7
D6
NC
ZQ
D3
Q2
D1
Q1
D0
NC
A
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 4 of 25
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
V
SS
/288M NC/72M BWS
2
KWPS
BWS
1
Q18
D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19
A BWS
3
K
BWS
0
V
SS
AAA
Q19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q20
D21
V
DDQ
D23
Q23
D25
Q25
Q26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
AC
V
SS
A
A
A
D20 V
SS
Q29 V
SS
Q21
D30
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
Q32
Q24
Q35
D26
D24
V
DD
A
891011
Q0
NC/36M V
SS
/144MRPS
CQ
A D17
Q17
Q8
V
SS
D16 Q7 D8
Q16
V
SS
D15
Q6
D5
D9
Q14
V
REF
Q11
Q3
V
DDQ
Q15
V
DDQ
D14 Q5
V
DDQ
VDDQ
V
DDQ
D4V
DDQ
D12
Q4
Q12
V
DDQ
V
DDQ
D11
V
SS
D10 D2
Q10
TDITMS
V
SS
A
Q9
A
D7
D6
D13
ZQ
D3
Q2
D1
Q1
D0
Q13
A
CY7C1314V18 (512k x 36) - 11 x 15 BGA
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 5 of 25
Pin Definitions
Pin Name I/O Pin Description
D
[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid
write operations.
CY7C1310V18 - D[7:0]
CY7C1312V18 - D[17:0]
CY7C1314V18 - D[35:0]
WPS Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
[x:0]
to be ignored.
BWS0, BWS1,
BWS
2
, BWS
3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K
and K
clocks during write o perations. Used to s elect which byte is w ritten into the devi ce
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1310V18 − BWS
0
controls D
[3:0]
and BWS1 controls D
[7:4]
.
CY7C1312V18 − BWS
0
controls D
[8:0]
and BWS1 controls D
[17:9].
CY7C1314V18 − BWS0 controls D
[8:0]
, BWS1 controls D
[17:9]
, BWS2 controls D
[26:18]
and BWS
3
controls D
[35:27]
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the
device.
A Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write
operations. These addres s input s are multip lexed for both Read and W rite operatio ns.
Internally , the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7 C1310V18,
1M x 18 (2 arrays e ach o f 512K x 18) for CY 7C1312V1 8 and 256K x 36 ( 2 array s eac h
of 256K x 36) for CY7C1314V18. Therefore, only 20 address inputs are needed to
access the entire memor y array of CY7C1310V18, 19 address i nputs for CY7C1312V18
and 18 address inputs for CY7C1314V18. These inputs are ignored when the appropriate port is deselected.
Q
[x:0]
Outputs-
Synchronous
Data Output signa ls. These pins driv e out the requeste d data during a Read operation.
Valid data is driven out on the rising edge of both the C and C
clocks during Read
operations or K and K
. when in single clock mo de. When the Read port is deselected,
Q
[x:0]
are automatically three-st ate d.
CY7C1310V18 − Q
[7:0]
CY7C1312V18 − Q
[17:0]
CY7C1314V18 − Q
[35:0]
RPS Input-
Synchronous
Read Port Select, active LOW . Sample d on the rising edge of Positive Input C lock (K).
When active, a Read opera tion is i nitiated. Deasserting will caus e the Read p ort to be
deselected. When deselected, the pending access is allowed to comp lete and the output
drivers are automati cally three-sta ted following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
C Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read
data from the devi ce. C and C can be used toge ther to deskew the fligh t times of various
devices on the board b ack to the con troller. See applicati on ex ample for furthe r det ails.
C Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the devi ce. C and C
can be used together to de skew the flight times of various
devices on the board b ack to the con troller. See applicati on ex ample for furthe r det ails.
K Input-Clock Positive Input Clock Input. The rising edge of K is us ed to capture synchro nous inputs
to the device an d to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the ri sing edge of K.
K Input-Clock Negative Input Clock Input. K is used to capture synchron ous inputs being presented
to the device and to drive out data through Q
[x:0]
when in single clock mode.
CQ Ec ho C lock CQ is referenced wi th res pec t to C. This is a free running cl ock and is synchronized
to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ Ec ho C lock CQ is referenced with res pec t to C . Thi s i s a fre e running clock and is sy nc hron iz ed
to the output clock of the QDR
TM
-II. In the single clock mode, CQ is generated with
respect to K
. The timings for the echo clocks are shown in the AC timing table.
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 6 of 25
Introduction
Functional Overview
The CY7C1310V18/CY7C1312V18/CY7C1314V18 are
synchronous pipelined Burst SRAMs equipped with both a
Read port and a Write port. The Read port is dedicated to
Read operations and the Write port is dedicated to Write
operations. Data flows into the SRAM through the Write port
and out thro ugh the Read Po rt. These d evices mult iplex the
address inputs in order to minimize the number of address pin s
required. By having separate Read and Write ports, the
QDR
TM
-II completely elimina tes th e n eed to “turn-around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 8-bit
data transfers in the case of CY7C1310V18, two 18-bit data
transfers in the case of CY7C1312V18 and two 36-bit data
transfers in the case of CY7C1314V18, in one clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K
)
and all output timings are referenced to the output clocks (C
and C
or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous dat a output s (Q
[x:0]
) outputs pass through out put
registers controlled by the rising edge of the output clocks (C
and C
or K and K when in single clock mode).
All synchronous control (RPS
, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K
).
The following descriptions take CY7C1312V18 as an
example. However, the same is true for the other QDR
TM
-II
SRAMs, CY7C1310V18 and CY7C1314V18.
These chips utilize a Delay Lock Loop (DLL) that is designed
to function betwee n 80 MH z and the specifie d maxim um clock
frequency . The DLL may be disabled by applyin g ground to the
DOFF
pin.
Read Operations
The CY7C1312V18 is organized internally as a 512Kx36
SRAM. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS
active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using C as the output timing reference. On the subse-
quent rising edge of C, th e next 1 8-bit dat a word i s driven onto
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bu s impedance. Q
[x:0]
output impedance are set to 0. 2 x RQ, where RQ
is a resistor connected b etween ZQ and ground. Alterna tely, this pin can be connected
directly to V
DD
, which enables the minimum impedance mode. This pin cannot be
connected directly to GND or left uncon ne cte d.
DOFF Input DLL T urn Off. Co nnecting this pin t o ground w ill turn o ff the D LL inside the devic e. The
timings in the DLL turned off operation will be different from those listed in this data
sheet. More details on this operation can be found in the application note, “DLL
Operation in the QDR
TM
-II.”
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC Input No connects inside the package. Can be tied to any voltage level.
NC/36M Input Address expansion fo r 36M. This is no t connected to th e die and so ca n be tied to any
voltage level.
NC/72M Input Address expansion fo r 72M. This is no t connected to th e die and so ca n be tied to any
voltage level.
VSS/72M Input Address expansion for 72M. This must be tied LOW on the 18M devices.
V
SS/
144M Input Address expansion for 144M. This must be tied LOW on the 18M devices.
V
SS/
288M Input Address expansion for 288M. This must be tied LOW on the 18M devices.
V
REF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
V
DD
Power Supply Power supply input s to the c ore of the device. Should be connected to 1.8 V power
supply.
V
SS
Ground Ground for the device. Should be connected to ground of the system.
V
DDQ
Power Supply Power supply inputs for the outputs of the device. Should be connected to 1.5V
power supply.
Pin Definitions (continued)
Pin Name I/O Pin Description
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 7 of 25
the Q
[17:0]
. The requested data will be valid 0.4 ns from the
rising edge of the output clock (C/C, 167-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs fo llowing th e next rising edge of the Output Clo cks
(C/C
). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS
active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D
[17:0]
is latched and stored
into the lower 18-bit W rit e Data regist er pro vided BWS
[1:0]
are
both asserted active. On the subsequent rising edge of the
Negative Input Cloc k (K
), the address is latched and th e infor-
mation presented to D
[17:0]
is stored into the Write Data
Register provi ded BWS
[1:0]
are both asserted active. The 36
bits of data are then written into the memory array at the
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write op erat ion s are supported by the CY7C131 2V18. A
write operation is initi ated as de scrib ed in the W rite Ope ration
section above. The bytes that are written are determined by
BWS
0
and BWS1 which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Wri te Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1312V18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will r eco gn i ze on ly a si ng le pai r of i n pu t c l oc ks ( K an d
K
) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K
and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user mus t ti e C an d C
HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1312V18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction on the other port. Als o, reads and writes can be s tart ed
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deli ver the most recent information associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1312V18 has a Port Select in put for each port. Thi s
allows for easy depth expansion. Both Port Selects are
sampled on the rising edg e of the Positive Input Clock onl y (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the inten ded line impe dance driven by the SRAM. The
allowable range of RQ to guaran tee imped ance matchi ng with
a tolerance of ±10% is between 175Ω and 350Ω
, with
V
DDQ
= 1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR
TM
-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR
TM
-II. CQ is referenced with respect to
C and CQ
is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the QDR
TM
-II. In the single clock mode, CQ is generated
with respect to K and CQ
is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Document #: 38-05180 Rev. *A Page 8 of 25
\
Application Example
[2]
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K
clock; input write data on K and K
rising edges.
L-H X L D(A + 00)at K(t) ↑ D(A + 01) at K
(t) ↑
Read Cycle:
Load address on the rising edge of K
clock; wait one and a half cycle; read
data on C
and C rising edges.
L-H L X Q(A + 00) at C
(t + 1)↑ Q(A + 01) at C(t + 2) ↑
NOP: No Operation L-H H H High-Z High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Write Cycle Descriptions
(CY7C1310V18 and CY7C1312V18)
[3, 9]
BWS0BWS
1
KK Comments
LLL-H– During the Data portion of a Write sequence :
CY7C1310V18 − both nibbles (D
[7:0]
) are written into the device,
CY7C1312V18 − both bytes (D
[17:0]
) are written into the device.
LL– L-H During the Data portion of a Write sequence :
CY7C1310V18 − both nibbles (D
[7:0]
) are written into the device,
CY7C1312V18 − both bytes (D
[17:0]
) are written into the device.
Notes:
2. The above application shows 4 CY7C1312V18 being used. This holds true for CY7C1310V18 and CY7C1314V18 as well.
3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
4. Device will power-up deselected and the outputs in a three-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K
rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetricall y.
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth T a ble. BWS
0
and BWS1 can be altered on different portions of a write cycle, as
long as the set-up and hold requirements are achieved.
D
Q
Add.
K/K
C/C
Cntr.
Add.
K/K
C/C
Cntr.
18
72
SRAM #1
SRAM #4
V
TERM
= V
REF
72
18
CLK/CLK (output)
Q
Din
Add.
Cntr.
CLK/CLK
(input)
18
18
2
R = 50Ω
VT = V
REF
R = 50Ω
D
Q
Memory
Controller
17
17
2
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