Cypress Semiconductor CY7C1305BV25, CY7C1307BV25 Specification Sheet

Q

CY7C1305BV25
CY7C1307BV25

18-Mbit Burst of 4 Pipelined SRAM with

DR™ Architecture

Features

• Separate independent Read and Write data ports

• Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K

• SRAM uses rising edges only

• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JT A G in terface

) for precise DDR timing

) to minimize

Configurations

Functional Description

The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV25) and four
36-bit words (CY7C1307BV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K

) memory bandwidth is maximized while simplifying

C/C
system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

input clocks. Writes are

and

• CY7C1305BV25 – 1M x 18

• CY7C1307BV25 – 512K x 36

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05630 Rev. *A Revised April 3, 2006

[+] Feedback

Logic Block Diagram (CY7C1305BV25)

D

A

[17:0]

[17:0]

18

18

Address
Register

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Address
Register

CY7C1305BV25
CY7C1307BV25

A

(17:0)

18

K
K

CLK

Gen.

Write Add. Decode

Vref
WPS
BWS

[0:1]

Control
Logic

Logic Block Diagram (CY7C1307BV25)

D

A

(16:0)

[35:0]

17

K
K

36

Address
Register

CLK

Gen.

Write Add. Decode

Read Data Reg.

Write

Write

Reg

Reg

128K x 36 Array

128K x 36 Array

Read Data Reg.

72

36

36

Write

Write

Reg

Reg

128K x 36 Array

128K x 36 Array

Read Add. Decode

Read Add. Decode

Reg.

Reg.

Control
Logic

Reg.

Address
Register

Control
Logic

18

17

RPS

C
C

RPS

C
C

18

A

Q

(16:0)

[17:0]

Vref
WPS
BWS

[0:3]

Control
Logic

Selection Guide

Maximum Operating Frequency 167 MHz
Maximum Operating Current 400 mA

Document #: 38-05630 Rev. *A Page 2 of 21

144

72

72

Reg.

Reg.

Reg.

36

CY7C1305BV25-167
CY7C1307BV25-167 Unit

36

Q

[35:0]

[+] Feedback

CY7C1305BV25
CY7C1307BV25

\

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1305BV25 (1M x 18)

1 2 3 4567891011

A NC GND/ 144M NC/ 36M WPS
B NC Q9 D9 A NC K BWS
C NC NC D10 VSS A NC A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A C

BWS

K NC RPS A GND/ 72M NC

1

ANCNCQ8

0

AAATMSTDI

CY7C1307BV25 (512K x 36)

12 34567891011

A NC GND/ 288M NC/ 72M WPS
B Q27 Q18 D18 A BWS
C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS A A A VSS Q10 D9 D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R TDO TCK A A A C

BWS

K BWS

2

KBWS0AD17Q17 Q8

3

AAATMSTDI

RPS NC/ 36M GND/ 144 M NC

1

Document #: 38-05630 Rev. *A Page 3 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Pin Definitions

Name I/O Description

D

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

BWS
BWS

, BWS1,

0

, BWS

2

3

Input-

Synchronous

A Input-

Synchronous

Q

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

K

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the

TDO Output TDO pin for JTAG
TCK Input TCK pin for JTAG
TDI Input TDI pin for JTAG
TMS Input TMS pin for JTAG

Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.

CY7C1305BV25 – D
CY7C1307BV25 – D

[17:0]
[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deassertin g will deselect the Write port.
Deselecting the Write port will cause D

to be ignored.

[x:0]

Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and
K

clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1305BV25 - BWS0 controls D
CY7C1307BV25 - BWS0 controls D
and BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a

controls D

3

[35:27]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

Byte Write Select will cause the corresponding byte of data to be ignored and not written
into the device.

Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for
CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25.
Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for
CY7C1307BV25. These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C
operations or K and K

are automatically three-stated.

Q

[x:0]

CY7C1305BV25 - Q
CY7C1307BV25 - Q

when in single clock mode. When the Read port is deselected,

[17:0]
[35:0]

clocks during Read

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. Each
read access consists of a burst of four sequential 18-bit or 36-bit transfers.

to clock out the

Read data from the device. C and C

can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.

Read data from the device. C and C

can be used together to deskew the flight times of
various devices on the board cack to the controller. See application example for further
details.

to the device and to drive out data through Q
are initiated on the rising edge of K.

to drive out data through Q

system data bus impedance. Q
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
connected directly to VSS or left unconnected.

, which enables the minimum impedance mode. This pin cannot be

DDQ

when in single clock mode.

[x:0]

output impedance are set to 0.2 x RQ, where RQ is

[x:0]

when in single clock mode. All accesses

[x:0]

Document #: 38-05630 Rev. *A Page 4 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Pin Definitions (continued)

Name I/O Description

NC/36M N/A Address expansion for 36M. This is not connected to the die. Can be connected to any

voltage level on CY7C1305BV25/CY7C1307BV25.

GND/72M Input Address expansion for 72M. This sh ould be tied LOW on the CY7C1305BV2 5 .
NC/72M N/A Address expansion for 72M. This can be connected to any voltage level on

GND/144M Input Address expansion for 144M. This should be tied LOW on

GND/288M Input Address expansion for 144M. This should be tied LOW on CY7C1307BV25.
V

V
V
V

REF

DD
SS
DDQ

Input-

Reference

Power Supply Power supply inputs to the cor e of the de vi ce

Ground Ground for the device

Power Supply Power supply inputs for the outputs of the device

NC N/A Not connected to the die. Can be tied to any voltage level.

CY7C1307BV25.

CY7C1305BV25/CY7C1307BV25.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.

Introduction

Functional Overview

The CY7C1305BV25/CY7C1307BV25 are synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write Port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the device completely elimi­nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in the case
of CY7C1305BV25 and four 36-bit data transfers in the case
of CY7C1307BV25, in two clock cycles.

Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K
all output timing is referenced to the rising edge of output
clocks (C and C, or K and K when in single clock mode).

All synchronous data inputs (D
registers controlled by the rising edge of input clocks (K and

). All synchronous data outputs (Q

K
registers controlled by the rising edge of the output clocks (C

) pass through input

[x:0]

) pass through output

[x:0]

and C, or K and K when in single clock mode).
All synchronous control (RPS

, WPS, BWS

through input registers controlled by the rising e dge of input

) inputs pass

[0:x]

clocks (K and K).
CY7C1305BV25 is described in the following sections. The

same basic descriptions apply to CY7C1307BV25.

Read Operations

The CY7C1305BV25 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS
Clock (K). The address presented to Address inputs are stored

active at the rising edge of the Positive Input

in the Read address register. Following the next K clock rise
the corresponding lowest order 18-bit word of data is driven
onto the Q

using C as the output timing reference. On the

[17:0]

) and

subsequent rising edge of C
onto the Q
words have been driven out onto Q

. This process continues until all four 18-bit data

[17:0]

will be valid 2.5 ns from the rising e dge of the output clock
(C and C

, or K and K when in single clock mode, 250-MHz

the next 18-bit data word is driven

. The requested data

[17:0]

device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes 2 clock cycles to
complete. Therefore, Read accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C,

or K and K when in single clock mode).

When the read port is deselected, the CY7C1305BV25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D
into the lower 18-bit Write Data register provided BWS
both asserted active. On the subsequent rising edge of the
negative input clock (K

) the information presented to D
also stored into the Write Data Register provided BWS
both asserted active. This process continues for one more

is latched and stored

[17:0]

[1:0]

[17:0]

[1:0]

are

is

are

cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device wil l ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans­ferred into the device on every rising edge of the input cl ocks
(K and K

).

Document #: 38-05630 Rev. *A Page 5 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1305BV25.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter­mined by BWS0 and BWS1, which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that b yte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1305BV25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K

) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C
a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1305BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This

Application Example

HIGH at power-on. This function is

[1]

includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

Read and Write accesses must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.

Depth Expansion

The CY7C1305BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles upon power-up to account for drifts in supply voltage
and temperature.

to allow the SRAM to adjust its

SS

, with

Note:

1. The above application shows four QDR-I being used.

Document #: 38-05630 Rev. *A Page 6 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Truth Table

[2, 3, 4, 5, 6, 7, 8, 9]

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

Load address on the rising

L-H H

[8]

[9]

L

D(A+00) at
K(t+1) ↑

D(A+01) at
K

(t+1) ↑

D(A+10) at
K(t+2) ↑

D(A+11) at

K(t+2) ↑
edge of K; wait one cycle;
input write data on two
consecutive K and K

rising

edges.
Read Cycle:

Load address on the rising

L-H L

[9]

X Q(A+00) at

C(t+1) ↑

Q(A+01) at
C

(t+1) ↑

Q(A+10) at
C(t+2) ↑

Q(A+11) at

C(t+2) ↑
edge of K; wait one cycle;
read data on two consec­utive C and C

NOP: No operation L-H H H D = X

rising edges.

Q = High-Z

D = X
Q = High-Z

D = X
Q = High-Z

D = X

Q = High-Z

Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous state

Write Cycle Descriptions (CY7C1305BV25)

BWS0BWS

L L L-H – During the Data portion of a Write sequence, both bytes (D
L L – L-H During the Data portion of a Write sequence, both bytes (D
L H L-H – During the Data portion of a Write sequence, only the lower byte (D

L H – L-H During the Data portion of a Write sequence, only the lower byte (D

H L L -H – During the Data portion of a Write sequence, only the upper byte (D

H L – L-H During the Data portion of a Write sequence, only the upper byte (D

KK Comments

1

device. D

device. D

[17:9]

[17:9]

the device. D

the device. D

[2, 10]

will remain unaltered.

will remain unaltered.

will remain unaltered.

[8:0]

will remain unaltered.

[8:0]

) are written into the device.

[17:0]

) are written into the device.

[17:0]

) is written into the

[8:0]

) is written into the

[8:0]

) is written into

[17:9]

) is written into

[17:9]

H H L-H – No data is written into the device during this portion of a Write operation.
H H – L-H No data is written into the device during this portion of a Write operation.

Notes:

2. X = Don't Care, H = Logic HIGH, L = Logic LOW,

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+1 0 and A+1 1 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read request.

10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

↑represents rising edge.

and BWS1 in the case of CY7C1305BV25 and BWS2 and BWS3 in

0

Document #: 38-05630 Rev. *A Page 7 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Write Cycle Descriptions

BWS

BWS

0

BWS

1

2

(CY7C1307BV25)

BWS

3

[2, 10]

KK Comments

L L L L L-H – During the Data portion of a Write sequence, all four bytes

(D

) are written into the device.

[35:0]

L L L L – L-H During the Data portion of a Write sequence, all four bytes

(D

) are written into the device.

[35:0]

L H H H L-H – During the Data portion of a Write sequence, only the lower

byte (D
unaltered.

) is written into the device. D

[8:0]

will remain

[35:9]

L H H H – L-H During the Data portion of a Write sequence, only the lower

byte (D

[8:0]

unaltered.

) is written into the device. D

will remain

[35:9]

H L H H L-H – During the Data portion of a Write sequence, only the byte

) is written into the device. D

(D

[17:9]

remain unaltered.

[8:0]

and D

[35:18]

H L H H – L-H During the Data portion of a Write sequence, only the byte

(D

) is written into the device. D

[17:9]

remain unaltered.

[8:0]

and D

[35:18]

H H L H L-H – During the Data portion of a Write sequence, only the byte

(D
remain unaltered.

) is written into the device. D

[26:18]

[17:0]

and D

[35:27]

H H L H – L-H During the Data portion of a Write sequence, only the byte

(D
remain unaltered.

) is written into the device. D

[26:18]

[17:0]

and D

[35:27]

H H H L L-H During the Data portion of a Write sequence, only the byte

(D
unaltered.

) is written into the device. D

[35:27]

will remain

[26:0]

H H H L – L-H During the Data portion of a Write sequence, only the byte

(D
unaltered.

) is written into the device. D

[35:27]

will remain

[26:0]

H H H H L-H – No data is written into the device during this portion of a Write

operation.

H H H H – L-H No data is written into the device during this portion of a write

operation.

will

will

will

will

Document #: 38-05630 Rev. *A Page 8 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP op erates using
JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the

) for five rising

DD

TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction

Document #: 38-05630 Rev. *A Page 9 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR sta te. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the T AP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee th at the boundary scan regi ster will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

CS

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.

EXTEST Output Bus Tri-state

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05630 Rev. *A Page 10 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

TAP Controller State Diagram

1

TEST-LOGIC
RESET

0

0

TEST-LOGIC/

1

IDLE

[11]

SELECT
DR-SCAN

0

1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

1

SELECT

1

IR-SCAN

0

1

CAPTURE-IR

0

0

SHIFT-IR

1

1

EXIT1-IR

0

0

0

1

1

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

11.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

0

1

0

Document #: 38-05630 Rev. *A Page 11 of 21

[+] Feedback

TAP Controller Block Diagram

TDI

Selection
Circuitry

Bypass Register

Instruction Register

CY7C1305BV25
CY7C1307BV25

0

012

Selection
Circuitry

TDO

29

3031

012..

Identification Register

.

.106

012..

Boundary Scan Register

TCK
TMS

TAP Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

V
V
V
V
V
V
I

OH1
OH2
OL1
OL2
IH
IL

X

Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.7 V
Output LOW Voltage IOL = 100 µA0.2V
Input HIGH Voltage 1.7 V
Input LOW Voltage –0.3 0.7 V
Input and Output Load Current GND ≤ VI ≤ V

Over the Operating Range

TAP AC Switching Characteristics Over the Operating Range

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

Set-up Times

t

TMSS

t

TDIS

t

CS

Hold Times

t

TMSH

t

TDIH

t

CH

Notes:

12.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

13.Parameters t

14.Test conditions are specified using the load in TAP AC test conditions. t

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

TMS Set-up to TCK Clock Rise 10 ns
TDI Set-up to TCK Clock Rise 10 ns
Capture Set-up to TCK Rise 10 ns

TMS Hold after TCK Clock Rise 10 ns
TDI Hold after Clock Rise 10 ns
Capture Hold after Clock Rise 10 ns

and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

CS

TAP Controller

[12, 15, 17]

= −2.0 mA 1.7 V

OH

= −100 µA2.1 V

OH

+ 0.3 V

DD

−55µA

R/tF

DDQ

[13, 14]

= 1 ns.

Document #: 38-05630 Rev. *A Page 12 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

TAP AC Switching Characteristics Over the Operating Range (continued)

[13, 14]

Parameter Description Min. Max. Unit

Output Times

t

TDOV

t

TDOX

TAP Timing and Test Conditions

TDO

TCK Clock LOW to TDO Valid 20 ns
TCK Clock LOW to TDO Invalid 0 ns

[14]

1.25V

50Ω

ALL INPUT PULSES

Z

=50Ω

0

(a)

GND

C

L

= 20 pF

0V

t

TH

2.5V

1.25V

t

TL

Test Clock
TCK

t

TMSS

t

TMSH

t

TCYC

Test Mode Select
TMS

t

TDIS

t

TDIH

Test Data-In
TDI

Test Data-Out
TDO

t

TDOX

t

TDOV

Identification Register Definitions

Value

Instruction Field

Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 01011010011010101 01011010011100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.

DescriptionCY7C1305BV25 CY7C1307BV25

Document #: 38-05630 Rev. *A Page 13 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan regi ster between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document #: 38-05630 Rev. *A Page 14 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
2 6N 29 9G 56 6A 83 1J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
5 7R 32 9F 59 4A 86 3J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L

9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F

Document #: 38-05630 Rev. *A Page 15 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage on V
Supply Voltage on V
DC Applied to Outputs in High-Z State –0.5V to V
DC Input Voltage

Relative to GND.......–0.5V to + 3.6V

DD

Relative to GND.....–0.5V to + V

DDQ

[15]

...............................–0.5V to VDD + 0.5V

DDQ

DD

+ 0.5V

Electrical Characteristics Over the Operating Range

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current................................................... > 200 mA

Operating Range

Range

Te m pe r ature (T

A)

Com’l 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V
Ind’l –40°C to +85°C

[17]

Ambient

[16]

V

DD

V

DDQ

[16]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

I

DD

I

SB1

Power Supply Voltage 2.4 2.5 2.6 V
I/O Supply Voltage 1.4 1.5 1.9 V
Output HIGH Voltage Note 18 V
Output LOW Voltage Note 19 V
Output HIGH Voltage I
Output LOW Voltage I
Input HIGH Voltage
Input LOW Voltage

[15]

[15, 20]

Input Load Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage

[21]

VDD Operating Supply V

Automatic
Power-Down
Current

= –0.1 mA, Nominal Impedance V

OH

= 0.1 mA, Nominal Impedance V

OH

DDQ

Output Disabled –5 5 µA

DDQ,

Typic al value = 0.75V 0.68 0.75 0.95 V

DD

f = f

= Max., I

= 1/t

MAX

OUT

CYC

= 0 mA,

Max. VDD, Both Ports
Deselected,V
f = f

MAX

≤ VIH or VIN < VIL

IN

= 1/t

CYC,

Inputs Static

/2 – 0.12 V

DDQ

– 0.12 V

DDQ/2

– 0.2 V

DDQ

SS

V

+ 0.1 V

REF

–0.3 V

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+ 0.3 V

DDQ

– 0.1 V

REF

–5 5 µA

400 mA

200 mA

AC Input Requirements Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit

V

IH

V

IL

Thermal Resistance

Input HIGH Voltage V

+ 0.2 – – V

REF

Input LOW Voltage – – V

[22]

– 0.2 V

REF

165 FBGA

Parameter Description Test Conditions

Θ

JA

Θ

JC

Notes:

15.Overshoot: V

16.Power-up: Assumes a linear ramp from 0V to V

17.All Voltage referenced to Ground.

18.Output are impedance controlled. I

19.Output are impedance controlled. I

20.This spec is for all inputs except C and C

(Min.) = 0.68V or 0.46V

21.V

REF

22.Tested initially and af ter any design or process change that may affect these parameters.

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

(AC) < V

IH

+0.85V (Pulse width less than t

DDQ

OH
OL

, whichever is larger, V

DDQ

Test conditions follow standard test methods and proce­dures for measuring thermal impedance, per
EIA/JESD51.

/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than t

CYC

(min.) within 200 ms. During this time V

DD

= –(V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

= (V

2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ/

Clock. For C and C Clock, VIL(Max.) = V

(Max.) = 0.95V or 0.54V

REF

REF

– 0.2V.

DDQ

< V

and V

IH

DD

DDQ

, whichever is smaller.

< VDD.

Package Unit

16.7 °C/W

2.5 °C/W

/2).

CYC

V

Document #: 38-05630 Rev. *A Page 16 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Capacitance

[22]

Parameter Description Test Conditions Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

O

Clock Input Capacitance 6 pF
Output Capacitance 7 pF

V
V

= 2.5V.

DD
DDQ

= 1.5V

5pF

AC Test Loads and Waveforms

V

= 0.75V

REF

(a)

0.75V

Z

0

RQ =
250

= 50Ω

Ω

V

REF

= 50Ω

R

L

= 0.75V

V

REF

OUTPUT

Device
Under
Test

ZQ

0.75V

RQ =
250

(b)

R = 50Ω

5pF

Ω

0.25V

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2 V/ns

V

REF

OUTPUT
Device

Under
Test

ZQ

[23]

Document #: 38-05630 Rev. *A Page 17 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Switching Characteristics Over the Operating Range

Cypress

Parameter

[24]

t

Power

Consortium

Parameter Description

VCC (typical) to the First Access Read or Write 10 µs

[23]

Cycle Time

t

CYC

t

KH

t

KL

t

KHKH

t

KHCH

t

KHKH

t

KHKL

t

KLKH

t

KHKH

t

KHCH

K Clock and C Clock Cycle Time 6.0 ns
Input Clock (K/K and C/C) HIGH 2.4 ns
Input Clock (K/K and C/C) LOW 2.4 ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge

to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns

Set-up Times

t

SA

t

SC

t

SD

t

SA

t

SC

t

SD

Address Set-up to Clock (K and K) Rise 0.7 ns
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
D

Set-up to Clock (K and K) Rise 0.7 ns

[x:0]

Hold Times

t

HA

t

HC

t

HD

t
t

t

HA
HC

HD

Address Hold after Clock (K and K) Rise 0.7 ns
Control Signals Hold after Clock (K and K) Rise

(RPS

, WPS, BWS0, BWS1)

D

Hold after Clock (K and K) Rise 0.7 ns

[x:0]

Output Times

t

CO

t

DOH

t

CHZ

t

CLZ

Notes:

23.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,V
pulse levels of 0.25V to 1.25V, and output loading of the specified I

24.This part has a voltage regulator that steps down the volt age inte rnally; t
or Write operation can be init iated.

25.At any given voltage and temperature t

26.t

CHZ

t

CHQV

t

CHQX

t

CHZ

t

CLZ

, t

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CLZ

C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns
Clock (C and C) rise to High-Z (Active to High-Z)
Clock (C and C) rise to Low-Z

is less than t

CHZ

CLZ

and, t

[25, 26]

and load capacitance shown in (a) of AC Test Loads.

OL/IOH

is the time power needs to be supplied above VDD minimum initially before a Read

Power

less than tCO.

CHZ

[25, 26]

[25]

167 MHz

2.7 3.3 ns

0.7 ns

1.2 ns

= 0.75V, RQ = 250Ω, V

REF

UnitMin. Max.

2.5 ns

2.5 ns

= 1.5V, input

DDQ

Document #: 38-05630 Rev. *A Page 18 of 21

[+] Feedback

W

3

D

CY7C1305BV25
CY7C1307BV25

Switching Waveforms

NOP NOP
1

K

t

K

RPS

PS

A

D

t

KH

KL

t t

SC

t

SAtHA

[27, 28, 29]

READ READWRITE WRITE
23456

A0

t

CYC

HC

A1

t

KHKH

t

t

HC

SC

A2

t

HD

t

SD

D10 D11 D12 D13 D30 D31 D32 D3

A3

t

SD

t

HD

7

Qx3

Q

t

KHCH

C

t

KHCH

C

Notes:

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forward ed immediately as read results.This note applies to t he whole diagram.

t

CYC

t

t

CO

CLZ

Q00 Q03

Q01 Q02 Q23Q22Q20 Q21

t

CO

t

KHKH

t

DOH

t

DOH

t

KH

DON’T CARE UNDEFINE

t

CHZ

t

KL

Document #: 38-05630 Rev. *A Page 19 of 21

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1305BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1307BV25-167BZC
CY7C1305BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1307BV25-167BZXC
CY7C1305BV25-167BZI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1307BV25-167BZI
CY7C1305BV25-167BZXI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1307BV25-167BZXI

Package Diagram

PIN 1 CORNER

PIN 1 CORNER

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

SEATING PLANE

15.00±0.10

A

0.25 C

visit www.cypress.com for actual products offered”.

Package
Diagram Package Type

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

TOP VIEW

TOP VIEW

1110986754321

1110986754321

1.00

14.00

14.00

15.00±0.10

7.00

A

B

0.15(4X)

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

13.00±0.10

0.35±0.06

1.40 MAX.

0.35±0.06

0.15 C

1.40 MAX.

15.00±0.10

A

0.15 C

BOTTOM VIEW

11

11

1.00

7.00

5.00

5.00

10.00

B

13.00±0.10

BOTTOM VIEW

Ø0.05 M C

Ø0.05 M C

Ø0.25MCAB

-0.06

Ø0.25 M C A B

Ø0.50 (165X)

+0.14

Ø0.50 (165X)

10.00

13.00±0.10

PIN1CORNER

-0.06

2345678910

+0.14

1.00

1.00

PIN 1 CORNER

1

2345678910

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

Operating

Range

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Quad Data Rate SRAM and QDR SRAM co mprise a new family of products developed by Cypress, IDT, NEC, Renesas and
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05630 Rev. *A Page 20 of 21

© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch an ge wi t hout notice. Cypress Semiconductor Corporation assumes no responsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CY7C1305BV25
CY7C1307BV25

Document History Page

Document Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR™ Architecture
Document Number: 38-05630

REV. ECN NO. Issue Date

** 253049 See ECN SYT New Data Sheet

*A 436864 See ECN NXR Converted fro m Preli mi nary to Final.

Orig. of
Change Description of Change

Removed 133 MHz & 100 MHz from product offering.
Included industrial Operating Range.
Changed C/C
Changed t
and changed t
Characteristics table

Description in the Features Section & Pin Description Table.

from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz

TCYC

TH

and t

from 40 ns to 20 ns in TAP AC Switching

TL

Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Modified the Description of IX from Input Load current to Input Leakage
Current on page # 16.
Modified test condition in note# 16 from V
Updated the Ordering Information table and replaced the Package Name

DDQ

< V

Column with Package Diagram.

, which enables the

DDQ

Relative to GND

DDQ

DDQ

DD to VDDQ

≤ V

to V

DD

DD.

Document #: 38-05630 Rev. *A Page 21 of 21

[+] Feedback