Cypress Semiconductor CY7C1303BV25, CY7C1306BV25 Specification Sheet

Q

tecture

CY7C1303BV25

CY7C1306BV25

18-Mbit Burst of 2 Pipelined SRAM with

DR™ Archi

Features

• Separate independent Read and Write data ports
— Supports concurrent tra nsactions

• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K
— SRAM uses rising edg es only

• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JT A G In terface

• Variable Impedance HSTL

) for precise DDR timing

) to minimize

Configurations

CY7C1303BV25 – 1M x 18
CY7C1306BV25 – 512K x 36

Functional Description

The CY7C1303BV25 and CY7C1306BV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR™ archi­tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303BV25/
CY7C1306BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter­faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K
device on every rising edge of the output clock (C and C
and K

when in single clock mode) thereby maximizing perfor­mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303BV25) or two
36-bit words (CY7C1306BV25) that burst sequentially into or
out of the device.

Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

input clocks. Writes are

) and out of the

clock.

, or K

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05627 Rev. *A Revised April 3, 2006

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Logic Block Diagram (CY7C1303BV25)

D

A

(18:0)

Vref

WPS
BWS

BWS

[17:0]

19

K
K

0
1

18

Address
Register

CLK
Gen.

Control
Logic

Write
Data Reg

512Kx18
Memory

Array

Write Add. Decode

Read Data Reg.

512Kx18
Memory

Array

36

Write
Data Reg

18

18

Read Add. Decode

Reg.

Reg.

Address
Register

Control
Logic

Reg.

18

CY7C1303BV25
CY7C1306BV25

A

(18:0)

19

RPS

C
C

18

18

Q

[17:0]

Logic Block Diagram (CY7C1306BV25)

D

A

(17:0)

Vref

WPS
BWS

BWS

BWS
BWS

[35:0]

18

K
K

0
1

2
3

36

Address
Register

CLK
Gen.

Control
Logic

Write
Data Reg

256Kx36
Memory

Array

Write Add. Decode

Read Data Reg.

Write
Data Reg

256Kx36
Memory

Array

72

36

36

Read Add. Decode

Reg.

Reg.

Address
Register

Control
Logic

Reg.

36

36

18

RPS

C
C

36

A

(17:0)

Q

[35:0]

Selection Guide

Maximum Operating Frequency 167 MHz
Maximum Operating Current 500 mA

Document #: 38-05627 Rev. *A Page 2 of 19

CY7C1303BV25-167
CY7C1306BV25-167 Unit

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CY7C1303BV25
CY7C1306BV25

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1303BV25 (1M x 18)

1 2 34567891011

A NC Gnd/ 144M NC/ 36M WPS
B NC Q9 D9 A NC K BWS
C NC NC D10 VSS A A A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A C

BWS

1

K NC RPS A Gnd/ 72M NC

ANCNCQ8

0

AAATMSTDI

CY7C1306BV25 (512K x 36)

1 2 34567891011

A NC Gnd/ 288M NC/72M WPS
B Q27 Q18 D18 A BWS
C D27 Q28 D19 VSS A A A VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS A A A VSS Q10 D9 D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R TDO TCK A A A C

BWS

2
3

K BWS
KBWS0AD17Q17Q8

AAATMSTDI

RPS NC/36M Gnd/ 144M NC

1

Document #: 38-05627 Rev. *A Page 3 of 19

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CY7C1303BV25
CY7C1306BV25

Pin Definitions

Name I/O Description

D

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

BWS
BWS

, BWS1,

0

, BWS

2

Input-

Synchronous

3

A Input-

Synchronous

Q

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

K

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

TDO Output TDO pin for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.

Data input signals, sampled on the rising edge of K and K clocks during valid write opera­tions.

CY7C1303BV25 – D
CY7C1306BV25 – D

[17:0]
[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D

to be ignored.

[x:0]

Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations.
CY7C1303BV25 - BWS
CY7C1306BV25 - BWS0 controls D
controls D
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corresponding

[35:27]

controls D

0

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

and BWS3

byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read operations and

on the rising edge of K

for Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18)
for CY7C1303BV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306BV25. Therefore,
only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and
18 address inputs for CY7C1306BV25. These inputs are ignored when the appropriate port is
deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C
K

when in single clock mode. When the Read port is deselected, Q
three-stated.
CY7C1303BV25 - Q
CY7C1306BV25 - Q

[17:0]
[35:0]

clocks during Read operations or K and

are automatically

[x:0]

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the K clock. Each read access consists of a burst
of two sequential 18-bit or 36-bit transfers.

to clock out the Read

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

device and to drive out data through Q
on the rising edge of K.

out data through Q

data bus impedance. Q
connected between ZQ and ground. Alternately, this pin can be connected directly to V

when in single clock mode.

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a resistor

[x:0]

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

when in single clock mode. All accesses are initiated

[x:0]

DDQ

, which

unconnected.

Document #: 38-05627 Rev. *A Page 4 of 19

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CY7C1303BV25
CY7C1306BV25

Pin Definitions (continued)

Name I/O Description

NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to any

GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25.
NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25.
GND/144M Input Address expansion for 144M. This pin has to be tied to GND on

GND/288M Input Address expansion for 288M. This pin has to be tied to GND on CY7C1306BV25.
NC N/A Not connected to the die. Can be tied to any voltage level.
V

V
V
V

REF

DD
SS
DDQ

Input-

Reference

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

voltage level on CY7C1303BV25/CY7C1306BV25.

CY7C1303BV25/CY7C1306BV25.

Reference V oltage Input. S tatic input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.

Introduction

Functional Overview

The CY7C1303BV25/CY7C1306BV25 are synchronous
pipelined Burst SRAM equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, this architecture completely
eliminates the need to “turn-around” the data bus and avoids
any possible data contention, thereby simplifying system
design. 38-05627Each access consists of two 18-bit data
transfers in the case of CY7C1303BV25, and two 36-bit data
transfers in the case of CY7C1306BV25, in one clock cycle.

Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K
all output timings are referenced to rising edge of output clocks
(C and C

All synchronous data inputs (D
registers controlled by the rising edge of the input clocks (K
and K
output registers controlled by the rising edge of the output
clocks (C and C

All synchronous control (RPS
through input registers controlled by the rising e dge of input
clocks (K and K

or K and K when in single clock mode).

) pass through input

[x:0]

). All synchronous data outputs (Q

, or K and K when in single clock mode).

, WPS, BWS

).

) pass through

[x:0]

) inputs pass

[x:0]

The following descriptions take CY7C1303BV25 as an
example. The same basic descriptions apply to
CY7C1306BV25.

Read Operations

The CY7C1303BV25 is organized internally as 2 arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS

active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q

[17:0]

) and

using C as

the output timing reference. On the subsequent rising edge of
C

the higher order data word is driven onto the Q

requested data will be valid 2.5 ns from the rising edge of the

[17:0]

. The

output clock (C and C, or K and K when in single clock mode,
250-MHz device).

Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
lower 18-bit Write Data register provided BWS
asserted active. On the subsequent rising edge of the negative
input clock (K
presented to D
provided BWS
are then written into the memory array at the specified

), the address is latched and the information

is stored into the Write Data register

[17:0]

are both asserted active. The 36 bits of data

[1:0]

is latched and stored into the

[17:0]

[1:0]

are both

location.
When deselected, the Write port will ignore all inputs after the

pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1303BV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter­mined by BWS0 and BWS1 which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1303BV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K

) that control both the input and output registers. This

Document #: 38-05627 Rev. *A Page 5 of 19

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CY7C1303BV25
CY7C1306BV25

operation is identical to the operation if the device had zero
skew between the K/K

and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C

HIGH at power-up.This function is

a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1303BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

Application Example

[1]

Depth Expansion

The CY7C1303BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the

to allow the SRAM to adjust its

SS

value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles to account for drifts in supply voltage and temperature.

, with

Truth Table

[2, 3, 4, 5, 6, 7]

Operation K RPS WPS DQ DQ

Write Cycle:
Load address on the rising edge of K
data on K and K

rising edges.

clock; input write

Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C

rising edges.

NOP: No Operation L-H H H D = X

Standby: Clock Stopped Stopped X X Previous

Notes:

1. The above application shows 4 QDR-I being used.

2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
symmetrically.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

L-H X L D(A+0) at

K(t) ↑

L-H L X Q(A+0) at

C(t+1)↑

Q = High-Z

State

D(A+1) at
K

(t) ↑

Q(A+1) at
C

(t+1) ↑

D = X
Q = High-Z

Previous
State

Document #: 38-05627 Rev. *A Page 6 of 19

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CY7C1303BV25
CY7C1306BV25

Write Descriptions (CY7C1303BV25)

BWS0BWS

L L L-H - During the Data portion of a Write sequence, both bytes (D
L L - L-H During the Data portion of a Write sequence, both bytes (D
L H L-H - During the Data portion of a Write sequence, only the lower byte (D

L H - L-H During the Data portion of a Write sequence, only the lower byte (D

H L L-H - During the Data portion of a Write sequence, only the byte (D

H L - L-H During the Data portion of a Write sequence, only the byte (D

KK Comments

1

device. D

device. D

D

[8:0]

D

[8:0]

[2, 8]

remains unaltered.

[17:9]

remains unaltered.

[17:9]

remains unaltered.

remains unaltered.

) are written into the device.

[17:0]

) are written into the device.

[17:0]

) is written into the

[8:0]

) is written into the

[8:0]

) is written into the device.

[17:9]

) is written into the device.

[17:9]

H H L-H - No data is written into the device during this portion of a write operation.
H H - L-H No data is written into the device during this portion of a write operation.

Write Descriptions (CY7C1306BV25)

BWS0BWS1BWS2BWS

LLLLL-H-During the Data portion of a Write sequence, all four bytes (D

LLLL-L-HDuring the Data portion of a Write sequence, all four bytes (D

L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D

L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D

H L H H L-H - During the Data portion of a Write sequence, only the byte (D

H L H H - L-H During the Data portion of a Write sequence, only the byte (D

H H L H L-H - During the Data portion of a Write sequence, only the byte (D

H H L H - L-H During the Data portion of a Write sequence, only the byte (D

H H H L L-H - During the Data portion of a Write sequence, only the byte (D

H H H L - L-H During the Data portion of a Write sequence, only the byte (D

3

[2, 8]

KK Comments

written into the device.

written into the device.

is written into the device. D

is written into the device. D

written into the device. D

written into the device. D

written into the device. D

written into the device. D

written into the device. D

written into the device. D

will remain unaltered.

[35:9]

will remain unaltered.

[35:9]

and D

[8:0]

[8:0]

[17:0]

[17:0]

[26:0]

[26:0]

[35:18]

and D

[35:18]

and D

[35:27]

and D

[35:27]

will remain unaltered.

will remain unaltered.

will remain unaltered.

will remain unaltered.

will remain unaltered.

will remain unaltered.

[35:0]

[35:0]

[17:9]

[17:9]

[26:18]

[26:18]

[35:27]

[35:27]

) are

) are

[8:0]

[8:0]

) is

) is

) is

) is

) is

) is

HHHHL-H-No data is written into the device during this portion of a Write operation.
HHHH-L-HNo data is written into the device during this portion of a Write operation.

Note:

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
in the case of CY7C1306BV25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. 38-05627

, BWS1, in the case of CY7C1303BV25 and also BWS2 and BWS

0

)

)

3

Document #: 38-05627 Rev. *A Page 7 of 19

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CY7C1303BV25
CY7C1306BV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149 .1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the

) for five rising

DD

TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction

Document #: 38-05627 Rev. *A Page 8 of 19

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CY7C1303BV25
CY7C1306BV25

is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR sta te. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the T AP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guaran tee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

CS

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.

EXTEST Output Bus Tri-state

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05627 Rev. *A Page 9 of 19

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CY7C1306BV25

TAP Controller State Diagram

1

TEST-LOGIC
RESET

0

0

TEST-LOGIC/

1

IDLE

[9]

1

0

1

SELECT
DR-SCAN

0

1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

1

SELECT
IR-SCAN

0

1

CAPTURE-DR

0

0

SHIFT-IR

1

0

1

1

EXIT1-IR

0

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

0

1

0

Document #: 38-05627 Rev. *A Page 10 of 19

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TAP Controller Block Diagram

TDI

Selection
Circuitry

Bypass Register

Instruction Register

CY7C1303BV25
CY7C1306BV25

0

012

Selection
Circuitry

TDO

29

3031

012..

Identification Register

.

.106

012..

Boundary Scan Register

TCK
TMS

TAP Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

V
V
V
V
V
V
I

OH1
OH2
OL1
OL2
IH
IL

X

Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.7 V
Output LOW Voltage IOL = 100 µA0.2V
Input HIGH Volt age 1.7 V
Input LOW Voltage –0.3 0.7 V
Input and Output Load Current GND ≤ VI ≤ V

Over the Operating Range

OH
OH

TAP AC Switching Characteristics Over the Operating Range

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

Set-up Times

t

TMSS

t

TDIS

t

CS

Hold Times

t

TMSH

t

TDIH

t

CH

Notes:

10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

11. t

CS

12.Test conditions are specified using the load in TAP AC test conditions. t

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

TMS Set-up to TCK Clock Rise 10 ns
TDI Set-up to TCK clock Rise 10 ns
Capture Set-up to TCK Rise 10 ns

TMS Hold after TCK Clock Rise 10 ns
TDI Hold after Clock Rise 10 ns
Capture Hold after Clock Rise 10 ns

TAP Controller

[10, 14, 17]

= −2.0 mA 1.7 V
= −100 µA2.1V

+ 0.3 V

DD

−55µA

R/tF

DDQ

[11, 12]

= 1 ns.

Document #: 38-05627 Rev. *A Page 11 of 19

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CY7C1306BV25

TAP AC Switching Characteristics Over the Operating Range

[11, 12]

(continued)

Parameter Description Min. Max. Unit

Output Times

t

TDOV

t

TDOX

TAP Timing and Test Conditions

TDO

TCK Clock LOW to TDO Valid 20 ns
TCK Clock LOW to TDO Invalid 0 ns

[12]

1.25V

50Ω

ALL INPUT PULSES

Z

= 50Ω

0

(a)

GND

C

L

= 20 pF

0V

t

TL

t

TH

2.5V

1.25V

Test Clock
TCK

t

TMSS

t

TMSH

t

TCYC

Test Mode Select
TMS

t

TDIS

t

TDIH

Test Data-In
TDI

Test Data-Out
TDO

t

TDOX

t

TDOV

Identification Register Definitions

Value

Instruction Field

Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 01011010010010101 01011010010100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.

DescriptionCY7C1303BV25 CY7C1306BV25

Document #: 38-05627 Rev. *A Page 12 of 19

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CY7C1306BV25

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register

RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register

RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 1 11 Places the bypass register between TDI and TDO. This operation does not

between TDI and TDO. This operation does not affect SRAM operation.

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.

between TDI and TDO. Does not affect the SRAM operation.

affect SRAM operation.

Document #: 38-05627 Rev. *A Page 13 of 19

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CY7C1306BV25

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
2 6N 29 9G 56 6A 83 1J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
5 7R 32 9F 59 4A 86 3J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L

9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F

Document #: 38-05627 Rev. *A Page 14 of 19

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CY7C1303BV25
CY7C1306BV25

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage on VDD Relative to GND.......–0.5V to + 3.6V

Supply Voltage on V

Relative to GND.....–0.5V to + V

DDQ

DD

DC Applied to Outputs in

High-Z State..................................... ...–0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Operating Range

Range

Com’l 0°C to + 70°C 2.5 ± 0.1V 1.4V to 1.9V
Ind’l –40°C to + 85°C

[14]

[17]

...............................–0.5V to VDD + 0.5V

Ambient

Temperature (TA)V

DD

[13]

V

DDQ

[13]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

V

REF

I

X

I

OZ

I

DD

I

SB1

Power Supply Voltage 2.4 2.5 2.6 V
I/O Supply Voltage 1.4 1.5 1.9 V
Output HIGH Voltage Note 15 V
Output LOW Voltage Note 16 V
Output HIGH Voltage I
Output LOW Voltage I
Input HIGH Voltage
Input LOW Voltage
Input Reference Voltage

[17]

[17, 18]

[19]

Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V

Automatic
Power-Down
Current

= –0.1 mA, Nominal Impedance V

OH

= 0.1 mA, Nominal Impedance V

OL

Typical value = 0.75V 0.68 0.75 0.95 V

DDQ

Output Disabled –5 5 µA

DDQ,

= Max., I

DD

f = f
Max. V

V
Inputs Static

= 1/t

MAX

, Both Ports Deselected,

DD

≥ VIH or VIN ≤ VIL f = f

IN

OUT

CYC

= 0 mA,

MAX

=1/t

CYC,

/2 – 0.12 V

DDQ

– 0.12 V

DDQ/2

– 0.2 V

DDQ

SS

V

+ 0.1 V

REF

–0.3 V

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+ 0.3 V

DDQ

– 0.1 V

REF

–5 5 µA

500 mA

240 mA

AC Input Requirements Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

IH

V

IL

Thermal Resistance

Input HIGH Voltage V

+ 0.2 – – V

REF

Input LOW Voltage – – V

[20]

– 0.2 V

REF

Parameter Description Test Conditions 165 FBGA Package Unit

Θ

JA

Θ

JC

Notes:

13.Power-up: Assumes a linear ramp from 0V to V

14.All Voltage referenced to Ground.

15.Output are impedance controlled. I

16.Output are impedance controlled. I

17.Overshoot: V

18.This spec is for all inputs except C and C
(Min.) = 0.68V or 0.46V

19.V

REF

20.Tested initially and af ter any design or process change that may affect these parameters.

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

(AC) < V

IH

+0.85V (Pulse width less than t

DDQ

, whichever is larger, V

DDQ

T est conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51.

(min.) within 200 ms. During this time V

DD

= –V

OH
OL

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

= (V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

Clock. For C and C Clock, VIL(Max.) = V

/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than t

CYC

(Max.) = 0.95V or 0.54V

REF

< VDD and V

IH

– 0.2V.

REF

, whichever is smaller.

DDQ

DDQ

< V

DD

16.7 °C/W

6.5 °C/W

.

/2).

CYC

V

Document #: 38-05627 Rev. *A Page 15 of 19

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CY7C1306BV25

Capacitance

[23]

Parameter Description Test Conditions Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,
C
C

IN
CLK
O

Clock Input Capacitance 6 pF
Output Capacitance 7 pF

V
V

DD
DDQ

= 2.5V.

= 1.5V

5pF

AC Test Loads and Waveforms

V

= 0.75V

REF

V

REF

OUTPUT
Device

Under
Test

ZQ

Switching Characteristics

Cypress

Parameter

[22]

t

Power

Cycle Time

t

CYC

t

KH

t

KL

t

KHKH

t

KHCH

Set-up Times

t

SA

t

SC

t

SD

Hold Times

t

HA

t

HC

t

HD

Output Times

t

CO

t

DOH

t

CHZ

t

CLZ

Notes:

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, ti ming reference levels of 0.75V,Vref = 0.75V, RQ = 250

pulse levels of 0.25V to 1.25V, and output loading of the specified I

22.This part has a voltage regulator that steps down the voltage internally; t

or write operation can be initiated.

23.At any given voltage and temperature t

0.75V

(a)

Z

0

RQ =
250

= 50Ω

Ω

V

OUTPUT

Device
Under
Test

V

REF

= 50Ω

R

L

= 0.75V

Over the Operating Range

REF

ZQ

0.75V

RQ =
250

(b)

Ω

[21]

Consortium

Parameter Description

VCC (typical) to the First Access Read or Write 10 µs

t

KHKH

t

KHKL

t

KLKH

t

KHKH

t

KHCH

t

SA

t

SC

t

SD

t

HA

t

HC

t

HD

t

CHQV

t

CHQX

t

CHZ

t

CLZ

K Clock and C Clock Cycle Time 6.0 ns
Input Clock (K/K and C/C) HIGH 2.4 ns
Input Clock (K/K and C/C) LOW 2.4 ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise

(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns

Address Set-up to Clock (K and K) Rise 0.7 ns
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
D

Set-up to Clock (K and K) Rise 0.7 ns

[x:0]

Address Hold after Clock (K and K) Rise 0.7 ns
Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
D

Hold after Clock (K and K) Rise 0.7 ns

[x:0]

C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns
Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns
Clock (C and C) rise to High-Z (Active to High-Z)

and, t

[23, 24]

and load capacitance shown in (a) of AC test loads.

OL/IOH

CHZ

is the time power needs to be supplied above VDD minimum initially before a read

Power

less than tCO.

Clock (C and C) rise to Low-Z

is less than t

CHZ

CLZ

R = 50Ω

5pF

ALL INPUT PULSES

1.25V

0.75V

0.25V
Slew Rate = 2 V/ns

167 MHz

2.7 3.3 ns

[23, 24]

1.2 ns

Ω, V

[21]

2.5 ns

= 1.5V, input

DDQ

UnitMin. Max.

Document #: 38-05627 Rev. *A Page 16 of 19

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0

W

D

CY7C1303BV25

CY7C1306BV25

Switching Waveforms

READ READ WRITE WRITEWRITE NOPREAD WRITE NOP
12345 8 1

K

RPS

t

KH

K

PS

A0

A

t

SA

D

D10

Q

t

KL

tSC

A1

t

HA

D11 D30 D31 D50 D51 D60 D61

[25, 26, 27]

A2

t

t

SA

HA

t

tHC

t

SD

6

CYC

A3 A4

t

HD

Q00 Q21Q01 Q20 Q40 Q41

t

KHKH

A5 A6

t

SD

7

t

HD

9

t

CHZ

tCYC

t

DOH

t

CLZ

t

KHCH

C

C

Notes:

24.t

, t

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CHZ

25.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

26.Outputs are disabled (High-Z) one clock cycle after a NOP.

27.In this example, if address A2 = A1 then data Q2 0= D10 and Q21 = D1 1. Write data is forwarded immedi ately as read results.This note applies to the whole diagram.

CLZ

t

KHCH

t

KH

t

KL

t

CO

t

KHKH

t

CO

t

DOH

DON’T CARE UNDEFINE

Document #: 38-05627 Rev. *A Page 17 of 19

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CY7C1303BV25

CY7C1306BV25

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1303BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1306BV25-167BZC
CY7C1303BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1306BV25-167BZXC
CY7C1303BV25-167BZI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1306BV25-167BZI
CY7C1303BV25-167BZXI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1306BV25-167BZXI

Package Diagram

PIN 1 CORNER

PIN 1 CORNER

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

SEATING PLANE

15.00±0.10

A

0.25 C

visit www.cypress.com for actual products offered”.

Package

Diagram Package Type

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

TOP VIEW

TOP VIEW

1110986754321

1110986754321

1.00

14.00

14.00

15.00±0.10

7.00

A

B

0.15(4X)

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

13.00±0.10

0.35±0.06

1.40 MAX.

0.35±0.06

0.15 C

1.40 MAX.

15.00±0.10

A

0.15 C

BOTTOM VIEW

11

11

1.00

7.00

5.00

5.00

10.00

B

13.00±0.10

BOTTOM VIEW

Ø0.05 M C

Ø0.05 M C

Ø0.25MCAB

-0.06

Ø0.25 M C A B

Ø0.50 (165X)

+0.14

Ø0.50 (165X)

10.00

13.00±0.10

PIN1CORNER

-0.06

2345678910

+0.14

1.00

1.00

PIN 1 CORNER

1

2345678910

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

Operating

Range

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

Quad Data Rate™ SRAM and QDR™ SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05627 Rev. *A Page 18 of 19

© Cypress Semiconductor Corporation, 2006. The information contained herein is su bject to change without notice. Cypress Semiconduct or Corpo ration assu mes no resp onsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does no t authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1303BV25

CY7C1306BV25

Document History Page

Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05627

REV. ECN NO. Issue Date

** 253010 See ECN SYT New Data Sheet

*A 436864 See ECN NXR Converted from Preliminary to Final.

Orig. of

Change Description of Change

Removed 133 MHz & 100 MHz from product offering.
Included the Industrial Operating Range.
Changed C/C
Changed t
and changed t
Characteristics table

Description in the Features Section & Pin Description Table.

from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz

TCYC

TH

and t

from 40 ns to 20 ns in TAP AC Switching

TL

Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Modified the Description of IX from Input Load current to Input Leakage
Current on page # 15.
Modified test condition in note# 13 from V
Updated the Ordering Information table and replaced the Package Name

DDQ

< V

Column with Package Diagram.

, which enables the

DDQ

Relative to GND

DDQ

DD to VDDQ

DDQ

≤ V

to V

DD

DD.

Document #: 38-05627 Rev. *A Page 19 of 19

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