Cypress Semiconductor CY7C1302DV25 Specification Sheet

Q

CY7C1302DV25

9-Mbit Burst of Two Pipelined SRAMs

Features

• Separate independent Read and Write data ports
— Supports concurrent tra nsactions

• 167-MHz clock for high bandwidth
— 2.5 ns Clock-to-Valid access time

• 2-word burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167 MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edg es only

• Two input clocks for output dat a (C and C

) to minimize

clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JT A G In terface

Configurations

CY7C1302DV25 – 512K x 18

with

DR™ Architecture

Functional Description

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K
edge of the output clock (C and C
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.

clock. QDR has separate data inputs and

) and out of the device on every rising

, or K and K in a single clock

input clocks. All data outputs pass through output

(or K or K in a single clock

Logic Block Diagram (CY7C1302DV25)

D

[17:0]

A

(17:0)

18

K

Vref

WPS
BWS

0

BWS

1

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05625 Rev. *A Revised March 23, 2006

18

Address
Register

CLK
Gen.K

Control
Logic

Write
Data Reg

256Kx18
Memory
Array

Write Add. Decode

Read Data Reg.

Write
Data Reg

256Kx18
Memory
Array

36

18

18

Read Add. Decode

Reg.

Reg.

Address
Register

Control
Logic

Reg.

18

18

18

RPS

C
C

18

A

(17:0)

Q

[17:0]

[+] Feedback

CY7C1302DV25

Selection Guide

CY7C1302DV25-167 Unit

Maximum Operating Frequency 167 MHz
Maximum Operating Current 500 mA

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1302DV25 (512K x 18)

1 2 34567891011

A NC Gnd/144M NC/36M WPS
B NC Q9 D9 A NC K BWS
C NC NC D10 VSS A A A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDOTCKAAAC

BWS

1

K NC RPS NC/18M Gnd/72M NC

0

ANCNCQ8

AAATMSTDI

Pin Definitions

Name I/O Description

D

[17:0]

WPS

Input-

Synchronous

Input-

Synchronous

BWS
BWS

,

0
1

Input-

Synchronous

A Input-

Synchronous

Q

[17:0]

RPS

Outputs-

Synchronous

Input-

Synchronous

Data input signals, sampled on the rising edge of K and K clocks during valid Write opera­tions.

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,

a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D

to be ignored.

[17:0]

Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Write operations. Used to select which byte is written into the device during the current portion of
the Write operations. Bytes not written remain unaltered.
BWS

controls D

0

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

and BWS1 controls D

[8:0]

[17:9].

Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K

for active Read and Write operations. These address inputs are multiplexed for both Read and
Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18).
These inputs are ignored when the appropriate port is deselected.

Data Output signal s. These pins drive out the requested data during a Read operation. Valid data
is driven out on the rising edge of both the C and C
when in single clock mode. When the Read port is deselected, Q
three-stated.

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst of
two sequential transfers.

(write address) clocks

clocks during Read operations or K and K

are automatically

[17:0]

Document #: 38-05625 Rev. *A Page 2 of 18

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CY7C1302DV25

Pin Definitions (continued)

Name I/O Description

C Input-

Clock

Positive Input Clock for Output Data. C is used in conjunction with C
from the device. C and C

can be used together to deskew the flight times of various devices on

the board back to the controller. See application example for further details.

C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data

from the device. C and C

can be used together to deskew the flight times of various devices on

the board cack to the controller. See application example for further details.

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

device and to drive out data through Q
on the rising edge of K.

K

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the

device and to drive out data through Q

when in single clock mode. All accesses are initiated

[17:0]

when in single clock mode.

[17:0]

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

data bus impedance. Q
between ZQ and ground. Alternately, this pin can be connected directly to V

output impedance is set to 0.2 x RQ, where RQ is a resistor connected

[17:0]

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC/18M N/A Address expansion for 18M. This is not connected to the die and so can be tied to any voltage

level.
NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any voltage

level.
GND/72M Input Address expansion for 72M. This must be tied LOW.
GND/144M Input Address expansion for 144M. This must be tied LOW.
NC N/A Not connected to the die. Can be tied to any voltage level.
V

V
V
V

REF

DD
SS
DDQ

Input-

Reference

Power Supply Power supply inputs to the core of the device.

Ground Grou nd for the device.

Power Supply Power supply inputs for the outputs of the device.

Reference Volt age Input. Static input used to set the reference level for HSTL inputs and Outputs

as well as AC measurement points.

to clock out the Read data

, which enables

DDQ

Introduction

Functional Overview

The CY7C1302DV25 is a synchronous pipelined Burst SRAM
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-I completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. 38-05625

Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K
all output timing is referenced to the output clocks (C and C,
or K and K when in single clock mode).

All synchronous data inputs (D
registers controlled by the input clocks (K and K

Document #: 38-05625 Rev. *A Page 3 of 18

[17:0]

) and

) pass through input

). All

synchronous data outputs (Q
registers controlled by the rising edge of the output clocks (C
and C

, or K and K when in single clock mode).

All synchronous control (RPS
through input registers controlled by the rising edge of input
clocks (K and K

).

) pass through output

[17:0]

, WPS, BWS

[1:0]

) inputs pass

Read Operations

The CY7C1302DV25 is organized internally as 2 arrays of
256K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS

active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q
the output timing reference. On the subsequent rising edge of

the higher order data word is driven onto the Q

C
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C

, or K and K when in single clock mode,

using C as

[17:0]

[17:0]

. The

167-MHz device).

[+] Feedback

CY7C1302DV25

Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
Write Data register provided BWS
active. On the subsequent rising edge of the negative input

is latched into the lower 18-bit

[17:0]

are both asserted

[1:0]

clock (K), the address is latched and the information presented
to D
BWS
written into the memory array at the specified location.

is stored into the Write Data register provided

[17:0]

are both asserted active. The 36 bits of data are then

[1:0]

When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1302DV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter­mined by BWS
of 18-bit data word. Asserting the appropriate Byte Write

and BWS1 which are sampled with each set

0

Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that b yte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
38-05625

Single Clock Mode

The CY7C1302DV25 can be used with a single clock mod e.
In this mode the device will recognize only the pair of input
clocks (K and K

Application Example

) that control both the input and output

[1]

registers. This operation is identical to the operation if the
device had zero skew between the K/K

and C/C clocks. All
timing parameters remain the same in this mode. To use this
mode of operation, the user must tie C and C

HIGH at
power-up.This function is a strap option and not alterable
during device operation.

Concurrent Tr a ns a ct ion s

The Read and Write ports on the CY7C1302DV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

Depth Expansion

The CY7C1302DV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the

to allow the SRAM to adjust its

SS

value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
=1.5V . The output impedance is adjusted every 1024 cycles to

, with V

DDQ

account for drifts in supply voltage and temperature.

Note:

1. The above application shows 4 QDR-I being used.

Document #: 38-05625 Rev. *A Page 4 of 18

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CY7C1302DV25

Truth Table

[2, 3, 4, 5, 6, 7]

Operation K RPS WPS DQ DQ

Write Cycle:

L-H X L D(A+0) at K(t) ↑ D(A+1) at K

(t) ↑
Load address on the rising edge of K
clock; input write data on K and K

rising

edges.
Read Cycle:

L-H L X Q(A+0) at C(t+1)↑ Q(A+1) at C

(t+1) ↑
Load address on the rising edge of K
clock; wait one cycle; read data on 2
consecutive C and C rising edges.

NOP: No Operation L-H H H D = X

Q = High-Z

D = X

Q = High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

Write Cycle Descriptions

BWS0BWS

L L L-H – During the Data portion of a Write sequence, both bytes (D
L L – L-H During the Data portion of a Write sequence, both bytes (D
L H L-H – During the Data portion of a Write sequence, only the lower byte (D

L H – L-H During the Data portion of a Write sequence, only the lower byte (D

H L L-H – During the Data portion of a Write sequence, only the byte (D

H L – L-H During the Data portion of a Write sequence, only the byte (D

KK Comments

1

[2,8]

device. D

device. D

D

[8:0]

D

[8:0]

[17:9]

[17:9]

remains unaltered.

remains unaltered.

remains unaltered.

remains unaltered.

) are written into the device.

[17:0]

) are written into the device.

[17:0]

) is written into the

[8:0]

) is written into the

[8:0]

) is written into the device.

[17:9]

) is written into the device.

[17:9]

H H L-H – No da ta is written into the device during this portion of a Write operation.
H H – L-H No da ta is written into the device during this portion of a Write operation.

Notes:

2. X = Don't Care, H = Logic HIGH, L = Logic LOW,

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
symmetrically. 38-05625

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
as the set-up and hold requirements are achieved. 38-05625

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

↑ represents rising edge.

, BWS1 can be altered on different portions of a Wri te cycle, as l ong

0

Document #: 38-05625 Rev. *A Page 5 of 18

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CY7C1302DV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the

) for five rising

DD

TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction

Document #: 38-05625 Rev. *A Page 6 of 18

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CY7C1302DV25

is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR sta te. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the T AP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

CS

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.

EXTEST Output Bus Three-state

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.

The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller , it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05625 Rev. *A Page 7 of 18

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CY7C1302DV25

TAP Controller State Diagram

1

TEST-LOGIC
RESET

0

0

TEST-LOGIC/

1

IDLE

[9]

1

0

1

SELECT
DR-SCAN

1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

1

SELECT
IR-SCAN

0

0

1

CAPTURE-DR

0

0

SHIFT-IR

1

0

1

1

EXIT1-IR

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

0

1

0

Document #: 38-05625 Rev. *A Page 8 of 18

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TAP Controller Block Diagram

TDI

Selection
Circuitry

Bypass Register

Instruction Register

CY7C1302DV25

0

012

Selection
Circuitry

TDO

29

3031

012..

Identification Register

.

.106

012..

Boundary Scan Register

TCK
TMS

TAP Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

V
V
V
V
V
V
I

OH1
OH2
OL1
OL2
IH
IL

X

Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.7 V
Output LOW Voltage IOL = 100 µA0.2V
Input HIGH Volt age 1.7 V
Input LOW Voltage –0.3 0.7 V
Input and Output Load Current GND ≤ VI ≤ V

Over the Operating Range

TAP AC Switching Characteristics Over the Operating Range

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

Set-up Times

t

TMSS

t

TDIS

t

CS

Hold Times

t

TMSH

t

TDIH

t

CH

Notes:

10.These characteristics pertain to the TAP input s (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11. T

and TCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

CS

12.Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

TMS Set-up to TCK Clock Rise 10 ns
TDI Set-up to TCK Clock Rise 10 ns
Capture Set-up to TCK Rise 10 ns

TMS Hold after TCK Clock Rise 10 ns
TDI Hold after Clock Rise 10 ns
Capture Hold after Clock Rise 10 ns

TAP Controller

[10, 13, 15]

= −2.0 mA 1.7 V

OH

= −100 µA2.1 V

OH

+ 0.3 V

DD

DDQ

[11, 12]

–5 5 µA

Document #: 38-05625 Rev. *A Page 9 of 18

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CY7C1302DV25

TAP AC Switching Characteristics Over the Operating Range (continued)

[11, 12]

Parameter Description Min. Max. Unit

Output Times

t

TDOV

t

TDOX

TAP Timing and Test Conditions

TDO

TCK Clock LOW to TDO Valid 20 ns
TCK Clock LOW to TDO Invalid 0 ns

[12]

1.25V

50Ω

ALL INPUT PULSES

Z

= 50Ω

0

(a)

GND

C

L

= 20 pF

0V

t

TH

2.5V

1.25V

t

TL

Test Clock
TCK

t

TMSS

t

TMSH

t

TCYC

Test Mode Select
TMS

t

TDIS

t

TDIH

Test Data-In
TDI

Test Data-Out
TDO

t

TDOX

t

TDOV

Identification Register Definitions

Value

Instruction Field

Revision Number (31:29) 000 Version number.
Cypress Device ID (28:12) 01011010010010110 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 Indicate the presence of an ID register.

DescriptionCY7C1302DV25

Document #: 38-05625 Rev. *A Page 10 of 18

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CY7C1302DV25

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boun dary scan register between TDI

and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document #: 38-05625 Rev. *A Page 11 of 18

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CY7C1302DV25

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
2 6N 29 9G 56 6A 83 1J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
5 7R 32 9F 59 4A 86 3J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L

9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F

Document #: 38-05625 Rev. *A Page 12 of 18

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CY7C1302DV25

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired.)

Latch-up Current..................................................... >200 mA

Storage Temperature.................................–65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage on VDD Relative to GND.......–0.5V to + 3.6V

Supply Voltage on V

DC Applied to Outputs in High-Z......... –0.5V to V

DC Input Voltage

Relative to GND.....–0.5V to + V

DDQ

[13

................................–0.5V to VDD + 0.5V

DDQ

DD

+ 0.5V

Operating Range

Range

Temperature (TA)V

Com’l 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V
Ind’l –40°C to +85°C

Ambient

DD

[14]

V

DDQ

[14]

Current into Outputs (LOW).........................................20 mA

Electrical Characteristics Over the Operating Range

[15]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

I

DD

I

SB1

Power Supply Voltage 2.4 2.5 2.6 V
I/O Supply Voltage 1.4 1.5 1.9 V
Output HIGH Voltage Note 16 V
Output LOW Voltage Note 17 V
Output HIGH Volt age I
Output LOW Voltage I
Input HIGH Voltage
Input LOW Voltage

[13]

[13, 18]

Input Load Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage

[19]

VDD Operating Supply V

Automatic
Power-Down
Current

= –0.1 mA, Nominal Impedance V

OH

= 0.1 mA, Nominal Impedance V

OL

DDQ

Output Disabled –5 5 µA

DDQ,

Typical value = 0.75V 0.68 0.75 0.95 V

DD

f = f

= Max., I

= 1/t

MAX

OUT

CYC

= 0 mA,

Max. VDD, Both Ports Deselected,

≥ VIH or VIN ≤ VIL, f =f

V

IN

=1/t

Inputs Static

CYC,

MAX

/2 – 0.12 V

DDQ

– 0.12 V

DDQ/2

– 0.2 V

DDQ

SS

V

+ 0.1 V

REF

–0.3 V

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+ 0.3 V

DDQ

– 0.1 V

REF

–5 5 µA

500 mA

240 mA

AC Input Requirements Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

IH

V

IL

Notes:

13.Overshoot: V

14.Power-up: Assumes a linear ramp from 0V to V

15.All voltage referenced to Ground.

16.Output are impedance controlled. I

17.Output are impedance controlled. I

18.This spec is for all inputs except C and C

19.V

REF

Input HIGH Voltage V

+ 0.2 – V

REF

Input LOW Voltage – V

(AC) < V

IH

(Min.) = 0.68V or 0.46V

+0.85V (Pulse width less than t

DDQ

, whichever is larger, V

DDQ

OH
OL

DD

= –(V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

= (V

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

Clock. For C and C Clock, VIL(Max.) = V

/2), Undershoot: V

CYC

(min.) within 200 ms. During this time VIH< V

(Max.) = 0.95V or 0.54V

REF

AC) > –1.5V (Pulse width less than t

IL(

– 0.2V.

REF

, whichever is smaller.

DDQ

DD

and V

DDQ

< VDD.

CYC

/2).

– 0.2 V

REF

V

Document #: 38-05625 Rev. *A Page 13 of 18

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CY7C1302DV25

Thermal Resistance

[20]

Parameter Description Test Conditions 165 FBGA Package Unit

Θ
Θ

Thermal Resistance (Junction to Ambient) Test conditions follow standard test

JA

Thermal Resistance (Junction to Case) 2.5 °C/W

JC

Capacitance

methods and procedures for measuring
thermal impedance, per EIA/JESD51.

[20]

16.7 °C/W

Parameter Description T est Conditions Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

O

Clock Input Capacitance 6 pF
Output Capacitanc e 7 pF

V

V

DD

DDQ

= 2.5V.

= 1.5V

5pF

AC Test Loads and Waveforms

V

= 0.75V

REF

(a)

0.75V

Z

0

RQ =
250

= 50Ω

Ω

V

REF

R

= 50Ω

L

= 0.75V

V

REF

OUTPUT

Device
Under
Test

ZQ

0.75V

RQ =
250

(b)

R = 50Ω

5pF

Ω

0.25V

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2 V/ns

[21]

V

REF

OUTPUT
Device

Under
Test

ZQ

Switching Characteristics

Cypress

Parameter

[22]

t

Power

Consortium

Parameter Description

VCC (typical) to the First Access Read or Write 10 µs

Over the Operating Range

[21]

167 MHz

Cycle Time

t

CYC

t

KH

t

KL

t

KHKH

t

KHCH

t

KHKH

t

KHKL

t

KLKH

t

KHKH

t

KHCH

K Clock and C Clock Cycle Time 6.0 ns
Input Clock (K/K and C/C) HIGH 2.4 ns
Input Clock (K/K and C/C) LOW 2.4 ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge

2.7 3.3 ns

to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns

Set-up Times

t

SA

t

SC

t

SD

t

SA

t

SC

t

SD

Address Set-up to Clock (K and K) Rise 0.7 ns
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
D

Set-up to Clock (K and K) Rise 0.7 ns

[17:0]

Hold Times

t

HA

t

HC

t

HD

Notes:

20.Tested initially and af ter any design or process change that may affect these parameters.

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, ti ming reference levels of 0.75V,Vref = 0.75V, RQ = 250W, V
pulse levels of 0.25V to 1.25V, and output loading of the specified I

22.This part has a voltage regulator that steps down the voltage internally; t
or write operation can be initiated.

t

HA

t

HC

t

HD

Address Hold after Clock (K and K) Rise 0.7 ns
Control Signals Hold after Clock (K and K) Rise

, WPS, BWS0, BWS1)

(RPS
D

Hold after Clock (K and K) Rise 0.7 ns

[17:0]

and load capacitance shown in (a) of AC test loads.

OL/IOH

is the time power needs to be supplied above VDD minimum initially before a read

Power

0.7 ns

= 1.5V, input

DDQ

UnitMin. Max.

Document #: 38-05625 Rev. *A Page 14 of 18

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CY7C1302DV25

Switching Characteristics Over the Operating Range (continued)

Cypress

Parameter

Output Times

t

CO

t

DOH

t

CHZ

t

CLZ

Notes:

, t

23.t

CHZ

24.At any given voltage and temperature t

Consortium

Parameter Description

t

CHQV

t

CHQX

t

CHZ

t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CLZ

C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns
Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns
Clock (C and C) Rise to High-Z (Active to High-Z)

less than tCO.

CHZ

[23, 24]

Clock (C and C) Rise to Low-Z

is less than t

CHZ

CLZ

and, t

[21]

[23, 24]

167 MHz

UnitMin. Max.

2.5 ns

1.2 ns

Document #: 38-05625 Rev. *A Page 15 of 18

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CY7C1302DV25

0

W

D

Switching Waveforms

READ READ WRITE WRITEWRITE NOPREAD WRITE NOP
12345 8 1

K

RPS

PS

t

KH

K

A0

A

t

SA

D

D10

t

KL

tSC

A1

t

HA

D11 D30 D31 D50 D51 D60 D61

[25, 26, 27]

A2

t

t

SA

HA

t

CYC

tHC

A3 A4

t

KHKH

6

A5 A6

7

9

t

t

SD

Q

t

CLZ

t

KH

t

KHCH

t

KL

t

KHCH

C

C

Notes:

25.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

26.Outputs are disabled (High-Z) one clock cycle after a NOP.

27.In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.

t

CO

t

KHKH

HD

Q00 Q21Q01 Q20 Q40 Q41

t

DOH

t

CO

tCYC

t

SD

t

DOH

t

HD

DON’T CARE UNDEFINE

t

CHZ

Document #: 38-05625 Rev. *A Page 16 of 18

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CY7C1302DV25

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com

Speed

(MHz) Ordering Code

Package

Diagram Package Type

167 CY7C1302DV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1302DV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1302DV25-167BZI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1302DV25-167BZXI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free

Package Diagram

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

TOP VIEW

TOP VIEW

PIN 1 CORNER

15.00±0.10

A

0.25 C

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

PIN 1 CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

13.00±0.10

SEATING PLANE

1110986754321

1110986754321

for actual products offered”.

1.00

14.00

14.00

15.00±0.10

7.00

A

B

0.15(4X)

0.15(4X)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

0.35±0.06

1.40 MAX.

0.35±0.06

0.15 C

1.40 MAX.

15.00±0.10

A

0.15 C

Operating

BOTTOM VIEW

11

11

1.00

7.00

5.00

5.00

10.00

B

13.00±0.10

NOTES :

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

PACKAGE CODE : BB0AC

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

BOTTOM VIEW

Ø0.05 M C

Ø0.05 M C

Ø0.25MCAB

-0.06

Ø0.25 M C A B

Ø0.50 (165X)

+0.14

Ø0.50 (165X)

10.00

13.00±0.10

51-85180-*A

PIN 1 CORNER

-0.06

2345678910

+0.14

1.00

1.00

PIN 1 CORNER

1

2345678910

51-85180-*A

1

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

J

J

K

K

L

L

M

M

N

N

P

P

R

R

Range

Quad Data Rate SRAM and QDR SRAM comprise a new family of p roducts developed by Cypress, IDT, NEC, Renesas and
Samsung. All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-05625 Rev. *A Page 17 of 18

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to chan ge without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title:CY7C1302DV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05625

REV. ECN NO. Issue Date

** 253010 See ECN SYT New Data Sheet

*A 436864 See ECN NXR Converted from Preliminary to Final

Orig. of
Change Description of Change

Removed 133 MHz & 100 MHz from product offering
Included the Industrial Operating Range.
Changed C/C
Changed t
changed t
table

Description in the Features Section & Pin Description Table

from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz and

TCYC

and t

TH

from 40 ns to 20 ns in T AP AC Switching Characteristics

TL

Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to V
minimum impedance mode
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Modified the Description of IX from Input Load current to Input Leakage
Current on page # 13
Modified test condition in note# 14 from V
Updated the Ordering Information table and replaced the Package Name

DDQ

Column with Package Diagram

CY7C1302DV25

, which enables the

DDQ

Relative to GND

< V

DD to VDDQ

DDQ

DDQ

≤ V

to V

DD

DD

Document #: 38-05625 Rev. *A Page 18 of 18

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