Cypress Semiconductor CY7C1231H Specification Sheet

A
B

CY7C1231H

2-Mbit (128K x 18) Flow-Through SRAM

with NoBL™ Architecture

Features

• Can support up to 133-MHz bus operations with ze ro
wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 128K x 18 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times
— 6.5 ns (133-MHz device)

• Clock Enable (CEN

• Synchronous self-timed write

• Asynchronous Output Enable

• Offered in JEDEC-standard lead-free 100-pin TQFP
package

• Burst Capability—linear or interleaved burst order

• Low standby powe r

) pin to suspend operation

Functional Description

[1]

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified b y
the Clock Enable (CEN

) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:B]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

MODE

CLK
CEN

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

C

ADV/LD

BW
BW

WE

ZZ

CE
CE
CE

A

B

OE

CE

1
2
3

ADDRESS
REGISTER

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

A1

D1

A0

D0

BURST
LOGIC

A1'

Q1

A0'

Q0

S
E

N

INPUT

S

E
A

M

P

S

E

WRITE

DRIVERS

MEMORY

ARRAY

REGISTER

O
U

T
P

D

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I
N
G

E

DQs
DQP
DQP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00207 Rev. *B Revised April 26, 2006

[+] Feedback

CY7C1231H

Selection Guide

133 MHz Unit

Maximum Access Time 6.5 ns
Maximum Operating Current 225 mA
Maximum CMOS Standby Current 40 mA

Pin Configuration

100-pin TQFP Pinout

BYTE B

V

DDQ

V

DQ
DQ

V

V

DDQ

DQ
DQ

V

V
DQ
DQ

V

DDQ

V
DQ
DQ

DQP

V

V

DDQ

NC
NC
NC

SS

NC
NC

SS

NC

DD

NC

SS

SS

NC

SS

NC
NC
NC

1CE2

A

A

CE

100

9998979695

1
2
3
4
5
6
7
8

B

9

B

10
11
12

B

13

B

14
15
16
17
18

B

19

B

20
21
22

B

23

B

24

B

25
26
27
28
29
30

BBWA

NC

NC

BW

9493929190898887868584

CE3VDDV

SS

CLKWECEN

CY7C1231H

OE

ADV/LD

NC(9M)

NC(18M)

838281

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A
NC
NC
V

DDQ

V

SS

NC
DQP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

A
A
A

A
A

BYTE A

A
A

A
A

313233

A

MODE

Document #: 001-00207 Rev. *B Page 2 of 12

34

A

A

3536373839

A

A1

A0

NC/288M

4041424344454647484950

A

A

SS

V

NC/144M

NC(72M)

A

NC(36M)

DD

V

A

A

A

NC/4M

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CY7C1231H

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

[A:B]

Input-

Synchronous

WE Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

CEN Input-

Synchronous

ZZ Input-

Asynchronous

DQ

DQP

s

[A:B]

I/O-

Synchronous

I/O-

Synchronous

Mode Input

Strap Pin
V
V

V

DD
DDQ

SS

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Ground Ground for the device.

NC – No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of
the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new address

should be driven LOW

in order to load a new address.

is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

, and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select/deselect the device.

CE

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave
as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE

is masked
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
When deasserted HIGH the Clock signal is masked. Since deasserting CEN
device, CEN

can be used to extend the previous cycle when required.

does not deselect the

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has
an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE

and DQP

DQ

s

the data portion of a write sequence, during the first clock when emerging from a deselected state,

are placed in a tri-state condition. The outputs are automatically tri-stated during

[A:B]

and when the device is deselected, regardless of the state of OE

is asserted LOW, the pins can behave as outputs. When HIGH,

.

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP

is controlled by BW

[A:B]

correspondingly.

x

Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
tied to V

or left floating selects interleaved burst sequence.

DD

Power supply for the I/O circuitry.

1G are address expansion pins and are not internally connected to the die.

Document #: 001-00207 Rev. *B Page 3 of 12

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CY7C1231H

Functional Overview

The CY7C1231H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t

Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.

Burst Read Accesses

The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of Chip Enable inputs or WE
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

) is 6.5 ns (133-MHz device).

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

1

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:B]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is asserted

is active LOW. After the first

will increment the internal burst counter regardless of

. WE is latched at the

Single Write Accesses

Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus

are ALL asserted active, and (3) the Write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE

input
signal. This allows the external logic to present the data on
DQs and DQP

On the next clock rise the data presented to DQs and DQP
(or a subset for Byte Write operations, see Truth Table for

[A:B]

.

[A:B]

details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.

The data written during the Write operation is controlled by
BW

signals. The CY7C1231H provides Byte Write

[A:B]

capability that is described in the Truth Table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed write mechanism has bee n provided
to simplify the Write operations. Byte Write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera­tions.

Because the CY7C1231H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
before presenting data to the DQs and DQP
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
portion of a write cycle, regardless of the state of OE

.are automatically tri-stated during the data

[A:B]

) can be deasserted HIGH

inputs. Doing

[A:B]

.

Burst Write Accesses

The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW

inputs must be driven in each cycle of the burst write,

[A:B]

in order to write the correct bytes of data.

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t

1, CE2, and CE3, must remain inactive for

after the ZZ input returns LOW.

ZZREC

Document #: 001-00207 Rev. *B Page 4 of 12

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CY7C1231H

Interleaved Burst Sequence

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Deselect Cycle None H X X L L X X X L L->H Tri-St ate
Deselect Cycle None X X H L L X X X L L->H Tri-St ate
Deselect Cycle None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle None X X X L H X X X L L->H Tri-State
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Tri-State
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State
WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State
IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –
Sleep MODE None X X X H X X X X X X Tri-State

Truth Table for Read/Write

Sleep mode standby current ZZ > VDD − 0.2V 40 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
ZZ Active to sleep current This parameter is sampled 2t
ZZ inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5, 6, 7, 8]

Address

Operation

[2, 3]

Used CE1CE2 CE3ZZ ADV/LD WE BWXOE CEN CLK DQ

First

Address

Second

Address

Third

Address

Fourth

Address

A1, A0 A1, A0 A1, A0 A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

CYC

CYC

CYC

ns
ns
ns

Function

Read HXX
Write – No bytes written L H H
Write Byte A – (DQ
Write Byte B – (DQ

and DQPA)LHH

A

and DQPB)LHH

B

Write All Bytes L L L

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx
selects are asserted, see Truth Table for details.

3. Write is defined by BW

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5. The DQs and DQP

= H, inserts wait states.

6. CEN

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

8. OE
OE

is inactive or when the device is deselected, and DQs and DQP

, and WE. See Truth Table for Read/Write.

[A:B]

pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

[A:B]

Document #: 001-00207 Rev. *B Page 5 of 12

WE

= 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write

.

= data when OE is active.

[A:B]

BW

A

BW

= Tri-state when

[A:B]

B

[+] Feedback

CY7C1231H

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
Supply Voltage on V

Relative to GND........–0.5V to +4.6V

DD

Relative to GND......–0.5V to +V

DDQ

DD

DC Voltage Applied to Outputs

in Tri-State...........................................–0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage...................................–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –
Industrial -40°C to +85°C

[9,10]

Ambient

Te m pe r ature (TA)V

DD

5%/+10%

+ 0.5V

DD

V

DDQ

2.5V – 5% to
V

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

DD
DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3V I/O, I

for 2.5V I/O, I

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4

OL

Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V

Input LOW Voltage

for 2.5V I/O 1.7 V

[9]

for 3.3V I/O –0.3 0.8 V

+ 0.3V

DD

for 2.5V I/O –0.3 0.7

I

X

I

OZ

I

DD

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

9. Overshoot: V

10.T

Power-up

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE
Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V
Output Leakage Current GND ≤ VI ≤ V
V

Operating Supply

DD

Current
Automatic CE

Power-down
Current—TTL Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

(AC) < V

IH

: Assumes a linear ramp from 0V to V

+1.5V (Pulse width less than t

DD

V

= Max., I

DD

f = f

MAX

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ VIL, f = f

IN

inputs switching

V

= Max, Device Deselected,

DD

V

≥ VDD – 0.3V or VIN ≤ 0.3V,

IN

f = 0, inputs static

V

= Max, Device Deselected,

DD

V

≥ V

IN

f = f

MAX

V

= Max, Device Deselected,

DD

V

≥ V

IN

f = 0, inputs static

(min.) within 200 ms. During this time VIH < VDD and V

DD

DDQ

SS
DD
SS
DD

, Output Disabled –5 5 µA

DDQ

= 1/t

OUT

CYC

= 0 mA,

7.5-ns cycle, 133 MHz 225 mA

7.5-ns cycle, 133 MHz 90 mA

,

MAX

7.5-ns cycle, 133 MHz 40 mA

7.5-ns cycle, 133 MHz 75 mA

– 0.3V or VIN ≤ 0.3V,

DDQ

, inputs switching

7.5-ns cycle, 133 MHz 45 mA

– 0.3V or VIN ≤ 0.3V,

DD

/2), undershoot: VIL(AC)> –2V (Pulse width less than t

CYC

DDQ

< VDD.

–5 5 µA

–30 µA

–5 µA

/2).

CYC

5 µA

30 µA

V

Document #: 001-00207 Rev. *B Page 6 of 12

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CY7C1231H

Capacitance

[11]

Parameter Description Test Conditions

C

IN

C

CLOCK

C

I/O

Thermal Resistance

Input Capacitance TA = 25°C, f = 1 MHz,
Clock Input Capacitance 5 pF
I/O Capacitance 5 pF

[11]

Parameters Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

T est conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

= 50Ω

0

3.3V

OUTPUT

= 50Ω

R

L

VL= 1.5V

INCLUDING

(a) (b)

5pF

JIG AND

SCOPE

R = 317Ω

R = 351Ω

V

V

DD

DDQ

= 3.3V

= 2.5V

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

100 TQFP

Max. Unit

5pF

100 TQFP

Package Unit

30.32 °C/W

6.85 °C/W

90%

10%

≤ 1 ns

(c)

2.5V I/O Test Load

OUTPUT

= 50Ω

Z

0

V

T

R

= 1.25V

= 50Ω

L

2.5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R =1538Ω

(a) (b)

Note:

11.Tested initially and after any design or process change that may affect these parameters.

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1 ns

(c)

Document #: 001-00207 Rev. *B Page 7 of 12

[+] Feedback

CY7C1231H

Switching Characteristics Over the Operating Range

[12, 13]

-133

Parameter Description

t

POWER

VDD(Typical) to the first Access

[14]

1 ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 7.5 ns
Clock HIGH 2.5 ns
Clock LOW 2.5 ns

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid after CLK Rise 6.5 ns
Data Output Hold after CLK Rise 2.0 ns
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z

[15, 16, 17]

[15, 16, 17]

[15, 16, 17]

[15, 16, 17]

0 ns

3.5 ns

3.5 ns

0 ns

3.5 ns

Set-up Times

t

AS

t

ALS

t

WES

t

CENS

t

DS

t

CES

Address Set-up before CLK Rise 1.5 ns
ADV/LD Set-up before CLK Rise
WE, BW

Set-up before CLK Rise

[A:B]

1.5 ns

1.5
CEN Set-up before CLK Rise 1.5 ns
Data Input Set-up before CLK Rise 1.5 ns
Chip Enable Set-up before CLK Rise 1.5 ns

Hold Times

t

AH

t

ALH

t

WEH

t

CENH

t

DH

t

CEH

Notes:

12.Timing reference level is 1.5V when V

13.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.

14.This part has a voltage regulator internally; t
can be initiated.

, t

15.t

16.At any given voltage and temperature, t

17.This parameter is sampled and not 100% tested.

, t

CHZ

CLZ

OELZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.

Address Hold after CLK Rise 0.5 ns
ADV/LD Hold after CLK Rise
WE, BW

Hold after CLK Rise

[A:B]

CEN Hold after CLK Rise

0.5 ns

0.5 ns

0.5 ns
Data Input Hold after CLK Rise 0.5 ns
Chip Enable Hold after CLK Rise 0.5 ns

, and t

= 3.3V and 1.25V when V

DDQ

is the time that the power needs to be supplied a bove V

POWER

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

is less than t

OEHZ

OELZ

and t

= 2.5V.

DDQ

is less than t

CHZ

minimum initially before a read or write operat ion

DD

to eliminate bus contention between SRAMs when sharing the same

CLZ

UnitMin. Max.

ns

Document #: 001-00207 Rev. *B Page 8 of 12

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Switching Waveforms

123456789

10

C

CENS

CES

[18, 19, 20]

t

CENH

t

CEH

Read/Write Waveforms

CLK

t

CEN

t

CE

ADV/LD

WE

BW

[A:B]

CY7C1231H

t

CYC

t

t

CL

CH

ADDRESS

DQ

A1 A2

t

t

AH

AS

D(A1) D(A2) Q(A4)Q(A3)

t

t

DH

DS

A3

t

CDV

t

CLZ

D(A2+1)

OE

OMMAND

Notes:

For this waveform ZZ is tied LOW.

18.

19.When CE

20.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Inte rleaved). Burst operations are optional.

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

WRITE

D(A1)

WRITE
D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

DON’T CARE UNDEFINED

A4

READ

Q(A4)

t

DOH

t

OEHZ

BURST

READ

Q(A4+1)

A5 A6 A7

t

OEV

t

OELZ

t

CHZ

Q(A4+1)

t

DOH

WRITE
D(A5)

D(A5)

READ

Q(A6)

WRITE

D(A7)

D(A7)Q(A6)

DESELECT

Document #: 001-00207 Rev. *B Page 9 of 12

[+] Feedback

Switching Waveforms (continued)

45678910

123

C

A

NOP, STALL and Deselect Cycles

CLK

CEN

CE

ADV/LD

WE

BW

[A:B]

[18, 19, 21]

CY7C1231H

ADDRESS

DQ

OMMAND

ZZ Mode Timing

CLK

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

A1 A2

D(A1)

[22, 23]

READ
Q(A2)

A3 A4

Q(A2)D(A1) Q(A3)

STALL NOP READ

READ

Q(A3)

WRITE

D(A4)

STALLWRITE

D(A4)

A5

Q(A5)

t

CHZ

Q(A5)

t

DOH

DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

t

ZZ

t

ZZI

I

DDZZ

DESELECT or READ Only

t

RZZI

t

ZZREC

Outputs (Q)

Notes:

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN

22.Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.

23.I/Os are in tri-state when exiting ZZ sleep mode.

Document #: 001-00207 Rev. *B Page 10 of 12

High-Z

DON’T CARE

being used to create a pause. A write is not performed during this cycle.

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Ordering Information

CY7C1231H

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered”.

Speed

(MHz) Ordering Code

Package
Diagram Package Type

Operating

Range

133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

Package Diagram

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

1.40±0.05

SEE DETAIL

0.20 MAX.

20.00±0.10

22.00±0.20

14.00±0.10

100

1

30

31 50

81

80

0.30±0.08

0.65
TYP.

51

12°±1°

(8X)

A

1.60 MAX.

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

0.10

51-85050-*B

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 001-00207 Rev. *B Page 11 of 12

© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch ange without notice. Cypress Semiconductor Corpo ration assu mes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypres s does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-00207

REV. ECN NO. Issue Date

** 347377 See ECN PCI New Data Sheet

*A 428408 See ECN NXR Converted from Preliminary to Final.

*B 459347 See ECN NXR Included 2.5V I/O option

Orig. of
Change Description of Change

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information T able.
Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information table.

DDQ

< V

DD to VDDQ

CY7C1231H

< V

DD

Document #: 001-00207 Rev. *B Page 12 of 12

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