Datasheet CY7C109B-20ZC, CY7C109B-20VI, CY7C109B-20VC, CY7C109B-15ZI, CY7C109B-15ZC Datasheet (Cypress Semiconductor)
...
009B
CY7C109B
CY7C1009B
128K x 8 St atic RAM
Features
put Enable (OE
is accomplished by taking Chip Enable One (CE
• High speed
= 12 ns
—t
AA
• Low active power
—495 mW (max. 12 ns)
• Low CMOS standby power
—55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inpu ts and outputs
• Easy memory exp ansion with CE
Functional Description
[1]
, CE2, and OE options
1
Enable (WE
HIGH. Data on the eight I/O pins (I/O
written into the location specified on the address pins (A
through A16).
Reading from the device is accomplished by taking Chip Enable One (CE
Write Enable (WE
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operat ion (CE
The CY7C109B is ava ilable in sta ndard 400-mil-wide SOJ and
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organi zed as 131, 072 words by 8 bit s. Ea sy mem ory expansion is provided by an active LOW Chip Enable
), an active HIGH Chip Enable (CE2), an active LOW Out-
(CE
1
32-pin TSOP type I pack ages. Th e CY7C10 09B is a vailable in
a 300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
Logic Block Diagram Pin Configurations
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
A
11
3
A
9
A
8
A
13
4
WE
CE
2
A
15
5
V
CC
NC
A
16
6
A
14
A
12
A
7
7
A
6
A
5
A
4
CE
CE
WE
OE
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
A
1
2
ROW DECODER
7
8
512x256x8
ARRAY
COLUMN
DECODER
11
10
12
9
A
A
A
SENSE AMPS
POWER
DOWN
14
15
16
A
A
A
A13A
Selection Guide
7C109B-12
7C1009B-12
Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating Current (mA) 90 80 75 70 60
Maximum CMOS Standby Current (mA) 10 10 10 10 10
Maximum CMOS Standby Current (mA)
Low Power Version
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2 2 2 - -
7C109B-15
7C1009B-15
), and three-stat e driv ers. W rit ing to the devic e
) and Write
2
1
7
6
5
4
3
109B–2
7C109B-35
7C1009B-35
1
32
OE
31
A
10
30
CE
29
I/O
7
28
I/O
6
27
I/O
5
26
I/O
4
25
I/O
3
24
GND
I/O
23
2
22
I/O
1
I/O
21
0
A
20
0
A
19
1
18
A
2
A
17
3
) inputs LOW and Chip Enable Two (CE2) input
through I/O7) is then
0
) and Output Enable (OE) LOW while forcing
1
) and Chip Enable Two (CE2) HIGH. Under
through I/O7) are placed in a
0
LOW, CE2 HIGH, and WE LOW).
1
SOJ
Top View
V
32
CC
31
A
15
30
CE
29
WE
28
A
13
27
A
8
26
A
9
25
A
11
24
OE
23
A
10
22
CE
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C109B-20
7C1009B-20
NC
1
A
16
2
A
3
14
A
4
12
5
A
7
A
6
6
A
7
5
A
8
4
A
9
3
A
10
2
A
1
11
A
12
0
I/O
0
13
I/O
1
14
I/O
2
15
16
TSOP I
Top View
(not to scale)
7C109B-25
7C1009B-25
0
1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05038 Rev. *A Revised September 13, 2002
CY7C109B
CY7C1009B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Stat ic Disc ha rge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[2]
DC Input Voltage
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
[2]
.................................–0.5V to VCC + 0.5V
[2]
....–0.5V to +7.0V
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Ambient
Temperature V
CC
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Ov er the Op erat ing Range
7C109B-12
7C1009B-12
Parameter Description Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
OS
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH Voltage VCC = Min.,
Output LOW V o lt a ge VCC = Min.,
Input HIGH Voltage 2.2 V
Input LOW Voltage
[2]
Input Load Current GND < VI < V
Output Leakage
Current
Output Short
Circuit Current
[3]
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Notes:
2. Minimum voltage is–2.0V for pulse d urations of les s than 20 ns .
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Test Conditions
= –4.0 mA
I
OH
= 8.0 mA
I
OL
CC
GND < VI < VCC,
Output Disabled
VCC = Max.,
= GND
V
OUT
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC, CE1 > V
or CE2 < VIL,
> VIH or
V
IN
< VIL, f = f
V
IN
MAX
Max. VCC,
> VCC – 0.3V,
CE
1
or CE2 < 0.3V,
> VCC – 0.3V,
V
IN
< 0.3V, f = 0
or V
IN
2.4 2.4 V
0.4 0.4 V
CC
+ 0.3
–0.3 0.8 –0.3 0.8 V
–1+1–1+1µA
–5+5–5+5µA
–300 –300 mA
90 80 mA
IH
45 40 mA
10 10 mA
L2 2mA
7C109B-15
7C1009B-15
2.2 V
+ 0.3
CC
V
Document #: 38-05038 Rev. *A Page 2 of 12
Electrical Characteristics Ov er the Op erat ing Range (continued)
CY7C109B
CY7C1009B
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Parameter Descrip tion Test Conditions Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min.,
= –4.0 mA
I
OH
Output LOW Voltage VCC = Min.,
= 8.0 mA
I
OL
Input HIGH Voltage 2.2 V
[3]
[2]
GND < VI < VCC,
Output Disabled
VCC = Max.,
V
OUT
VCC = Max.,
I
OUT
f = f
Max. V
or CE2 < VIL,
> VIH or
V
IN
< VIL, f = f
V
IN
Max. VCC,
CE
1
or CE
> VCC – 0.3V,
V
IN
or V
CC
= GND
= 1/t
, CE1 > V
CC
RC
MAX
= 0 mA,
MAX
> VCC – 0.3V,
< 0.3V,
2
< 0.3V, f = 0
IN
IH
L2——mA
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
2.4 2.4 2.4 V
0.4 0.4 0.4 V
CC
+ 0.3
2.2 V
+ 0.3
CC
2.2 V
CC
+ 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
–1+1–1+1–1+1µA
–5+5–5+5–5+5µA
–300 –300 –300 mA
75 70 60 mA
30 30 25 mA
10 10 10 mA
V
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
Output Capacitance 8 pF
CC
9pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: VENIN EQUIVALENT
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
R1 480Ω
(a)
THÉ
167Ω
R2
255Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
1.73V
5 pF
R1 480Ω
R2
255Ω
(b)
3.0V
GND
≤ 3 ns ≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
Document #: 38-05038 Rev. *A Page 3 of 12
CY7C109B
CY7C1009B
Switching Characteristics
[5]
Over the Oper ating R ange
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Parameter Description Min. Max. Min. Max. Unit
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
6. t
HZOE
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE
and the transition of any of these sig nals can termina te the write. The input data set -up and hold timi ng should be refere nced to the leadi ng edge of the s ignal that terminat es the
write.
9. The minimum write cycle time for Write Cycle No. 3 (WE
Read Cycle Time 12 15 ns
Address to Data Valid 12 15 ns
Data Hold from Address Change 3 3 ns
CE1 LOW to Data Valid, CE2 HIGH to Data
12 15 ns
Valid
OE LOW to Data Valid 6 7 ns
OE LOW to Low Z 0 0 ns
OE HIGH to High Z
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z
CE1 LOW to Power-Up, CE2 HIGH to
[6, 7]
[7]
[6, 7]
67ns
33ns
67ns
00ns
Power-Up
CE1 HIGH to Power-Down, CE2 LOW to
12 15 ns
Power-Down
[8]
Write Cycle Time
[9]
12 15 ns
CE1 LOW to Write End, CE2 HIGH to Write End 10 12 ns
Address Set-Up to Write End 10 12 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 10 12 ns
Data Set-Up to Write End 7 8 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
and 30-pF load capacitance.
, t
HZCE
, and t
are specified with a lo ad cap acit ance of 5 pF as in part (b) o f AC Test Loads. Transi tion i s meas ured ±500 mV from steady-state voltage.
HZWE
[7]
[6, 7]
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
HZOE
LOW, CE2 HIGH, and WE LOW . CE1 and WE must be LOW and C E2 HIGH to initiate a write,
1
33ns
67ns
is less than t
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given devi ce.
LZWE
Document #: 38-05038 Rev. *A Page 4 of 12
CY7C109B
CY7C1009B
Switching Characteristics
[5]
Over the Operating Range (continued)
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time 20 25 35 ns
Address to Data Valid 20 25 35 ns
Data Hold from Address Change 3 5 5 ns
CE1 LOW to Data Valid, CE2 HIGH to Data
20 25 35 ns
Valid
OE LOW to Data Valid 8 10 15 ns
OE LOW to Low Z 0 0 0 ns
OE HIGH to High Z
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z
CE1 LOW to Power-Up, CE2 HIGH to
[6, 7]
[7]
[6, 7]
81015ns
355ns
81015ns
000ns
Power-Up
CE1 HIGH to Power-Down, CE2 LOW to
20 25 35 ns
Power-Down
[8]
Write Cycle Time
[9]
20 25 35 ns
CE1 LOW to Write End, CE2 HIGH to Write End152025ns
Address Set-Up to Write End 15 20 25 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 121520ns
Data Set-Up to Write End 10 15 20 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[7]
[6, 7]
355ns
81015ns
Data Retention Characte ristics Over the Operating Range (Low Power version only)
7C109B-35
7C1009B-35
UnitMin. Max. Min. Max. Min. Min.
Parameter Description Conditions Min. Max Unit
V
DR
I
CCDR
t
CDR
t
R
VCC for Data Retention No input may exceed VCC + 0.5V
Data Retention Current 150 µA
Chip Deselect to Data Retention Time 0 ns
VCC = VDR = 2.0V,
> VCC – 0.3V or CE2 < 0.3V,
CE
1
> VCC – 0.3V or VIN < 0.3V
V
IN
2.0 V
Operation Recovery Time 200 µs
Document #: 38-05038 Rev. *A Page 5 of 12
Data Retention Waveform
V
CC
CE
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
[10, 11]
PREVIOUS DATA VALID DATA VALID
t
OHA
t
CDR
CY7C109B
CY7C1009B
DATA RETENTION MODE
VDR> 2V
t
RC
t
AA
4.5V4.5V
t
R
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
1
CE
2
OE
DATA OUT
V
CC
SUPPLY
CURRENT
Notes:
10. Device is continuously selected. OE
is HIGH for read cycle .
11. WE
12. Address valid prior to or coincident wit h CE
HIGH IMPEDANCE
t
LZCE
t
PU
, CE1 = VIL, CE2 = VIH.
[11, 12]
t
RC
t
ACE
t
DOE
t
LZOE
50%
transition LOW and CE2 transition HIGH.
1
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
I
CC
50%
I
SB
Document #: 38-05038 Rev. *A Page 6 of 12
Switching Waveforms (continued)
CY7C109B
CY7C1009B
Write Cycle No. 1 (CE
or CE2 Controlled)
1
[13, 14]
ADDRESS
CE
1
t
CE
2
SA
t
AW
WE
DATA I/O
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
ADDRESS
t
SCE
CE
1
t
WC
[13, 14]
t
WC
t
PWE
t
SCE
t
SCE
t
SD
DATA VALID
t
HA
t
HD
CE
2
t
SCE
t
AW
t
SA
t
PWE
WE
OE
t
SD
DATA I/O
Notes:
13. Data I/O is high impedance if OE
14. If CE
15. During this period the I/Os are in the output state and input signals should not be applied.
goes HIGH or CE2 goes LOW simult aneo usly w ith WE going HIGH, the outp ut remains in a high-i mpedance stat e.
1
NOTE 15
= VIH.
t
HZOE
DATAINVALID
t
HA
t
HD
Document #: 38-05038 Rev. *A Page 7 of 12
Switching Waveforms (continued)
CY7C109B
CY7C1009B
Write Cycle No. 3 (WE
ADDRESS
CE
1
CE
2
WE
DATA I/O
NOTE 15
Controlled, OE LOW)
t
SA
t
HZWE
[14]
t
WC
t
SCE
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HA
t
LZWE
t
HD
Truth Table
CE
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Ou tpu ts Disabled Active (ICC)
CE
1
OE WE I/O0–I/O
2
7
Mode Power
Document #: 38-05038 Rev. *A Page 8 of 12
Ordering Information
Speed
(ns) Ordering Code
12 CY7C109B-12VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009B-12VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-12ZC Z32 32-Lead TSOP Type I
15 CY7C109B-15VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C109BL-15VC V33 32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZC Z32 32-Lead TSOP Type I
CY7C109BL-15ZC Z32 32-Lead TSOP Type I
CY7C109B-15VI V33 32-Lead (400-Mil) Molded SOJ Industrial
CY7C109BL-15VI V33 32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VI V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZI Z32 32-Lead TSOP Type I
20 CY7C109B-20VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009B-20VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-20VI V33 32-Lead (400-Mil) Molded SOJ Industrial
CY7C109B-20ZC Z32 32-Lead TSOP Type I Commercial
CY7C109B-20ZI Z32 32-Lead TSOP Type I Industrial
25 CY7C109B-25VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009B-25VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-25VI V33 32-Lead (400-Mil) Molded SOJ Industrial
CY7C109B-25ZC Z32 32-Lead TSOP Type I Commercial
CY7C109B-25ZI Z32 32-Lead TSOP Type I Industrial
35 CY7C109B-35VC V33 32-Lead (400-Mil) Molded SOJ Commercial
CY7C1009B-35VC V32 32-Lead (300-Mil) Molded SOJ
CY7C109B-35VI V33 32-Lead (400-Mil) Molded SOJ Industrial
Package
Name Package Type
CY7C109B
CY7C1009B
Operating
Range
Document #: 38-05038 Rev. *A Page 9 of 12
Package Diagrams
CY7C109B
CY7C1009B
32-Lead (300-Mil) Molded SOJ V32
32-Lead (400-Mil) Molded SOJ V33
51-85041-*A
51-85033-*B
Document #: 38-05038 Rev. *A Page 10 of 12
Package Diagrams (continued)
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
CY7C109B
CY7C1009B
All product and company names mentioned in this document may be the trademarks of their respective holders.
51-85056-*D
Document #: 38-05038 Rev. *A Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document History Page
Document Title: CY7C109B, CY7C1009 128K x 8 SRAM
Document Number: 38-05038
REV. ECN NO.
** 106832 09/22/01 SZV Change from Spec number: 38-00971 to 38-05038
*A 116467 09/16/02 CEA Add applications foot note to data sheet, page 1
Issue
Date
Orig. of
Change Description of Change
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *A Page 12 of 12
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