CY7C109
CY7C1009
4
Switching Characteristics
[3, 5]
Over the Operating Range
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009-15
Parameter Description
Min. Max. Min. Max. Min. M ax. Unit
READ CYCLE
t
RC
Read Cycle Time 10 12 15 ns
t
AA
Address to Data Valid 10 12 15 ns
t
OHA
Data Hold from Address Change 3 33ns
t
ACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
10 12 15 ns
t
DOE
OE LOW to Data Va lid 567ns
t
LZOE
OE LOW to Low Z 0 00ns
t
HZOE
OE HIGH to High Z
[6, 7]
567ns
t
LZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[7]
3 33ns
t
HZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[6, 7]
567ns
t
PU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
0 00ns
t
PD
CE1 HIGH to Power-Do wn, CE2 LOW to
Power-Down
10 12 15 ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time 10 12 15 ns
t
SCE
CE1 LOW to Write End, CE2 HIGH to Write End 8 10 12 ns
t
AW
Address Set-Up to Write End 8 10 12 ns
t
HA
Address Hold from Write End 0 00ns
t
SA
Address Set-Up to Write Start 0 00ns
t
PWE
WE Pulse Widt h 8 10 12 ns
t
SD
Data Se t- U p to Wr ite End 6 78ns
t
HD
Data Hold from Write End 0 00ns
t
LZWE
WE HIGH to Low Z
[7]
3 33ns
t
HZWE
WE LOW to High Z
[6, 7]
567ns
Shaded areas contain preliminary information.
Notes:
5. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
I
OL/IOH
and 30-pF load capac itance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified wi th a loa d capac itance of 5 pF as i n part (b) of A C Test Loads. Transition is measured ±500 mV from steady- state v ol tage .
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
LOW , C E2 HIGH, and WE LOW. CE1 and WE must be LOW an d CE2 HIGH to init iate a write ,
and the trans ition of a ny of thes e signal s can te rminate the write . The i npu t data set-u p and hold timing s hould be r efe renced to the l ead ing edge of th e sig nal that terminates
the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.