512K x 8 Static RAM
CY7C1049V33
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 2, 1999
3
Features
• High speed
—t
AA
= 15 ns
• Low active power
—504 mW (max.)
• Low CMOS standby power (Commercial L version)
—1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automat ic power-down when deselected
• TTL-compatibl e inputs and outputs
• Easy memory expansion with CE
and OE fe atures
Functional Description
The CY7C1049V33 is a high-performance CMOS Static RAM
organized as 524,288 words by 8 bits. Easy memory expan-
sion is provided by an active LO W Chip Enable (CE
), an acti ve
LOW Output Enable (OE
), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE
) and
Write Enable ( WE
) inputs LOW . Data on the ei ght I/ O pins ( I/O
0
through I/O7) is then written into the location specified on the
address pins (A
0
through A18).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enab le (OE) LO W whi le f orci ng Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory locati on specified by the address pins wil l appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1049V33 is available in a standard 400-mil-wide
36-pin SOJ package with cent er power and groun d (revol utionary) pinout.
14
15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A13A
12
ACEA
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
1049V33–1
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
1049V33–2
A
9
A
18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A
10
Selectio n Gu ide
1049V33-12 1049V33-15 1049V33-17 1049V33-20 1049V33-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) 150 140 130 120 110
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l 8888 8
Com’l L 0.5 0.5 0.5 0.5 0.5
Shaded areas contain preliminary information.