Cypress Semiconductor CY7C1041V33L-17ZC, CY7C1041V33L-17VC, CY7C1041V33L-15ZC, CY7C1041V33L-15VC, CY7C1041V33L-12ZC Datasheet
...
041V33
CY7C1041V33
256K x 16 Static RAM
Features
written into the location specified on the address pins (A
through A17). If Byte High Enable (BHE) is LOW, then data
• High speed
—t
= 15 ns
AA
• Low active power
—612 mW (max.)
• Low CMOS standby power (Commercial L version)
—1.8 mW (max.)
• 2.0V Data Retention (600 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
Functional Description
The CY7C1041V33 is a hig h-perform ance CMOS Static RAM
organized as 262,144 words by 16 bits .
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O0 through I/O7), is
(BLE
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
then data from the memory location specified by the address
pins will appear on I/O
LOW , then data from me mory will appea r on I/O
the truth tab le at the back of th is data sheet for a c omplete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041V33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pi nout.
through I/O15) is written into the location
8
through A17).
0
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
to I/O7. If Byte High Enable (BHE) is
0
through I/O15) are placed in a
0
Logic Block Diagram Pin Configuration
A
A
A
A
A
CC
SS
A
A
A
A
A
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
SOJ
TSOP II
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
A
A
ROW DECODER
6
7
8
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
I/O0 – I/O
I/O8 – I/O
7
15
CE
I/O
I/O
I/O
I/O
V
COLUMN
DECODER
V
I/O
I/O
11
14
15
12
A13A
AAA
16
17
A
BHE
WE
CE
OE
9
10
A
A
A
I/O
I/O
WE
BLE
1041V33–1
A
17
A
16
A
15
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
SS
V
CC
I/O
I/O
I/O
I/O
NC
A
14
A
13
A
12
A
11
A
10
15
14
13
12
11
10
9
8
to I/O15. See
8
1041V33–2
0
Selection Guide
1041V33-12 1041V33-15 1041V33-17 1041V33-20 1041V33-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) 190 170 160 150 130
Maximum CMOS Standby Current (mA) Com’l/Ind’l 8888 8
Com’l L 0.5 0.5 0.5 0.5 0.5
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05069 Rev. ** Revised September 4, 2001
Maximum Ratings
(Above which the useful life may be impaired. For user guid elines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
Electrical Characteristics Ov er the Op erat ing Range
[1]
....–0.5V to +4.6V
CY7C1041V33
[1]
DC Input Voltage
Current into Outputs (LOW)........................................ 20 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C
................................–0.5V to VCC + 0.5V
Ambient
Temperature
[2]
V
CC
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded areas contain preliminary information.
Notes:
(min.) = –2.0V for pulse durat ions of les s than 20 ns.
1. V
IL
2. T
is the “Instant On” case temp erature.
A
Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
Output LOW Voltage VCC = Min.,
= 8.0 mA
I
OL
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage Current GND < V
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[1]
CC
< VCC, Output Di sabled –1 +1 –1+1µA
OUT
VCC = Max., f = f
Max. V
VIN > VIH or
V
IN
, CE > V
CC
< VIL, f = f
MAX
Max. VCC,
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
< 0.3V, f=0
or V
IN
MAX
IH
= 1/t
RC
Com’l/Ind’l
Com’lL
7C1041-12V33 7C1041V33-15
Min. Max. Min. Max. Unit
2.4 2.4 V
0.4 0.4 V
CC
+ 0.5
2.2 V
CC
+ 0.5
V
–0.5 0.8 –0.5 0.8 V
–1 +1 –1+1µA
190 170 mA
40 40 mA
88mA
0.5 0.5 mA
Document #: 38-05069 Rev. ** Page 2 of 11
CY7C1041V33
Electrical Characteristics Ov er the Op erat ing Range (continued)
Test Conditions 1041V33-17 1041V33-20 1041V33-25
Parameter Description Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[1]
GND < V
Output Disabled
VCC = Max.,
f = f
Max. V
VIN > VIH or
V
IN
Max. VCC,
CE
V
IN
or V
CC
< VCC,
OUT
= 1/t
MAX
< VIL, f = f
, CE > V
CC
RC
MAX
> VCC – 0.3V,
> VCC – 0.3V,
< 0.3V, f=0
IN
–0.5 0.8 –0.5 0.8 –0.5 0 .8 V
–1+1–1+1–1+1µA
–1+1–1+1–1+1µA
IH
Com’l/Ind’l8 8 8mA
Com’l L 0.5 0.5 0.5 mA
+
CC
0.5
2.2 V
CC
0.5
+
2.2 VCC +
0.5
160 150 130 mA
40 40 40 mA
V
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
I/O Capacitance 8 pF
AC Test Loads and Waveforms
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
30 pF
(a)
R1 317
Ω
R2
Ω
351
1041V33–3
THÉ
VENIN EQUIVALENT
OUTPUT
167Ω
(b)
3.3V
1.73V
GND
≤ 3 ns ≤ 3ns
ALL INPUT PULSES
90%
10%
90%
10%
1041V33–4
Document #: 38-05069 Rev. ** Page 3 of 11
CY7C1041V33
Switching Characteristics
[4]
Over the Operating Range
1041V33-12 1041V33-15 1041V33-17
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
5. t
HZOE
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
these signals ca n terminat e the write. The i nput data set-up and h old t iming s hould be referenc ed to the l eading e dge of the s ignal that t erminat es th e write.
8. The minimum write cycle time for Write Cycle No. 3 (WE
Read Cycle Time 12 15 17 ns
Address to Data Valid 12 15 17 ns
Data Hold from Address Change 3 33 ns
CE LOW to Data Valid 12 15 17 ns
OE LOW to Data Valid 678ns
OE LOW to Low Z 0 00 ns
[6]
[5, 6]
[5, 6]
677ns
3 33 ns
677ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 00 ns
CE HIGH to Power-Down 12 15 17 ns
Byte Enable to Data Valid 677ns
Byte Enable to Low Z 0 00 ns
Byte Disable to High Z 678ns
[7, 8]
Write Cycle Time 12 15 17 ns
CE LOW to Write End 10 12 12 ns
Address Set-Up to Write End 10 12 12 ns
Address Hold from Write End 0 00 ns
Address Set-Up to Write Start 0 00 ns
WE Pulse Width 10 12 12 ns
Data Set-Up to Write End 7 89 ns
Data Hold from Write End 0 00 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[5, 6]
3 33 ns
678ns
Byte Enable to End of Write 10 12 12 ns
and 30-pF load capacitance.
, t
HZCE
, and t
are specified wi th a load cap acit ance of 5 pF as in p art (b) of AC Test Loads. Trans ition is me asured ±500 mV from stea dy-st ate vo ltage.
HZWE
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
is less than t
HZOE
LOW, and WE LOW . CE and WE mus t be L OW to i nitiate a wr ite, and the t ran sition of eith er of
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given dev ice.
LZWE
Document #: 38-05069 Rev. ** Page 4 of 11
CY7C1041V33
Switching Characteristics
[4]
Over the Operating Range (continued)
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle T ime 20 25 ns
Address to Data Valid 20 25 ns
Data Hold from Address Change 3 5 ns
CE LOW to Data Valid 20 25 ns
OE LOW to Data Valid 8 10 ns
OE LOW to Low Z 0 0 ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[5, 6]
[6]
[5, 6]
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 20 25 ns
Byte Enable to Data Valid 8 10 ns
Byte Enable to Low Z 0 0 ns
Byte Disable to High Z 8 10 ns
[7,8]
Write Cycle Time 20 25 ns
CE LOW to Write End 13 15 ns
Address Set-Up to Write End 13 15 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 13 15 ns
Data Set-Up to Write End 9 10 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[5, 6]
Byte Enable to End of Write 13 15 ns
1041V33-20 1041V33-25
UnitMin. Max. Min. Max.
810ns
35ns
810ns
35ns
810ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter Description Conditions
V
DR
I
CCDR
[3]
t
CDR
[9]
t
R
Notes:
< 3 ns for the –12 and –15 speeds. tr < 5 ns for the –20 and slower speeds.
9. t
r
10. No input may exceed V
VCC for Data Retention 2.0 V
Data Retention Current VCC = VDR = 2.0V ,
Chip Deselect to Data
Retention Time
CE > VCC – 0.3V,
> VCC – 0.3V or VIN < 0.3V
V
IN
Operation Recovery Time t
+ 0.5V.
CC
Document #: 38-05069 Rev. ** Page 5 of 11
[10]
Min. Max. Unit
330 µA
0 ns
RC
ns
Data Retention Waveform
V
CC
CE
Switching Waveforms
t
CDR
CY7C1041V33
DATA RETENTION MODE
VDR> 2V
3.0V3.0V
t
R
1041V33–5
Read Cycle No. 1
[11, 12]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2(OE Controlled)
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[12, 13]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
OHA
50%
t
RC
t
AA
1041V33-6
t
RC
t
HZOE
t
HZCE
t
DATA VALID
HZBE
t
PD
HIGH
IMPEDANCE
I
ICC
CC
50%
I
ISB
SB
1041V33-7
Notes:
11. Device is continuously selected. OE
12. WE
is HIGH for read cycle .
13. Address valid prior to or coincident with CE
, CE, BHE and/or BHE = VIL.
transition LOW .
Document #: 38-05069 Rev. ** Page 6 of 11
Switching Waveforms (continued)
CY7C1041V33
Write Cycle No. 1 (CE Controlled)
ADDRESS
t
CE
WE
BHE, BLE
DATAI/O
SA
[14, 15]
t
AW
t
WC
t
SCE
t
PWE
t
BW
t
HA
t
SD
t
HD
1041V33-8
Write Cycle No. 2 (BLE or BHE Controlled)
ADDRESS
t
,BLE
BHE
WE
CE
DATAI/O
Notes:
14. Data I/O is high impedance if OE
15. If CE
goes HIGH simultaneousl y with WE going HIGH, the o utput remains in a hig h-imped ance stat e.
SA
or BHE and/or BLE= VIH.
t
WC
t
BW
t
AW
t
PWE
t
SCE
t
SD
t
HA
t
HD
1041V33-9
Document #: 38-05069 Rev. ** Page 7 of 11
Switching Waveforms (continued)
CY7C1041V33
Write Cycle No.3
ADDRESS
CE
WE
BHE
, BLE
DATA I/O
Truth Table
(WE
Controlled, OE LOW)
t
SA
t
AW
t
SCE
t
WC
t
BW
t
HZWE
t
PWE
t
HA
t
SD
t
HD
t
LZWE
1041V33-10
CE OE WE BLE BHE I/O0–I/O
7
I/O8–I/O
15
Mode Power
H X X X X High Z High Z Power Down Standby (ISB)
L L H L L Data Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High Z Read Lower Bits Only Active (ICC)
L L H H L High Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High Z Write Lower Bits Only Active (ICC)
L X L H L High Z Data In Write Upper Bits Only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
Document #: 38-05069 Rev. ** Page 8 of 11
Ordering Information
Speed
(ns) Ordering Code
12 CY7C1041V33 -12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33L-12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33 - 12ZC Z44 44-Pin TSOP II Z44
CY7C1041V33L-12ZC Z44 44-Pin TSOP II Z44
15 CY7C1041V33 -15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33L-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33 - 15ZC Z44 44-Pin TSOP II Z44
CY7C1041V33L-15ZC Z44 44-Pin TSOP II Z44
17 CY7C1 041V33 - 17VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33L-17VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33 - 17ZC Z44 44-Pin TSOP II Z44
CY7C1041V33L-17ZC Z44 44-Pin TSOP II Z44
20 CY7C1 041V33 - 20VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33L-20VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33 - 20ZC Z44 44-Pin TSOP II Z44
CY7C1041V33L-20ZC Z44 44-Pin TSOP II Z44
25 CY7C1 041V33 - 25VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33L-25VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041V33 - 25ZC Z44 44-Pin TSOP II Z44
CY7C1041V33L-25ZC Z44 44-Pin TSOP II Z44
Package
Name Package Type
CY7C1041V33
Operating
Range
Commercial
Document #: 38-05069 Rev. ** Page 9 of 11
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
CY7C1041V33
44-Lead (400-Mil) Mo lded SOJ V3 4
44-Pin TSOP II Z44
51-85082-B
Document #: 38-05069 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
51-85087-A
Document Title: CY7C1041V33 256K x 16 Static RAM
Document Number: 38-05069
REV. ECN NO.
** 107262 09/15/01 SZV Change from Spec number: 38-00645 to 38-05069
Issue
Date
Orig. of
Change Description of Change
CY7C1041V33
Document #: 38-05069 Rev. ** Page 11 of 11
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