Datasheet CY7C1041L-17VC, CY7C1041L-15ZC, CY7C1041L-15VC, CY7C1041L-25ZC, CY7C1041L-25VC Datasheet (Cypress Semiconductor)
...
041
CY7C1041
256K x 16 Static RAM
Features
written into the location specified on the address pins (A
through A17). If Byte High Enable (BHE) is LOW, then data
• High speed
—t
= 15 ns
AA
• Low active power
—1430 mW (max.)
• Low CMOS standby power (L version)
—2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
Functional Description
The CY7C1041 is a high-performance CMOS static RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip Enable (CE
) and Output Enable (OE) LOW while f orcing the Write
Enable (WE
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a com plete description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041 is av ai la ble in a standard 44-pin 400-mil-wide
body width SOJ a nd 44-pin TSOP II pa ckage wit h center p ower and ground (revolutionary) pinout.
through I/O15) is written into the location
8
through A17).
0
) HIGH. If Byte Low Enable (BLE) is LOW, then
to I/O7. If Byte High Enable (BHE) is LOW,
0
through I/O15) are placed in a
0
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
Logic Block Diagram Pin Configuration
A
A
A
A
A
CC
SS
A
A
A
A
A
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
SOJ
TSOP II
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
A
A
ROW DECODER
6
7
8
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
I/O0 – I/O
I/O8 – I/O
7
15
CE
I/O
I/O
I/O
I/O
V
COLUMN
DECODER
V
I/O
I/O
11
14
15
12
A13A
AAA
16
17
A
BHE
WE
CE
OE
9
10
A
A
A
I/O
I/O
WE
BLE
1041–1
to I/O15. See the
8
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
1041–2
0
Selection Guide
7C1041-12 7C1041-15 7C1041-17 7C1041-20 7C1041-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) 280 260 250 230 220
Maximum CMOS Standby Current
(mA)
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05068 Rev. ** Revised September 4, 2001
Com’l 333 3 3
Com’l L 0.5 0.5 0.5 0.5 0.5
Ind’l 666 6 6
Maximum Ratings
(Above which the useful life may be impaired. For user g uid elines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded areas contain preliminary information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of l ess t han 20 ns.
2. T
A
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
[1]
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
is the case temper atu re.
[1]
....–0.5V to +7.0V
CC
GND < V
Output Disabled
OUT
< VCC,
VCC = Max.,
MAX
= 1/t
RC
f = f
Max. VCC, CE > V
VIN > VIH or
< VIL, f = f
V
IN
MAX
Max. VCC,
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
< 0.3V, f = 0
or V
IN
IH
Com’l
Com’lL
Ind’l
CY7C1041
[1]
DC Input Voltage
Current into Outputs (LOW)........................................ 20 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 0.5
Industrial –40°C to +85°C
7C1041-12 7C1041-15 7C1041-17
Min. Max. Min. Max. Min. Max. Unit
–0.5 0.8 –0.5 0.8 –0.5 0.8 V
–1 +1 –1+1–1+1µA
–1 +1 –1+1–1+1µA
................................ –0.5V to VCC + 0.5V
CC
+ 0.5
Ambient
Temperature
2.2 V
CC
+ 0.5
[2]
2.2 V
V
CC
CC
+ 0.5
V
280 260 250 mA
40 40 40 mA
333mA
0.5 0.5 0.5 mA
666mA
Document #: 38-05068 Rev. ** Page 2 of 11
CY7C1041
Electrical Characteristics Ov er the Op erat ing Range (continued)
Test Conditions 7C1041-20 7C1041-25
Parameter Description Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
+ 0.5
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[1]
GND < V
Output Disabled
VCC = Max.,
f = f
Max. V
VIN > VIH or
V
IN
Max. VCC,
CE
V
IN
or V
CC
< VCC,
OUT
= 1/t
MAX
< VIL, f = f
, CE > V
CC
RC
MAX
> VCC – 0.3V,
> VCC – 0.3V,
< 0.3V, f = 0
IN
–0.5 0.8 –0.5 0.8 V
–1+1–1+1µA
–1+1–1+1µA
IH
Com’l33mA
Com’lL 0.5 0.5 mA
Ind’l66mA
CC
230 220 mA
40 40 mA
2.2 VCC + 0.5 V
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
I/O Capacitance 8 pF
CC
8pF
AC Test Loads and Waveforms
Ω
30 pF
R1 481
(a)
THÉ
167Ω
R2
255
OUTPUT
Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to: VENIN EQUIVALENT
OUTPUT
5V
INCLUDING
JIG AND
SCOPE
1.73V
5 pF
R1 481Ω
(b)
1041–3
R2
255
3.0V
GND
Ω
≤ 3 ns ≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
1041–4
Document #: 38-05068 Rev. ** Page 3 of 11
CY7C1041
Switching Characteristics
[4]
Over the Operating Range
7C1041-12 7C1041-15 7C1041-17
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CY CLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
5. t
HZOE
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
these signals can terminat e the write. The input data set -up and hold timing sh ould be referenc ed to the leading edge of the signal that terminat es the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE
Read Cycle Time 12 15 17 ns
Address to Data Valid 12 15 17 ns
Data Hold from Address Change 3 33ns
CE LOW to Data Valid 12 15 17 ns
OE LOW to Data Valid 677ns
OE LOW to Low Z 0 00ns
[6]
[5, 6]
[5, 6]
677ns
3 33ns
677ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 00ns
CE HIGH to Power-Down 12 15 17 ns
Byte Enable to Data Valid 677ns
Byte Enable to Low Z 0 00ns
Byte Disable to High Z 677ns
[7, 8]
Write Cycle Time 12 15 17 ns
CE LOW to Write End 10 12 14 ns
Address Set-Up to Write End 10 12 14 ns
Address Hold from Write End 0 00ns
Address Set-Up to Write Start 0 00ns
WE Pulse Width 10 12 14 ns
Data Set-Up to Write End 7 88ns
Data Hold from Write End 0 00ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[5, 6]
3 33ns
677ns
Byte Enable to End of Write 10 12 12 ns
and 30-pF load capacitance.
, t
HZCE
, and t
are specified with a lo ad cap acitance of 5 pF as in pa rt (b) of AC Test Loads. Tr ansiti on is mea sured ±500 mV from steady-state volt age.
HZWE
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
HZOE
LOW, and WE LOW . CE and WE must be LO W to i nitiate a wr ite, and the t ransi tion of eithe r of
is less than t
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given device.
LZWE
Document #: 38-05068 Rev. ** Page 4 of 11
CY7C1041
Switching Characteristics
[4]
Over the Operating Range (continued)
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle T ime 20 25 ns
Address to Data Valid 20 25 ns
Data Hold from Address Change 3 5 ns
CE LOW to Data Valid 20 25 ns
OE LOW to Data Valid 8 10 ns
OE LOW to Low Z 0 0 ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[5, 6]
[6]
[5, 6]
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 20 25 ns
Byte Enable to Data Valid 8 10 ns
Byte Enable to Low Z 0 0 ns
Byte Disable to High Z 8 10 ns
[7, 8]
Write Cycle Time 20 25 ns
CE LOW to Write End 13 15 ns
Address Set-Up to Write End 13 15 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 13 15 ns
Data Set-Up to Write End 9 10 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[5, 6]
Byte Enable to End of Write 13 15 ns
7C1041-20 7C1041-25
UnitMin. Max. Min. Max.
810ns
35ns
810ns
35ns
810ns
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions
V
DR
I
CCDR
[3]
t
CDR
[9]
t
R
Notes:
9. tr < 100 µs for all speeds .
10. No input may exceed V
VCC for Data Retention 2.0 V
Data Retention Current VCC = VDR = 2.0V,
Com’l L 200 µA
CE > VCC – 0.3V,
> VCC – 0.3V or VIN < 0.3V
V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time See Note 9
+ 0.5V.
CC
Document #: 38-05068 Rev. ** Page 5 of 11
[10]
Min. Max. Unit
µA
µA
Data Retention Waveform
V
CC
CE
Switching Waveforms
t
CDR
CY7C1041
DATA RETENTION MODE
VDR> 2V
3.0V3.0V
t
R
1041–5
Read Cycle No.1
[11, 12]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No.2 (OE Controlled)
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[12, 13]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
OHA
50%
t
RC
t
AA
1041-6
t
RC
t
HZOE
t
HZCE
t
DATA VALID
HZBE
t
PD
HIGH
IMPEDANCE
I
ICC
CC
50%
I
ISB
SB
1041-7
Notes:
11. Device is continuously selected. OE
12. WE
is HIGH for read cycle .
13. Address valid prior to or coincident with CE
, CE, BHE, and/or BHE = VIL.
transition LOW .
Document #: 38-05068 Rev. ** Page 6 of 11
Switching Waveforms (continued)
CY7C1041
Write Cycle No. 1 (CE Controlled)
ADDRESS
t
CE
WE
BHE, BLE
DATAI/O
SA
[14, 15]
t
AW
t
WC
t
SCE
t
PWE
t
BW
t
HA
t
SD
t
HD
1041-8
Write Cycle No. 2 (BLEorBHE Controlled)
ADDRESS
t
,BLE
BHE
WE
CE
DATAI/O
Notes:
14. Data I/O is high impedance if OE
15. If CE
goes HIGH simultaneousl y with WE going HIGH, the o utput remains in a hig h-imped ance stat e.
SA
or BHE and/or BLE= VIH.
t
AW
t
WC
t
BW
t
t
PWE
SCE
t
HA
t
SD
t
HD
1041-9
Document #: 38-05068 Rev. ** Page 7 of 11
Switching Waveforms (continued)
CY7C1041
Write Cycle No.3
ADDRESS
CE
WE
BHE
, BLE
DATA I/O
Truth Table
Controlled, LOW)
(WE
t
SA
t
AW
t
SCE
t
WC
t
BW
t
HZWE
t
PWE
t
HA
t
SD
t
HD
t
LZWE
1041-10
CE OE WE BLE BHE I/O0–I/O
7
I/O8–I/O
15
Mode Power
H X X X X High Z High Z Power Down Standby (ISB)
L L H L L Data Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High Z Read Lower Bits Only Active (ICC)
L L H H L High Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High Z Write Lower Bits Only Active (ICC)
L X L H L High Z Data In Write Upper Bits Only Active (ICC)
L H H X X Hi gh Z High Z Selected, Output s Disabled Active (ICC)
Document #: 38-05068 Rev. ** Page 8 of 11
Ordering Information
Speed
(ns) Ordering Code
15 CY7C1041-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1041L-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041-15ZC Z44 44-Lead TSOP Ty pe II
CY7C1041L-15ZC Z44 44-Lead TSOP T y pe II
17 CY7C1041-17VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041L-17VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041-17ZC Z44 44-Lead TSOP Ty pe II
CY7C1041L-17ZC Z44 44-Lead TSOP T y pe II
20 CY7C1041-20VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041L-20VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041-20ZC Z44 44-Lead TSOP Ty pe II
CY7C1041L-20ZC Z44 44-Lead TSOP T y pe II
25 CY7C1041-25VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041L-25VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1041-25ZC Z44 44-Lead TSOP Ty pe II
CY7C1041L-25ZC Z44 44-Lead TSOP T y pe II
15 CY7C1041-15ZI Z44 44-Lead TSOP Type II Industrial
CY7C1041-15VI V34 44-Lead (400-Mil) Molded SOJ
17 CY7C1041-17ZI V34 44-Lead TSOP Ty pe II
CY7C1041-17VI Z44 44-Lead (400-Mil) Molded SOJ
20 CY7C1041-20ZI Z44 44-Lead TSOP Type II
CY7C1041-20VI Z44 44-Lead (400-Mil) Molded SOJ
25 CY7C1041-25ZI Z44 44-Lead TSOP Type II
CY7C1041-25VI Z44 44-Lead (400-Mil) Molded SOJ
Package
Name Package Type
CY7C1041
Operating
Range
Document #: 38-05068 Rev. ** Page 9 of 11
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
CY7C1041
44-Lead (400-Mil) Mo lded SOJ V3 4
44-Pin TSOP II Z44
51-85082-B
Document #: 38-05068 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
51-85087-A
Document Title: CY7C1041 256K x 16 Static RAM
Document Number: 38-05068
REV. ECN NO.
** 107261 09/10/01 SZV Change from Spec number: 38-00644 to 38-05068
Issue
Date
Orig. of
Change Description of Change
CY7C1041
Document #: 38-05068 Rev. ** Page 11 of 11
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