Datasheet CY7C1021V33-15ZCT, CY7C1021V33-15ZC, CY7C1021V33-15VCT, CY7C1021V33-15VC, CY7C1021V33-15BAC Datasheet (Cypress Semiconductor)
...
64K x 16 Static RAM
CY7C1021V
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 18, 1999
Features
•
3.3V operation (3.0V–3 .6V)
•
High speed
—
t
AA
= 10/12/15 ns
•
CMOS for optimum speed/power
•
Low Active Power (L version )
—
576 mW (max.)
•
Low CMOS Standby Power (L version)
—
1.80 mW (max.)
•
Automat ic power-down when desel ected
•
Independent control of upper and lower bits
•
Available in 44-pin TSOP II and 400-mil SOJ
•
Av ail able in a 48-Ball Mini BGA package
Functional Description
The CY7C1021V is a high-p erf ormance CMOS sta tic RAM o rganized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O1 through I/O
8
), is
written into the location specified on the address pins (A
0
through A15 ). If B yte Hi gh Enabl e (BHE ) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip Enable (CE
) and Output Enable (O E) LOW whil e for cing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/ O
1
to I/O8. If Byte High Enable (BHE) is LOW ,
then data from memory will appear on I/O
9
to I/O
16
.
See the
truth table a t the bac k of this dat a sheet f or a c omplete des cription of read and write modes.
The input/output pins (I/O
1
through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disab led (OE HIGH ), the BHE and BLE
are disabl ed (BHE, BLE HIGH) , or during a write operation (CE
LOW, and WE LOW).
The CY7C1021V is available in 400-mil-wide SOJ, standard
44-pin TSOP Type II, and in 48-ball mini BGA packages.
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
A
4
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
1021V-2
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
64K x 16
RAM Array
I/O
1
– I/O
8
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A10A11A
12A13A14
A
15
512 X 2048
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O9 – I/O
16
CE
WE
BLE
BHE
A
8
1021V-1
Selection Guide
7C1021V-10 7C1021V-12 7C1021V-15
Maximum Access Time (ns) 10 12 15
Maximum Operating Curr ent (mA) Commercial 210 200 190
L 160 150 140
Maximum CMOS Standby Current (mA) Commercial 5 5 5
L 0.500 0.500 0.500
CY7C1021V
2
Pin Configurations
(continued)
Maximum Ratings
(Above which the useful lif e m ay be impaired. For user guidelines, not tested.)
Storage Temperature ................. ................–65°C to +15 0 °C
Ambient Temperature with
Power Applied.............................................–55°C to +1 2 5 °C
Supply Voltage on V
CC
to Relative GND
[1]
....–0.5V to +4.6V
DC V oltage Applied to Outputs
in High Z State
[1]
......................................–0.5V to VCC+0.5V
DC Input Voltage
[1]
...................................–0.5V to VCC+0.5V
Curre n t in to Out p ut s (L OW )................. ... ................... .. 20 mA
Static Discharge Voltage .......... .................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “ins tant on” case temperature.
Mini BGA
(Top View)
BLE
OE
BHE
WE
A
0
A
4
A
1
A
2
CE
V
SS
I/O
1
A
3
I/O
9
I/O
11
I/O
10
A
6
A
5
I/O
3
I/O
2
I/O
5
I/O
12
NC
A
7
I/O
4
V
CC
NC
V
SS
V
CC
I/O
13
NC
NC
I/O
15
I/O
14
I/O
8
A
8
A
15
A
14
I/O6I/O
7
I/O
16
NC
A
12
A
13
NC
NC
A
9
A
10
A
11
123456
A
B
C
D
E
F
G
H
Operating Range
Range Ambient Temperature
[2]
V
CC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
CY7C1021V
3
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditi ons
7C1021V-10
7C1021V-12 7C1021V-15
UnitMin. Max. Min. Max. Min. Max.
V
OH
Outp ut HIGH Volta ge VCC = Min.,
I
OH
= –4.0 mA
2.4
2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 VCC+
0.3V
2.2 VCC+
0.3V
2.2 VCC+
0.3V
V
V
IL
Input LOW Voltage
[1]
−0.3 0.8
–0.3 0.8 –0.3 0. 8 V
I
IX
Input Load Current GND < VI < V
CC
−1+1
–1 +1 –1 +1
µA
I
OZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
−1+1
–1 +1 –1 +1
µA
I
CC
VCC Operating
Supply Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
210 200 190 mA
L 160 150 140 mA
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > V
IH
VIN > VIH or
V
IN
< VIL, f = f
MAX
40 40 40 mA
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V,
V
IN
> VCC – 0.3V,
or V
IN
< 0.3V, f = 0
5 5 5 mA
L 500 500 500
µA
Capacitance
[3]
Parameter Description Te st Condi tions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz 6 pF
C
OUT
Output Capacitance 8 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
1021V-3
1021V-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
<3 ns <3 ns
OUTPUT
R 317
Ω
R 317
Ω
R2
351
Ω
R2
351
Ω
167
Equivalent to:
THÉVENIN
EQUIVALENT
1.73V
30 pF
CY7C1021V
4
Switching Characteristics
[4]
Over the Operating Range
Parameter Description
7C1021V-10
7C1021V-12 7C1021V-15
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read C yc le Time 10 12 15 ns
t
AA
Address to Data Valid 10 12 15 ns
t
OHA
Data Hold from Address Change 3 3 3 ns
t
ACE
CE LOW to Data Valid 10 12 15 ns
t
DOE
OE LOW to Data Valid 4 6 7 ns
t
LZOE
OE LOW to Low Z 0 0 0 ns
t
HZOE
OE HIGH to High Z
[5, 6]
5 6 7 ns
t
LZCE
CE LOW to Low Z
[6]
3 3 3 ns
t
HZCE
CE HIGH to High Z
[5, 6]
5 6 7 ns
t
PU
CE LOW to Power-Up 0 0 0 ns
t
PD
CE HIGH to Power-Do wn 12 12 15 ns
t
DBE
Byte Enable to Data Valid 5 6 7 ns
t
LZBE
Byte Enable to Low Z 0 0 0 ns
t
HZBE
Byte Disable to High Z 5 6 7 ns
WRITE CYCLE
[7]
t
WC
Write Cycle Time 10 12 15 ns
t
SCE
CE LOW to Write End 8 9 10 ns
t
AW
Address Set-Up to Write End 7 8 10 ns
t
HA
Address Hold from Write End 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 ns
t
PWE
WE Pulse Width 8 8 10 ns
t
SD
Data Set-Up to Write End 6 6 8 ns
t
HD
Data Hold from Write End 0 0 0 ns
t
LZWE
WE HIGH to Low Z
[6]
3 3 3 ns
t
HZWE
WE LOW to High Z
[5, 6]
5 6 7 ns
t
BW
Byte Enable to End of Write 8 8 9 ns
Data Rete n ti o n C h ar acteristics
Over the Operating Range (L version only)
Parameter Description Conditions
[10]
Min. Max. Unit
V
DR
VCC for Da ta Rete ntion 2.0 V
I
CCDR
Data Retention Current Com’l VCC = VDR = 2.0V ,
CE
> VCC – 0.3V ,
V
IN
> VCC – 0.3V or VIN < 0.3V
100
µA
t
CDR
[8]
Chip Deselect to Data Retention Time 0 ns
t
R
[9]
Operation Recov ery Time t
RC
ns
Notes:
4. Tes t conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
I
OL/IOH
and 30-pF load capac itance .
5. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capac itance of 5 pF as i n part (b) of AC Test Loads. Transition is measured ±500 mV from steady- state v ol tage .
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE
LOW , WE LO W an d BHE / BLE LOW. CE, WE and BHE / BLE must be LO W t o initi at e a wr ite,
and the transition o f these signa ls can terminate the write. The input data s et-up and hol d timing s hould be refer enced to the leading edge of the signal th at terminates the write.
8. Tested initially and after any design or process changes that may affect these parameters.
9. t
r
< 3 ns for the -1 2 and -15 spe eds. tr < 5 ns for th e -2 0 and slo wer speeds.
10. No input may exceed V
CC
+ 0.5V.
CY7C1021V
5
Data Retention Waveform
1021V–5
3.0V3.0V
t
CDR
V
DR
>
2V
DATA RETENTION MODE
t
R
CE
V
CC
Switchin g W aveforms
Notes:
11. Device is continuously selected. OE
, CE, BHE and/or BHE = VIL.
12. WE
is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
1021V-6
ADDRESS
DATA OUT
[11, 12]
Read Cycle No. 2
(OE
Controlled)
1021V-7
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
t
DBE
t
LZBE
t
HZCE
BHE,BLE
[12, 13]
CURRENT
I
CC
I
SB
CY7C1021V
6
Notes:
14. Data I/O is high impedance if OE
or BHE and/or BLE = VIH.
15. If CE
goes HIGH simu ltaneousl y with WE g oing HI GH, the output remain s in a hi gh-impedanc e state.
Switchin g W aveforms
(continued)
Write Cycle No. 1 (CE
Controlled)
1021V-8
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
[14, 15]
t
WriteCycleNo. 2 (BLEor BHE Controlled)
t
HD
t
SD
t
BW
t
SA
t
HA
t
AW
t
PWE
t
WC
t
SCE
DATA I/O
ADDRESS
BHE
,BLE
WE
CE
1021V-9
CY7C1021V
7
Switchin g W aveforms
(continued)
Write Cycle No. 3
(WE
Controlled,LOW)
1021V-10
t
HD
t
SD
t
SCE
t
HA
t
AW
t
PWE
t
WC
t
BW
DATA I/O
ADDRESS
CE
WE
BHE
,BLE
t
SA
t
LZWE
t
HZWE
Truth Table
CE OE WE BLE BHE I/O1–I/O
8
I/O9–I/O
16
Mode Power
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
L X L L L Data In Data In Write - All bits Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Da ta In Write - Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
CY7C1021V
8
Document #: 38-00544-D
Ordering Information
Speed (ns) Ordering Code
Package
Name
Pac kage Type
Operating
Range
10 CY7C1021V33-10BAC BA48 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021V33-10VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33L-10VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33-10ZC Z44 44-Lead TSOP Type II
CY7C1021V33L-10ZC Z44 44-Lead TSOP Type II
12 CY7C1021V33-12BAC BA48 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021V33-12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33L-12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33-12ZC Z44 44-Lead TSOP Type II
CY7C1021V33L-12ZC Z44 44-Lead TSOP Type II
CY7C1021V33-12BAI BA48 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial
CY7C1021V33-12VI V34 44-Lead (400-Mil) Molded SOJ
15 CY7C1021V33-15BAC BA48 48-Ball Mini Ball Grid Array (7.00 m m x 7.00 mm) Commercial
CY7C1021V33L-15BAC BA48 48-Ball Mini Ball Grid Arra y (7.00 mm x 7.00 mm)
CY7C1021V33-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33L-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021V33-15ZC Z44 44-Lead TSOP Type II
CY7C1021V33L-15VC Z44 44-Lead TSOP Type II
CY7C1021V33-15BAI BA48 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial
CY7C1021V33L-15BAI BA48 48-Ball Mini Ball Grid Arra y (7.00 mm x 7.00 mm)
CY7C1021V33-15VI V34 44-Lead (400-Mil) Molde d SOJ
CY7C1021V33L-15ZI Z44 44- Lead TSOP Type II
CY7C1021V
9
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-C
CY7C1021V
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
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