Datasheet CY7C1021CV33-15VC, CY7C1021CV33-15BAI, CY7C1021CV33-15BAC, CY7C1021CV33-12ZI, CY7C1021CV33-12ZC Datasheet (Cypress Semiconductor)

Features

• Pin- and function-compatible with CY7C1021BV33

• High speed
—t

= 8, 10, 12, and 15 ns

AA

• CMOS for optimum speed/power

• Low active power
—360 mW (max.)

• Data retention at 2.0V

• Automatic power-down when dese lec ted

• Independent control of upper and lower bits

• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA

Functional Description

The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

) and Write Enable (WE) inputs LOW. If Byte Low Enable

(CE

CY7C1021CV33

64K x 16 St atic RAM

) is LOW, then data from I/O pins (I/O1 through I/O8), is

(BLE
written into the location specified on the address pins (A
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A

Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
then data from the memory location specified by the address
pins will appear on I/O
LOW , then data from memory will app ear on I/O
the truth table at the end of this data sheet for a complete
description of Read and Write modes.

The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outp uts are d isabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation

LOW, and WE LOW).

(CE
The CY7C1021CV33 is available in standard 44-pin TSOP

Type II 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.

through I/O16) is written into the location

9

through A15).

0

) and Output Enable (OE) LOW while forcing the

) HIGH. If Byte Low Enable (BLE) is LOW,

to I/O8. If Byte High Enable (BHE) is

1

through I/O16) are placed in a

1

to I/O16. See

9

0

Logic Block Diagram

DATA IN DRIVERS

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

ROW DECODER

64K x 16

RAM Array

512 X 2048

COLUMN DECODER

9

8

A

A

A10A11A

Selection Guide

Maximum Acces s Time
Maximum Operating Curre nt
Maximum CMOS Standby Current

Pin Configuration

SOJ / TSOP II

Top View

44

1

A

4

A

2

3

3

A

2

4

A

1

5

A

0

6

I/O

–I/O

1

8

SENSE AMPS

I/O9–I/O

16

BHE
WE

12

14

15

A13A

A

CE
OE

BLE

I/O
I/O

I/O
I/O

V

V
I/O
I/O
I/O
I/O

WE
A
A

A
A

NC

CE

CC

SS

7

1

8

2

9

3

10

4

11
12
13

5

14

6

15

7

16

8

17
18

15

19

14

20

13

21

12

22

CY7C1021CV33-8 CY7C1021CV33-10 CY7C1021CV33-12 CY7C1021CV33-15 Unit

8 101215ns

95 90 85 80 mA

5555mA

A

5

43

A

6

42

A

7

41

OE

40

BHE

39

BLE

38

I/O

16

37

I/O

15

36

I/O

14

35

I/O

13

34

V

SS

33

V

CC

32

I/O

12

31

I/O

11

30

I/O

10

29

I/O

9

28

NC

27

A

8

26

A

9

25

A

10

A

24

11

23

NC

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05132 Rev. *C Revised October 30, 2002

Pin Configuration

CY7C1021CV33

48-ball FBGA

(Top View)

1

2

4

3

5

6

BLE

I/O

I/O

V

SS

V

CC

I/O

I/O

NC

A

A

A

A

NC

A

A

A

A

NC

2

1

CE

I/O

I/O

I/O

I/O

WE

A

I/O

I/O

2

V

3

CC

V

4

I/O

5

I/O

NC

11

4

6

7

15

13

10

SS

A

B

0

C

1

D

E

F

6

G

7

H

A

OE

BHE

8

I/O

9

I/O

I/O

I/O

14

15

NC

A

0

A

3

A

10

5

NC

11

NC

12

A

14

13

A

12

A

9

8

Document #: 38-05132 Rev. *C Page 2 of 12

CY7C1021CV33

Maximum Ratings

(Above which the us efu l l ife may be impaired. For us er gui de­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High-Z State

[1]

DC Input Voltage

to Relative GND

CC

......................................–0.5V to VCC+0.5V

[1]

...................................–0.5V to VCC+0.5V

[1]

....–0.5V to +4.6V

Electrical Characteristics Over the Operating Range

1021CV33-8 1021CV33-10

2.4 2.4

–0.3 0.8 −0.3 0.8 –0.3 0.8 –0.3 0.8 V

−1 +1 −1+1–1 +1 –1 +1 µA

−1 +1 −1+1–1 +1 –1 +1 µA

IH

Parameter Description

V

V

V

V

I

IX

I

OZ

I

OS

I

CC

I

SB1

OH

OL

IH

IL

Output HIGH
Voltage

Output LOW
Voltage

Input HIGH Voltage 2.0 V

Input LOW

[1]

Voltage
Input Load Current GND < VI < V
Output Leakage

Current
Output Short Circuit

[2]

Current
VCC Operating

Supply Current

Automatic CE
Power-Down
Current —TTL
Inputs

I

SB2

Automatic CE
Power-Down
Current —CMOS
Inputs

Test

Conditions

VCC = Min.,
I

= –4.0 mA

OH

VCC = Min.,

= 8.0 mA

I

OL

CC

GND < VI < VCC,
Output Disabled

VCC = Max.,
V

= GND

OUT

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

= 1/t

RC

Max. VCC, CE > V
VIN > VIH or
VIN < VIL,
f = f

MAX

Max. VCC,

> VCC – 0.3V , VIN >

CE

– 0.3V,

V

CC

or VIN < 0.3V, f = 0

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-up Current......................................................>200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

1021CV33-12 1021CV33-15

2.4 2.4 V

0.4 0.4

2.0 V

CC

+ 0.3

+ 0.3

CC

2.0 V

0.4 0.4 V

2.0 V

CC

+ 0.3

-300 −300 –300 –300 mA

95 90 85 80 mA

15 15 15 15 mA

55

5 5 mA

CC

+ 0.3

CC

UnitMin. Max. Min. Max. Min. Max. Min. Max.

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. V

(min.) = –2.0 V fo r pulse durati ons of l ess tha n 20 ns .

IL

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V

V

Output Capacitance 8 pF

CC

8 pF

Document #: 38-05132 Rev. *C Page 3 of 12

CY7C1021CV33

AC Test Loads and Waveforms

8-ns devices:

OUTPUT

* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT

3.0V

GND

Rise Time: 1 V/ns

Note:

4. AC characteristics (except High-Z) f or all 8-ns parts are tested using the load conditions shown in Figure (a). A ll other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).

Z = 50

ALL INPUT PULSES

90%

10%

[4]

Ω

50Ω

1.5V

30 pF*

10-, 12-, 15-ns devices:

3.3V

OUTPUT

30 pF

(a)

High-Z characteristics:

3.3V

(c)

90%

10%

Fall Time: 1 V/ns

OUTPUT

5 pF

R 317Ω

R2

351Ω

(b)

R 317Ω

R2

351Ω

(d)

Document #: 38-05132 Rev. *C Page 4 of 12

CY7C1021CV33

Switching Characteristics

Over the Operating Range

[5]

1021CV33-8 1021CV33-10

1021CV33-12 1021CV33-15

Parameter Description

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

[8]

t

PU

[8]

t

PD

t

DBE

t

LZBE

t

HZBE

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

t

BW

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6. At any given temperature and voltage condition, t

7. t

HZOE

8. This parameter is guaranteed by design and is not tested.

9. The internal Write time of the memory is defined by the overlap of CE
and the transition of these signals can terminate the Write. The inp ut data set-up and h old timing shou ld be referenced to t he leading edge of t he signal that term inates the Write .

Read Cycle Time 8 10 12 15 ns
Address to Data Valid 8 10 12 15 ns
Data Hold from Address Change 3 3 3 3 ns
CE LOW to Data Valid 8 10 12 15 ns
OE LOW to Data Valid 5 5 6 7 ns
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z

[6]

[6]

[6, 7]

[6, 7]

000 0 ns

456 7 ns

333 3 ns

456 7 ns
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 8 10 12 15 ns
Byte Enable to Data Valid 5 5 6 7 ns
Byte Enable to Low-Z 0 0 0 0 ns
Byte Disable to High-Z 4 5 6 7 ns

[9]

Write Cycle Time 8 10 12 15 ns
CE LOW to Write End 7 8 9 10 ns
Address Set-Up to Write End 7 8 9 10 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-Up to Write Start 0 0 0 0 ns
WE Pulse Width 6 7 8 10 ns
Data Set-Up to Write End 5 5 6 8 ns
Data Hold from Write End 0 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z

[6]
[6, 7]

333 3 ns

456 7 ns
Byte Enable to End of Write 6 7 8 9 ns

, t

HZBE

, t

HZCE

, and t

is less than t

are specified wi th a l oad cap acit ance o f 5 pF as in p art (d) of AC Te st Loa ds. Transition is mea sured ±500 mV from s teady- state volt age.

HZWE

HZCE

, t

LZCE

is less than t

HZOE

LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Wri te,

LZOE

, and t

HZWE

is less than t

for any given device.

LZWE

UnitMin. Max. Min. Max. Min. Max. Min. Max.

Document #: 38-05132 Rev. *C Page 5 of 12

Switching Waveforms

CY7C1021CV33

Read Cycle No. 1

ADDRESS

DATA OUT

Read Cycle No. 2

ADDRESS

CE

OE

BHE, BLE

DATA OUT

V

CC

SUPPLY

CURRENT

[10, 11]

t

RC

t

t

OHA

AA

PREVIOUS DATA VALID DATA VALID

LZCE
PU

[11, 12 ]

t

ACE

t

DOE

t

LZOE

t

DBE

t

LZBE

t

RC

t

HZOE

DATA VALID

Controlled)

(OE

HIGH IMPEDANCE

t
t

50%

t

HZCE

t

HZBE

t

PD

50%

HIGH

IMPEDANCE

I

ICC

CC

I

ISB

SB

Notes:

10. Device is continuously selected. OE
is HIGH for Read cycle.

11. WE

12. Address valid prior to or coincident with CE transition LOW .

, CE, BHE and/or BHE = VIL.

Document #: 38-05132 Rev. *C Page 6 of 12

Switching Waveforms (continued)

CY7C1021CV33

Write Cycle No. 1 (CE Controlled)

ADDRESS

t

CE

WE

BHE, BLE

DATA I/O

SA

[13, 14]

t

AW

t

WC

t

SCE

t

PWE

t

BW

t

HA

t

SD

t

HD

Write Cycle No. 2 (BLEor BHE Controlled)

ADDRESS

t

,BLE

BHE

WE

CE

DATA I/O

Notes:

13. Data I/O is high impedance if OE

14. If CE

goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.

SA

or BHE and/or BLE= VIH.

t

WC

t

BW

t

AW

t

PWE

t

SCE

t

SD

t

HA

t

HD

Document #: 38-05132 Rev. *C Page 7 of 12

Switching Waveforms (continued)

CY7C1021CV33

Write Cycle No. 3

ADDRESS

CE

WE

BHE

,BLE

DATA I/O

Truth Table

Controlled, LOW)

(WE

t

SA

t

AW

t

SCE

t

WC

t

BW

t

HZWE

t

PWE

t

HA

t

SD

t

HD

t

LZWE

CE OE WE BLE BHE I/O1–I/O

8

I/O9–I/O

16

Mode Power

H X X X X High-Z High-Z Power-down Standby (ISB)

L L H L L Data Out Data Out Read – All bits Active (ICC)

L H Data Out High-Z Read – Lower bits only Active (ICC)
H L High-Z Data Out Read – Upper bits only Active (ICC)

L X L L L Data In Data In Write – All bits Active (ICC)

L H Data In High-Z Write – Low er bits only Active (ICC)

H L High-Z Data In Write – Uppe r bits only Active (ICC)
L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC)
L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC)

Document #: 38-05132 Rev. *C Page 8 of 12

CY7C1021CV33

Ordering Information

Speed

(ns) Ordering Code

8 CY7C1021CV33-8VC V34 44-lead (400-Mil) Molded SOJ Commercial

CY7C1021CV33-8ZC Z44 44-lead TSOP Ty pe II
CY7C1021CV33-8BAC BA48A 48-ball FBGA

10 CY7C1021CV33-10VC V34 44-lead (400-Mil) Molded SOJ Commercial

CY7C1021CV33-10VI Industrial
CY7C1021CV33-10ZC Z44 44-lead TSOP Ty pe II Commercial
CY7C1021CV33-10ZI Industrial
CY7C1021CV33-10BAC BA48A 48-ball FBGA Commercial
CY7C1021CV33-10BAI Industrial

12 CY7C1021CV33-12VC V34 44-lead (400-Mil) Molded SOJ Commercial

CY7C1021CV33-12VI Industrial
CY7C1021CV33-12ZC Z44 44-lead TSOP Ty pe II Commercial
CY7C1021CV33-12ZI Industrial
CY7C1021CV33-12BAC BA48A 48-ball FBGA Commercial
CY7C1021CV33-12BAI Industrial

15 CY7C1021CV33-15VC V34 44-lead (400-Mil) Molded SOJ Commercial

CY7C1021CV33-15VI Industrial
CY7C1021CV33-15ZC Z44 44-lead TSOP Ty pe II Commercial
CY7C1021CV33-15ZI Industrial
CY7C1021CV33-15BAC BA48A 48-ball FBGA Commercial
CY7C1021CV33-15BAI Industrial

Package

Name Package Type

Operating

Range

Document #: 38-05132 Rev. *C Page 9 of 12

Package Diagrams

CY7C1021CV33

48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A

51-85096-*E

Document #: 38-05132 Rev. *C Page 10 of 12

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (continued)

CY7C1021CV33

44-Lead (400-Mil) Mo lded SOJ V3 4

51-85082-*B

44-pin TSOP II Z44

51-85087-*A

All products and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05132 Rev. *C Page 11 of 12

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

Document History Page

Document Title: CY7C1021CV33 64K x 16 Static RAM
Document Number: 38-05132

REV. ECN NO.

** 109472 12/06/01 HGK New Data Sheet

*A 115044 05/08/02 HGK Ram7 version C4K x 16 Async.

*B 115808 06/25/02 HGK I

*C 120413 10/31/02 DFP Updated BGA pin E4 to NC.

Issue

Date

Orig. of

Change Description of Change

Remove “Preliminary”

and ICC values changed

SB1

CY7C1021CV33

Document #: 38-05132 Rev. *C Page 12 of 12