Datasheet CY7C1020CV33-15ZI, CY7C1020CV33-15ZC, CY7C1020CV33-12ZI, CY7C1020CV33-12ZC, CY7C1020CV33-10ZI Datasheet (Cypress Semiconductor)

CY7C1020CV33

32K x 16 St atic RAM

Features

• Pin- and function-compatible with CY7C1020V33

• High speed
—t

= 10, 12, 15 ns

AA

• CMOS for optimum speed/power

• Low active power
—360 mW (max.)

• Automatic power-down when dese lec ted

• Independent control of upper and lower bits

• Available in 44-pin TSOP II

Functional Description

The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

) and Write Enable (WE) inputs LOW. If Byte Low Enable

(CE

Logic Block Diagram

DATA IN DRIVERS

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

ROW DECODER

32K × 16

RAM Array

COLUMN DECODER

9

8

A

A

A10A11A

12

A13A

SENSE AMPS

14

(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A

through I/O16) is written into the location

9

through A14).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE

) and Output Enable (OE) LOW while forcing the

) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW , then data from memory will app ear on I/O
the truth table at the back of this data sheet for a complete

to I/O8. If Byte High Enable (BHE) is

1

to I/O16. See

9

description of read and write modes.
The input/output pins (I/O

high-impedance state when the device is deselected (CE

through I/O16) are placed in a

1

HIGH), the outp uts are d isabled (OE HIGH), the BHE and BLE
are disabled (BHE, BL E HIGH), or during a wri te operation (CE
LOW, and WE LOW).

The CY7C1020CV33 is available in standard 44-pin TSOP
Type II packages.

Pin Configuration

TSOP II

Top View

44

I/O

–I/O

1

I/O9–I/O

BHE
WE

CE
OE

BLE

1

NC
A

2

3

3

A

2

4

A

1

5

A

0

6

CE

8

16

I/O
I/O

I/O
I/O

V

V
I/O
I/O
I/O
I/O

WE

A4

A
A

A

NC

CC

SS

7

1

8

2

9

3

10

4

11
12
13

5

14

6

15

7

16

8

17
18
19

14

20

13

21

12

22

A

5

43

A

6

42

A

7

41

OE

40

BHE

39

BLE

38

I/O

16

37

I/O

15

36

I/O

14

35

I/O

13

34

V

SS

33

V

CC

32

I/O

12

31

I/O

11

30

I/O

10

29

I/O

9

28

NC

27

A

8

26

A

9

25

A

10

A

24

11

23

NC

0

Selection Guide

1020CV33-10 1020CV33-12 1020CV33-15 Unit

Maximum Access Time 10 12 15 ns
Maximum Operating Curre nt 90 85 80 mA
Maximum CMOS Standby Current 5 5 5 mA

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05133 Rev. *B Revised August 13, 2002

CY7C1020CV33

Maximum Ratings

(Above which the us efu l l ife may be impaired. For us er gui de­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High-Z State

[1]

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

[1]

....–0.5V to +4.6V

DC Input Voltage

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 3.3V ± 10%

[1]

................................–0.5V to VCC + 0.5V

Industrial –40°C to +85°C3.3V ± 10%

Electrical Characteristics Ov er the Op erat ing Range

1020CV33-10 1020CV33-12 1020CV33-15

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

[2]

I

OS

I

CC

I

SB1

I

SB2

Capacitance

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. V

(min.) = –2.0 V fo r pulse durati ons of l ess tha n 20 ns .

IL

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. Tested initially and after any design or process changes that may affect these parameters.

Output HIGH Voltage VCC = Min.,

I

= –4.0 mA

OH

Output LOW V o lt a ge VCC = Min.,

I

= 8.0 mA

OL

2.4

0.4

Input HIGH Voltage 2.0 VCC +

0.3
Input LOW Voltage
Input Load Current GND < VI < V
Output

Leakage Current
Output Short

Circuit Current
VCC

Operating
Supply Current

Automatic CE
Power-down Current
—TTL Inputs

Automatic CE
Power-down Current
—CMOS Inputs

[3]

[1]

CC

GND < VI < VCC,
Output Disabled

VCC = Max.,

= GND

V

OUT

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

= 1/t

RC

Max. VCC,
CE > V

IH

VIN > VIH or

< VIL,

V

IN

f = f

MAX

Max. VCC,
CE > VCC – 0.3V, VIN >

– 0.3V,

V

CC

< 0.3V, f = 0

or V

IN

−0.3 0.8 –0.3 0.8 –0.3 0.8 V

−1+1–1 +1 –1 +1 µA

−1+1–1 +1 –1 +1 µA

−300

90 85 80 mA

15 15 15 mA

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 8 pF

VCC = 3.3V

2.4 2.4 V

0.4 0.4 V

2.0 VCC +

2.0 VCC +

0.3

–300 –300 mA

5

5 5 mA

8 pF

CC

UnitMin. Max. Min. Max. Min. Max.

V

0.3

Document #: 38-05133 Rev. *B Page 2 of 8

CY7C1020CV33

AC Test Loads and Waveforms

3.3V

OUTPUT

30 pF

R 317Ω

(a)

Switching Characteristics Over the Operating Range

[4]

R2

351Ω

3.0V

GND

Rise Time: 1 V/ns

ALL INPUT PULSES

90%

10%

[4]

(b)

High-Z characteristics:

3.3V

OUTPUT

5 pF

(c)

90%

10%

Fall Time: 1 V/ns

R 317Ω

R2

351Ω

1020CV33-10 1020CV33-12 1020CV33-15

Parameter Description

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

[7]

t

PU

[7]

t

PD

t

DBE

t

LZBE

t

HZBE

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

t

BW

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

5. At any given temperature and voltage condition, t

6. t

7. This parameter is guaranteed by design and is not tested.

8. The internal Write time of the memory is defined by the overlap of CE

, t

HZOE

and the transition o f these signal s can terminate the Write. The input dat a set-up and hold timing shoul d be referenced to the leading edge of the sign al that terminat es the Write.

Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 10 12 15 ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z

[5]

[5]

[5, 6]

[5, 6]

0 0 0 ns

5 6 7 ns

3 3 3 ns

5 6 7 ns
CE LOW to Power-up 0 0 0 ns
CE HIGH to Power-down 10 12 15 ns
Byte Enable to Data Valid 5 6 7 ns
Byte Enable to Low-Z 0 0 0 ns
Byte Disable to High-Z 5 6 7 ns

[8]

Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z

[5]
[5, 6]

3 3 3 ns

5 6 7 ns
Byte Enable to End of Write 7 8 9 ns

HZBE

, t

HZCE

, and t

is less than t

are specified w ith a l oad ca paci tance of 5 pF as in p art ( c) of A C Test Loads. T rans ition i s measur ed ± 500 m V fro m steady- sta te vol tage.

HZWE

HZCE

, t

LZCE

is less than t

HZOE

LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write,

LZOE

, and t

HZWE

is less than t

for any given dev ice.

LZWE

UnitMin. Max. Min. Max. Min. Max.

Document #: 38-05133 Rev. *B Page 3 of 8

Switching Waveforms

CY7C1020CV33

Read Cycle No. 1

ADDRESS

DATA OUT

Read Cycle No. 2

ADDRESS

CE

OE

BHE, BLE

DATA OUT

V

CC

SUPPLY

CURRENT

[9, 10]

t

RC

t

t

OHA

AA

PREVIOUS DATA VALID DATA VALID

LZCE

t

PU

[10, 11]

t

ACE

t

DOE

t

LZOE

t

DBE

t

LZBE

t

RC

t

HZOE

DATA VALID

Controlled)

(OE

HIGH IMPEDANCE

t

50%

t

HZCE

t

HZBE

t

PD

50%

HIGH

IMPEDANCE

I

ICC

CC

I

ISB

SB

Notes:

9. Device is continuously selected. OE
is HIGH for Read cycle.

10. WE

11. Address valid prior to or coincident with CE transition LOW.

, CE, BHE and/or BHE = VIL.

Document #: 38-05133 Rev. *B Page 4 of 8

Switching Waveforms (continued)

CY7C1020CV33

Write Cycle No. 1 (CE Controlled)

[12, 13]

ADDRESS

t

CE

SA

WE

BHE, BLE

DATA I/O

Write Cycle No. 2 (BLE or BHE Controlled)

ADDRESS

t

AW

t

WC

t

WC

t

SCE

t

PWE

t

BW

t

HA

t

SD

t

HD

,BLE

BHE

WE

CE

DATA I/O

Notes:

12. Data I/O is high impedance if OE

13. If CE

goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.

t

SA

or BHE and/or BLE = VIH.

t

AW

t

BW

t

PWE

t

SCE

t

HA

t

SD

t

HD

Document #: 38-05133 Rev. *B Page 5 of 8

Switching Waveforms (continued)

CY7C1020CV33

Write Cycle No. 3

ADDRESS

CE

WE

BHE

,BLE

DATA I/O

(WE

Controlled)

t

SA

t

AW

t

SCE

t

WC

t

BW

t

HZWE

t

PWE

t

HA

t

SD

t

HD

t

LZWE

Truth Table

CE OE WE BLE BHE I/O1–I/O

8

H X X X X High-Z High-Z Power-down Standby (I

L L H L L Data Out Data Out Read—All bits Active (I

L H Data Out High-Z Read—Lower bits only Active (I
H L High-Z Data Out Read—Upper bits only Active (I

L X L L L Data In Data In Write—All bits Active (I

L H Data In High-Z Write—Lower bits only Active (I

H L High-Z Data In Write—Upper bits only Active (I
L H H X X High-Z High-Z Selected, Outputs Disa ble d Active (I
L X X H H High-Z High-Z Selected, Outpu t s Di sa ble d Active (I

I/O9–I/O

16

Mode Power

CC
CC
CC
CC
CC
CC
CC
CC

SB

)
)
)
)
)
)
)
)
)

Ordering Information

Speed

(ns) Ordering Code

10 CY7C1020CV33-10ZC Z44 44-lead TSOP Type II Commercial

CY7C1020CV33-10ZI Z44 44-lead TSOP Type II Industrial

12 CY7C1020CV33-12ZC Z44 44-lead TSOP Type II Commercial

CY7C1020CV33-12ZI Z44 44-lead TSOP Type II Industrial

15 CY7C1020CV33-15ZC Z44 44-lead TSOP Type II Commercial

CY7C1020CV33-15ZI Z44 44-lead TSOP Type II Industrial

Document #: 38-05133 Rev. *B Page 6 of 8

Package

Name Package Type Operating Range

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

CY7C1020CV33

44-Pin TSOP II Z44

All products and company names mentioned in this document may be the trademarks of their respective holders.

51-85087-A

Document #: 38-05133 Rev. *B Page 7 of 8

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

CY7C1020CV33

Document Title: CY7C1020CV33 32K x 16 Static RAM
Document Number: 38-05133

REV. ECN NO.

** 109428 12/16/01 HGK New Data Sheet
*A 115045 05/30/02 HGK I
*B 117615 08/14/02 DFP Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option.

Issue

Date

Orig. of
Change Description of Change

CC

and I

data modified

SB1

Document #: 38-05133 Rev. *B Page 8 of 8