CY7C1020BN
32K x 16 Static RAM
Features
•High speed
—t
= 12, 15 ns
AA
• CMOS for optimum speed/power
• Low active power
— 825 mW (max.)
• Low CMOS standby power (L versio n only)
— 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
) is LOW, then data from I/O pins (I/O1 through I/O8), is
(BLE
written into the location specified on the address pins (A
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
through I/O16) is written into the location
9
through A15).
0
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
to I/O16. See
9
through I/O16) are placed in a
1
0
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
32K x 16
RAM Array
COLUMN DECODER
8
A
A
9
A10A11A
I/O
–I/O
1
8
SENSE AMPS
I/O9–I/O
16
BHE
WE
12
14
A13A
CE
OE
BLE
Pin Configuration
SOJ / TSOP II
Top View
44
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
NC
NC
A
A
A
A
CE
CC
SS
15
14
13
12
1
2
3
3
2
4
1
5
0
6
7
1
8
2
9
3
10
4
11
12
13
5
14
6
15
7
16
8
17
18
19
20
21
22
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
37
I/O
36
I/O
35
I/O
34
V
SS
33
V
CC
32
I/O
31
I/O
30
I/O
29
I/O
28
NC
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
16
15
14
13
12
11
10
9
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06443 Rev. ** Revised February 1, 2006
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CY7C1020BN
Selection Guide
7C1020BN-12 7C1020BN-15
Maximum Access Time (ns) 12 15
Maximum Operating Current (mA) 140 130
Maximum CMOS Standby Current (mA) 3 3
L 0.5 0.5
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied..................................... ........–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
................................. .. ...–0.5V to VCC+0.5V
[1]
................................ ...–0.5V to VCC+0.5V
[1]
....–0.5V to +7.0V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0×C to +70×C 5V ± 10%
Industrial –40×C to +85×C 5V ± 10%
Ambient
[2]
Electrical Characteristics Over the Operating Range
Parameter Description
V
V
V
V
I
IX
I
OZ
I
OS
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 6.0 2.2 6.0 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 –1 +1 µA
Output Short Circuit Current
VCC Operating Supply Current VCC = Max., I
Automatic CE Power-Down
Current—TTL Inputs
I
SB2
Automatic CE Power-Down
Current—CMOS Inputs
Capacitance
[4]
[1]
[3]
VCC = Max., V
Max. VCC, CE > V
VIN > VIH or VIN < VIL, f = f
Max. VCC, CE > VCC – 0.3V,
V
> VCC – 0.3V, or VIN < 0.3V,
IN
f = 0
Conditions
CC
= GND –300 –300 mA
OUT
= 0 mA, f = f
OUT
IH
MAX
MAX
= 1/t
Parameter Description Test Conditions Max. Unit
Test
C
IN
C
OUT
Notes:
(min.) = –2.0V for pulse durations of less than 20 ns.
1. V
IL
is the case temperature.
2. T
A
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
CC
Output Capacitance 8 pF
7C1020BN-12 7C1020BN-15
–0.5 0.8 –0.5 0.8 V
–1 +1 –1 +1 µA
RC
140 130 mA
20 20 mA
3 3 mA
L 0.5 0.5 mA
8 pF
V
CC
UnitMin. Max. Min. Max.
Document #: 001-06443 Rev. ** Page 2 of 8
[+] Feedback
AC Test Loads and Waveforms
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
30 pF
R 481Ω
OUTPUT
R2
255Ω
(a)
5V
5 pF
INCLUDING
JIG AND
SCOPE
167
R 481Ω
(b)
R2
255Ω
Equivalent to:
CY7C1020BN
3.0V
GND
Rise Time: 1 V/ns Fall Time: 1 V/ns
THÉVENIN
EQUIVALENT
OUTPUT
ALL INPUT PULSES
90%
10%
90%
10%
1.73V
30 pF
Switching Characteristics
[5]
Over the Operating Range
7C1020BN-12 7C1020BN-15
Parameter Description
UnitMin. Max. Min. Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing refer ence levels of 1.5 V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
6. At any given temperature and voltage condition, t
7. t
HZOE
voltage.
8. The internal write time of the memory is defined by the overlap of CE
a write, and the transition of these signals can t erminate the write. The input data set-up and ho ld timing sho uld be refer enced to the leading edg e of the signal
that terminates the write.
[8]
and 30-pF load capacitance.
, t
, t
HZBE
Read Cycle Time 12 15 ns
Address to Data Valid 12 15 ns
Data Hold from Address Change 3 3 ns
CE LOW to Data Valid 12 15 ns
OE LOW to Data Valid 6 7 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[6]
[6, 7]
[6]
[6, 7]
0 0 ns
6 7 ns
3 3 ns
6 7 ns
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 12 15 ns
Byte Enable to Data Valid 6 7 ns
Byte Enable to Low Z 0 0 ns
Byte Disable to High Z 6 7 ns
Write Cycle Time 12 15 ns
CE LOW to Write End 9 10 ns
Address Set-Up to Write End 8 10 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 8 10 ns
Data Set-Up to Write End 6 8 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[6, 7]
3 3 ns
6 7 ns
Byte Enable to End of Write 8 9 ns
HZCE
, and t
is less than t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. T ransition is measured ±500 mV from steady-state
HZWE
HZCE
, t
LZCE
LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
is less than t
HZOE
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
Document #: 001-06443 Rev. ** Page 3 of 8
[+] Feedback
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
[9, 10]
PREVIOUS DATA VALID DATA VALID
t
OHA
CY7C1020BN
t
RC
t
AA
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
BHE,BLE
DATA OUT
V
CC
SUPPLY
CURRENT
Notes:
9. Device is continuously selected. OE
10.WE
is HIGH for read cycle.
11.Address valid prior to or coincident with CE
HIGH IMPEDANCE
t
LZCE
t
PU
, CE, BHE and/or BHE = VIL.
[10, 11]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
50%
transition LOW.
t
RC
t
HZOE
t
HZCE
t
DATA VALID
HZBE
t
PD
HIGH
IMPEDANCE
I
ICC
CC
50%
I
ISB
SB
Document #: 001-06443 Rev. ** Page 4 of 8
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Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
ADDRESS
[12, 13]
t
CY7C1020BN
WC
t
CE
SA
WE
BHE,BLE
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
ADDRESS
t
BHE
,BLE
SA
t
SCE
t
AW
t
WC
t
BW
t
PWE
t
BW
t
SD
t
HA
t
HD
WE
CE
DATA I/O
Notes:
12.Data I/O is high impedance if OE
13.If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
or BHE and/or BLE= VIH.
Document #: 001-06443 Rev. ** Page 5 of 8
t
AW
t
PWE
t
SCE
t
HA
t
SD
t
HD
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
t
SA
WE
BHE, BLE
DATA I/O
t
AW
t
SCE
t
WC
t
BW
t
HZWE
CY7C1020BN
t
HA
t
PWE
t
SD
t
HD
t
LZWE
Truth Table
CE OE WE BLE BHE I/O1–I/O
8
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read – All bits Active (ICC)
L H Data Out High Z Read – Lower bits only Active (ICC)
H L High Z Data Out Read – Upper bits only Active (ICC)
L X L L L Data In Data In Write – All bits Active (ICC)
L H Data In High Z Write – Lower bits only Active (ICC)
H L High Z Data In Write – Upper bits only Active (ICC)
L H H X X High Z Hig h Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
I/O9–I/O
16
Mode Power
Ordering Information
Speed
(ns) Ordering Code
12 CY7C1020BN-12VC 51-85082 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020BN-12VXC 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-free) Commercial
CY7C1020BN-12ZC 51-85087 44-pin TSOP Type II Commercial
CY7C1020BN-12ZXC 51-85087 44-pin TSOP Type II (Pb-free) Commercial
15 CY7C1020BN-15ZC 51-85087 44-pin TSOP Type II Commercial
CY7C1020BN-15ZXC 51-85087 44-pin TSOP Type II (Pb-free)
Please contact local sales representative regarding availability of these parts.
Package
Diagram Package Type
Operating
Commercial
Range
Document #: 001-06443 Rev. ** Page 6 of 8
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Package Diagrams
CY7C1020BN
44-Lead (400-Mil) Molded SOJ (51-85082)
44-Pin TSOP II (51-85087)
51-85082-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06443 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch an ge without notice. Cypress Semiconductor Corporation assumes no responsib ility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
51-85087-*A
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Document History Page
Document Title: CY7C1020BN 32K x 16 Static RAM
Document #: 001-06443
REV. ECN NO.
** 426812 See ECN NXR New Data Sheet
Issue
Date
Orig. of
Change Description of Change
CY7C1020BN
Document #: 001-06443 Rev. ** Page 8 of 8
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