• Low CMOS standby power (L version only)
—2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020B is a high-perfo rmance CMOS st atic RAM organized as 32,768 word s by 16 bits. This device has an automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O1 through I/O8), is
(BLE
written into the location specified on the address pins (A
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A
through A15).
0
Reading from the device is accomplished by taking Chip Enable (CE
Enable (WE
) and Output Enable (OE) LOW while f orcing the Write
) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a complete descrip-
to I/O8. If Byte High Enable (BHE) is LOW,
1
to I/O16. See the
9
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O16) are placed in a
1
HIGH), the outputs are disabled (OE HIGH), the BHE an d BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020B is availabl e in stan dard 44-pin TSO P T ype II
and 400-mil -wide SOJ packages.
0
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
32K x 16
RAM Array
COLUMN DECODER
8
A
A
9
A10A11A
–I/O
I/O
1
8
SENSE AMPS
I/O9–I/O
16
BHE
WE
12
14
A13A
CE
OE
BLE
Pin Configuration
SOJ / TSOP II
Top View
44
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
NC
NC
A
A
A
A
CE
CC
SS
15
14
13
12
1
2
3
3
2
4
1
5
0
6
7
1
8
2
9
3
10
4
11
12
13
5
14
6
15
7
16
8
17
18
19
20
21
22
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
37
I/O
36
I/O
35
I/O
34
V
SS
33
V
CC
32
I/O
31
I/O
30
I/O
29
I/O
28
NC
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
16
15
14
13
12
11
10
9
Selection Guide
7C1020B-127C1020B-15
Maximum Access Time (ns)Commercial1215
Maximum Operating Current (mA)Commercial140130
Maximum CMOS Standby Current (mA)Commercial33
L0.50.5
Cypress Semiconductor Corporation•3901 North First Street•San Jose•CA 95134•408-943-2600
Document #: 38-05171 Rev. *A Revised August 20, 2002
CY7C1020B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
......................................–0.5V to VCC+0.5V
[1]
...................................–0.5V to VCC+0.5V
[1]
....–0.5V to +7.0V
Current into Outputs (LOW) ........................................20 mA
Stat ic Disc ha rge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Commercial0°C to +70°C 5V ± 10%
Industrial–40°C to +85°C5V ± 10%
Temperature
Electrical Characteristics Ov er the Op erat ing Range
ParameterDescription
V
V
V
V
I
IX
I
OZ
I
OS
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH VoltageVCC = Min.,
Output LOW VoltageVCC = Min.,
Input HIGH Voltage2.26.02.26.0V
Input LOW Vo lt a ge
[1]
Input Load CurrentGND < VI < V
Output Leakage
Current
Output Short
Circuit Current
[3]
VCC Operating
Supply Current
Automatic CE
Power-Down
Current—TTL Inputs
I
SB2
Automatic CE
Power-Down
Current—CMOS Inputs
Notes:
1. V
(min.) = –2.0V for pulse durations of les s than 20 ns.
IL
2. TA is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Conditions
IOH = –4.0 mA
IOL = 8.0 mA
CC
GND < VI < VCC,
Output Disabled
VCC = Max.,
V
= GND
OUT
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC,
> V
CE
IH
VIN > VIH or
V
< VIL,
IN
f = f
MAX
Max. VCC,
>
CE
– 0.3V, VIN >
V
CC
VCC – 0.3V,
< 0.3V, f = 0
or V
IN
L0.50.5mA
Test
7C1020B-127C1020B-15
2.42.4V
0.40.4V
–0.50.8–0.50.8V
–1+1–1+1µA
–1+1–1+1µA
–300–300mA
140130mA
2020mA
33mA
Ambient
[2]
V
CC
UnitMin.Max.Min.Max.
Document #: 38-05171 Rev. *APage 2 of 10
CY7C1020B
Capacitance
[4]
ParameterDescriptionTest ConditionsMax.Unit
C
IN
C
OUT
Input CapacitanceTA = 25°C, f = 1 MHz,
= 5.0V
V
Output Capacitance8pF
CC
8pF
AC Test Loads and Waveforms
(b)
R 481Ω
1.73V
R2
255Ω
3.0V
GND
Rise Time: 1 V/nsFall Time: 1 V/ns
ALL INPUT PULSES
90%
10%
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
R 481Ω
(a)
THÉVENIN
EQUIVALENT
OUTPUT
R2
255Ω
OUTPUT
5V
5 pF
INCLUDING
JIG AND
SCOPE
167
30 pF
90%
10%
Document #: 38-05171 Rev. *APage 3 of 10
CY7C1020B
Switching Characteristics
[5]
Over the Operating Range
7C1020B-127C1020B-15
ParameterDescription
UnitMin.Max.Min.Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
5. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
6. At any given temperature and voltage condition, t
7. t
HZOE
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW an d BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these s ignals can te rminate the wri te. The input data set-u p and hold ti ming should b e referenced t o the leading edge of the si gnal that terminat es the write.
[8]
and 30-pF load cap aci tance.
, t
HZBE
Read Cycle Time1215ns
Address to Data Valid1215ns
Data Hold from Address Change33ns
CE LOW to Data Valid1215ns
OE LOW to Data Valid67ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[6]
[6]
[6, 7]
[6, 7]
00ns
67ns
33ns
67ns
CE LOW to Power-Up00ns
CE HIGH to Power-Down1215ns
Byte Enable to Data Valid67ns
Byte Enable to Low Z00ns
Byte Disable to High Z67ns
Write Cycle Time1215ns
CE LOW to Write End910ns
Address Set-Up to Write End810ns
Address Hold from Write End00ns
Address Set-Up to Write Start00ns
WE Pulse Width810ns
Data Set-Up to Write End68ns
Data Hold from Write End00ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[6, 7]
33ns
67ns
Byte Enable to End of Write89ns
, t
HZCE
, and t
is less than t
are specified with a load cap acitance of 5 pF as in part (b) of AC Test Loads. Trans ition is measure d ±50 0 mV from stead y-st ate vol tag e.
HZWE
HZCE
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
Document #: 38-05171 Rev. *APage 4 of 10
Switching Waveforms
CY7C1020B
Read Cycle No. 1
ADDRESS
DATA OUT
Read Cycle No. 2
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
[9, 10]
t
RC
t
t
OHA
AA
PREVIOUS DATA VALIDDATA VALID
t
LZCE
t
PU
[10, 11]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
RC
t
HZOE
DATA VALID
Controlled)
(OE
HIGH IMPEDANCE
50%
t
HZCE
t
HZBE
t
PD
50%
HIGH
IMPEDANCE
I
ICC
CC
ISB
I
SB
Notes:
9. Device is continuously selected. OE
is HIGH for read cycle.
10. WE
11. Address valid prior to or coincident with CE transition LOW.
, CE, BHE and/or BHE = VIL.
Document #: 38-05171 Rev. *APage 5 of 10
Switching Waveforms (continued)
CY7C1020B
Write Cycle No. 1 (CE Controlled)
ADDRESS
t
CE
WE
BHE, BLE
DATA I/O
SA
[12, 13]
t
AW
t
WC
t
SCE
t
PWE
t
BW
t
HA
t
SD
t
HD
Write Cycle No. 2 (BLEorBHE Controlled)
ADDRESS
t
,BLE
BHE
WE
CE
DATA I/O
Notes:
12. Data I/O is high impedance if OE
13. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.