Cypress Semiconductor CY7C1020-15ZC, CY7C1020-15VC, CY7C1020-12ZC, CY7C1020-12VC, CY7C1020-10ZC Datasheet
...
020CY7C10
Features
• 5.0V operation (± 10%)
• High speed
—t
= 10 ns
AA
• Low active power
—825 mW (max., 10 ns, “L” version)
• Ver y Low standby pow er
—550 µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020 is a high-performance CMOS static RAM organized as 32,768 word s by 16 bits . Thi s de vi ce has an au tomatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
CY7C1020
32K x 16 Static RAM
(BLE
) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip Enable (CE
) and Output Enable (OE) LOW while f orcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a com plete description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020 is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
through I/O16) is written into the location
9
to I/O8. If Byte High Enable (BHE) is LOW,
1
through A14).
0
through I/O16) are placed in a
1
0
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
32K x 16
RAM Array
SENSE AMPS
– I/O
I/O
1
I/O9 – I/O
8
16
COLUMN DECODER
BHE
9
8
7
A
A
A
A10A11A
12
14
A13A
WE
CE
OE
BLE
1020-1
NC
A
A
A
A
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
NC
13
12
11
CE
CC
SS
10
A
A
A
14
1
2
3
4
5
6
7
8
9
8
7
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
A
0
43
A
1
42
A
2
41
OE
40
BHE
39
BLE
38
I/O
16
37
I/O
15
36
I/O
14
35
I/O
13
34
V
SS
33
V
CC
32
I/O
12
31
I/O
11
30
I/O
10
29
I/O
9
28
NC
27
A
3
26
A
4
25
A
5
A
24
6
23
NC
Selection Guide
7C1020-10 7C1020-12 7C1020-15 7C1020-20
Maximum Access Time (ns) 10 12 15 20
Maximum Operating Current (mA) 180 170 160 160
L150 140 130 130
Maximum CMOS Standby Current (mA) 3 3 3 3
L 0.1 0.1 0.1 0.1
1020-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05058 Rev. ** Revised August 31, 2001
CY7C1020
Maximum Ratings
(Above which the useful life may be im pai red. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
.....................................–0.5V to VCC +0.5V
[1]
.................................–0.5V to VCC +0.5V
[1]
....–0.5V to +7.0V
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Notes:
1. V
IL
2. T
is the case temperature.
A
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 6.0 2.2 6.0 2.2 6.0 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
(min.) = –2.0V for pulse durati ons of l ess than 2 0 ns.
[1]
CC
GND < VI < VCC,
Output Disabled
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC, CE > V
VIN > VIH or
VIN < VIL, f = f
MAX
Max. VCC,
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
or VIN < 0.3V, f = 0
Current into Outputs (LOW)........................................20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0°C to +70°C 4.5V–5.5V
Ambient
7C1020-10
7C1020-12 7C1020-15
–0.5 0.8 –0.5 0.8 –0.5 0.8 V
–1+1–1 +1 –1 +1 µA
–2+2–2 +2 –2 +2 µA
180 170 160 mA
L150140 130
IH
20 20 20 mA
L1010 10
3 3 3 mA
L 100 100 100 µA
[2]
V
CC
UnitMin. Max. Min. Max. Min. Max.
Document #: 38-05058 Rev. ** Page 2 of 10
Electrical Characteristics Ov er the Op erat ing Range (continued)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.2 6.0 V
Input LOW Vo lta ge
Input Load Current GND < VI < V
[1]
CC
Output Leakage Current GND < VI < VCC, Output Disabled –2+2µA
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC, CE > V
VIN > VIH or
< VIL, f = f
V
IN
MAX
Max. VCC,
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
< 0.3V, f = 0
or V
IN
IH
CY7C1020
7C1020-20
UnitMin. Max.
–0.5 0.8 V
–1+1µA
160 mA
L 130
20 mA
L10
3mA
L 100 µA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
Output Capacitance 8 pF
CC
8 pF
AC Test Loads and Wavefor ms
(b)
R 481Ω
1.73V
1020-3
R2
255
3.0V
GND
Ω
<3 ns <3 ns
ALL INPUT PULSES
90%
10%
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to:
30 pF
(a)
THÉVENIN
EQUIVALENT
R 481
Ω
R2
Ω
255
OUTPUT
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
167Ω
30 pF
90%
10%
1020-4
Document #: 38-05058 Rev. ** Page 3 of 10
CY7C1020
Switching Characteristics
[4]
Over the Operating Range
7C1020-10 7C1020-12 7C1020-15 7C1020-20
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
4. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and out put lo ading of the sp ecifi ed
I
OL/IOH
5. t
HZOE
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
and the transition of these signal s can terminate the write . The input data set-up and hold timing sho uld be referenced to the leadin g edge of th e signal that t erminates th e write.
Read Cycle Time 10 12 15 20 ns
Address to Data Valid 10 12 15 20 ns
Data Hold from Address Change 3 3 3 3 ns
CE LOW to D ata Valid 10 12 15 20 ns
OE LOW to Data Valid 5 5 7 9 ns
OE LOW to Low Z 0 0 0 0 ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[5, 6]
[6]
[5, 6]
5 6 7 8 ns
3 3 3 3 ns
5 6 7 8 ns
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 12 12 15 20 ns
Byte enable to Data Valid 5 6 7 9 ns
Byte enable to Low Z 0 0 0 0 ns
Byte disable to High Z 5 6 7 9 ns
[7]
Write Cycle Time 10 12 15 12 ns
CE LOW to Write End 8 9 10 12 ns
Address Set-Up to Write End 7 8 10 12 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-Up to Write Start 0 0 0 0 ns
WE Pulse Width 7 8 10 12 ns
Data Set-Up to Write End 5 6 10 10 ns
Data Hold from Write End 0 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[5, 6]
3 3 3 3 ns
5 6 7 9 ns
Byte enable to end of write 7 8 9 12 ns
and 30-pF load c apacitan ce.
, t
, t
HZBE
HZCE
, and t
are specified w ith a load ca pacit ance of 5 pF as in part (b ) of AC Test Loads. Transition is meas ured ±500 mV from steady-stat e voltage.
HZWE
HZCE
is less than t
, t
LZCE
is less than t
HZOE
LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Document #: 38-05058 Rev. ** Page 4 of 10
Switching Waveforms
CY7C1020
Read Cycle No. 1
[8, 9]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2(OE Controlled)
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[9, 10]
t
ACE
t
t
LZOE
t
DBE
t
LZBE
DOE
50%
t
OHA
t
RC
t
AA
1020-5
t
RC
t
HZOE
t
HZCE
t
DATA VALID
HZBE
t
PD
HIGH
IMPEDANCE
I
ICC
CC
50%
I
ISB
SB
1020-6
Notes:
8. Device is continuously selected. OE
9. WE
is HIGH for read cycle .
10. Address valid prior to or coincident with CE
, CE, BHE and/or BHE = VIL.
transition LOW .
Document #: 38-05058 Rev. ** Page 5 of 10
Switching Waveforms (continued)
CY7C1020
Write Cycle No. 1 (CE Controlled)
ADDRESS
t
CE
WE
BHE, BLE
DATAI/O
SA
[11, 12]
t
AW
t
WC
t
SCE
t
PWE
t
BW
t
HA
t
SD
t
HD
1020-7
Write Cycle No. 2 (BLEorBHE Controlled)
ADDRESS
t
,BLE
BHE
WE
CE
DATAI/O
Notes:
11. Data I/O is high impedance if OE
12. If CE
goes HIGH simultaneousl y with WE going HIGH, the o utput remains in a hig h-imped ance stat e.
SA
or BHE and/or BLE= VIH.
t
WC
t
BW
t
AW
t
PWE
t
SCE
t
SD
t
HA
t
HD
1020-8
Document #: 38-05058 Rev. ** Page 6 of 10
Switching Waveforms (continued)
CY7C1020
Write Cycle No.3
ADDRESS
CE
WE
BHE,BLE
DATA I/O
Controlled, OE LOW)
(WE
t
SA
t
WC
t
SCE
t
AW
t
BW
t
HZWE
t
PWE
t
SD
t
HA
t
HD
t
LZWE
1020-10
Truth Table
CE OE WE BLE BHE I/O1–I/O
8
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
L X L L L Data In Data In Write - All bits Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Data In Write - Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Sele ct ed, Outputs Disable d Active (ICC)
I/O9–I/O
16
Mode Power
Document #: 38-05058 Rev. ** Page 7 of 10
Ordering Information
Speed
(ns) Ordering Code
10 CY7C1020-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020L-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020-10ZC Z44 44-Lead TSOP Type II Commercial
CY7C1020L-10ZC Z44 44-Lead TSOP Type II Commercial
12 CY7C1020-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020L-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020-12ZC Z44 44-Lead TSOP Type II Commercial
CY7C1020L-12ZC Z44 44-Lead TSOP Type II Commercial
15 CY7C1020-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020L-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020-15ZC Z44 44-Lead TSOP Type II Commercial
CY7C1020L-15ZC Z44 44-Lead TSOP Type II Commercial
20 CY7C1020-20VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020L-20VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1020-20ZC Z44 44-Lead TSOP Type II Commercial
CY7C1020L-20ZC Z44 44-Lead TSOP Type II Commercial
Package
Name Package Type
CY7C1020
Operating
Range
Package Diagrams
44-Lead (400-Mil) Mo lded SOJ V3 4
51-85082-B
Document #: 38-05058 Rev. ** Page 8 of 10
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
CY7C1020
44-Pin TSOP II Z44
51-85087-A
Document #: 38-05058 Rev. ** Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
Document Title: CY7C1020 32K x 16 Static RAM
Document Number: 38-05058
REV. ECN NO.
** 107249 09/10/01 SZV Change from Spec number: 38-00542 to 38-05058
Issue
Date
Orig. of
Change Description of Change
CY7C1020
Document #: 38-05058 Rev. ** Page 10 of 10
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