Cypress Semiconductor CY7C1019V33L-15VC, CY7C1019V33L-12VC, CY7C1019V33-15VC, CY7C1019V33-12VC, CY7C1019V33-10VC Datasheet

019V33

CY7C1018V33

CY7C1019V33

128K x 8 Static RAM

Features

• High speed
—t

= 10 ns

AA

• CMOS for optimum speed/power

• Center power/ground pinout

• Automatic power-down when deselected

• Easy memory expansion with CE

and OE options

Functional Description

The CY7C1018V33/CY7C1019V33 is a high-performance
CMOS static RAM organized as 131,072 word s by 8 bits. Easy
memory expansion is prov ided by an activ e LOW Chip Enable

), an active LOW Output Enable (OE), and three-state driv-

(CE
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

) and Write Enab le (WE) inputs LOW . Data o n the eight I/O

(CE

Logic Block Diagram

INPUT BUFFER

A

0

A

1

A

2

A

3

A

CE

WE

OE

4

A

5

A

6

A
A

ROW DECODER

7
8

512 x 256 x 8

ARRAY

COLUMN

DECODER

9

10

A

A11A13A

A

SENSE AMPS

POWER

DOWN

14

15

12

16

A

A

A

pins (I/O
fied on the address pins (A

through I/O7) is then written into the location speci-

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enabl e (OE) LO W while forcing W rite

) HIGH. Under these conditions, the contents of
the memory locatio n spec ified by the add ress pi ns will a ppe ar
on the I/O pins.

The eight input/output pins (I/O
high-impedance state when the device is deselected (CE

through I/O7) are placed in a

0

HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE

LOW, and WE LOW).

The CY7C1018V33 is available in a standard 300-mil-wide
SOJ and CY7C1019V33 is available in a standard
400-mil-wide package. The CY7C1018V33 and
CY7C1019V33 are functionally equivalent in all other re­spects.

Configurations

Pin

SOJ

T op V iew

32
31

30
29

28
27
26
25
24
23

22
21

20
19
18

17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

1019V33–2

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

1019V33–1

I/O
I/O

V

V

I/O
I/O

WE

A
A

A
A

CE

CC

SS

A
A
A

A

1

0
1

2
3

2

4

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

Selection Guide

7C1019V33-10

7C1019V33-12

Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 175 160 145
Maximum Standby Current (mA) 5 5 5

L − 0.5 0.5

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05150 Rev. ** Revised September 18, 2001

7C1018V33-12

7C1018V33-15
7C1019V33-15

CY7C1018V33

CY7C1019V33

Maximum Ratings

(Above which the useful life may be im pai red. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Current into Outputs (LOW)........................................ 20 mA

Static Discharge Voltage...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

[1]

DC Input Voltage

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

[1]

................................–0.5V to VCC + 0.5V

[1]

....–0.5V to +7.0V

Range

Commercial 0°C to +70°C 3.3V ± 10%

Ambient

Temperature

[2]

V

CC

Electrical Characteristics Ov er the Op erat ing Range

7C1019V33-10

Parameter Description Min. Max. Min. Max. Min. Max. Unit

V

V

V

V
I

IX

I

OZ

I

CC

I

SB1

OH

OL

IH

IL

Output HIGH Voltage VCC = Min.,

Output LOW Vo lta ge VCC = Min.,

Input HIGH Voltage 2.2 V

Input LOW Voltage

[1]

Input Load Current GND < VI < V
Output Leakage

Current
VCC Operating

Supply Current

Automatic CE
Power-Down Current
—TTL Inputs

I

SB2

Automatic CE
Power-Down Current
—CMOS Inputs

Test Conditions

= – 4.0 mA

I

OH

= 8.0 mA

I

OL

CC

GND < VI < VCC,
Output Disabled

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

Max. V
VIN > VIH or

< VIL, f = f

V

IN

= 1/t

, CE > V

CC

RC

MAX

Max. VCC,

> VCC – 0.3V,

CE

> VCC – 0.3V,

V

IN

< 0.3V, f = 0

or V

IN

2.4 2.4 2.4 V

+ 0.3

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

–1+1–1+1–1+1µA
–5+5–5+5–5+5µA

IH

L − 0.5 0.5

7C1019V33-12

0.4 0.4 0.4 V

CC

2.2 V
+ 0.3

175 160 145 mA

20 20 20 mA

555mA

7C1018V33-12

7C1018V33-15
7C1019V33-15

CC

2.2 V

CC

+ 0.3

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

(min.) = –2.0V for pulse durations of l ess t han 20 ns .

1. V

IL

2. T

is the “Instant On” case temperat ure.

A

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,

= 5.0V

V

Output Capacitance 8 pF

CC

6pF

Document #: 38-05150 Rev. ** Page 2 of 8

AC Test Loads and Waveforms

CY7C1018V33

CY7C1019V33

Ω

(a)

THÉ

R1 480

167 Ω

OUTPUT

R2

Ω

255

[4]

Ov er the Op eratin g Range

3.3V

OUTPUT

30 pF

INCLUDING
JIG AND
SCOPE

Equivalent to: VENIN EQUIVALENT

OUTPUT

Switching Characteristics

3.3V

INCLUDING
JIG AND
SCOPE

1.73V

5 pF

R1 480 Ω

(b)

R2

Ω

255

1019V33–3

7C1019V33-10

3.0V

GND

≤ 3 ns ≤ 3 ns

7C1018V33-12
7C1019V33-12

ALL INPUT PULSES

90%

10%

7C1018V33-15
7C1019V33-15

90%

10%

1019V33–4

Parameter Description Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

WRITE CY CLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OL/IOH

5. t

HZOE

6. At any given temperature and voltage condition, t

7. The internal write time of the memory is defined by the overlap of CE
signals can termi nate t he writ e. The input dat a set -up and hold ti ming should b e refe renced to the lead ing edge of the signal t hat terminat es the write.

8. The minimum write cycle time for Write Cycle no. 3 (WE

Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 10 12 15 ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low Z 0 0 0 ns

[6]

[5, 6]

[5, 6]

567ns

333ns

567ns

OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 0 0 ns
CE HIGH to Power-Down 10 12 15 ns

[7, 8]

Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-Up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-Up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z

and 30-pF load capacitance.

, t

HZCE

, and t

are specified with a lo ad cap acitance of 5 pF as in pa rt (b) of AC Test Loads. T rans ition is measur ed ±500 mV from s teady- state voltage.

HZWE

[6]
[5, 6]

is less than t

HZCE

controlled, OE LOW) is the sum of t

, t

LZCE

HZOE

LOW and WE LOW . CE and WE must b e LOW to initiat e a write, and th e transition of any of these

333ns

567ns

is less than t

LZOE

, and t

HZWE

is less than t

HZWE

and tSD.

for any given device.

LZWE

Document #: 38-05150 Rev. ** Page 3 of 8