Cypress Semiconductor CY7C1019CV33 Specification Sheet

CY7C1019CV33
128K x 8 Static RAM
Features
• Pin and function compatible with CY7C1019BV33
•High speed —t
= 10 ns
AA
• CMOS for optimum speed/power
• Data retention at 2. 0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE
and OE options
• Available in Pb-free and non Pb-free 48-ball VFBGA, 32-pin TSOP II and 400-mil SOJ package
Functional Description
The CY7C1019CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE active LOW Output Enable (OE
), and tri-state drivers. This
), an
Logic Block Diagram
device has an automatic power-down feature that significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE
) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O specified on the address pins (A
through I/O7) is then written into the location
0
through A16).
0
Reading from the device is accomplished by taking Chip Enable (CE Enable (WE
) and Output Enable (OE) LOW while forcing Write
) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1019CV33 is available in Standard 48-ball FBGA, 32-pin TSOP II and 400-mil-wide SOJ packages
Pin
Configuration
SOJ/TSOP II
Top View
CE WE
OE
A
1
0
A
1
2
A
3
CE
I/O I/O
V V
I/O I/O
WE
A
CC
SS
A A A A
2
4
3
5 6
0
7
1
8 9 10
2 3
11 12
4
13
5
14
6
15 16
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUTBUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A A
ROW DECODER
7 8
128K x 8
DECODER
9
10
A
A
ARRAY
COLUMN
12
A11A13A
SENSE AMPS
POWER
DOWN
14
15
16
A
A
A
32 31
30 29
28 27 26 25 24 23
22 21
20 19
18 17
A A A
A OE
I/O I/O
V V I/O I/O
A A
A A
A
16 15 14
13
7 6
SS CC
5 4
12 11
10 9
8
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-05130 Rev. *F Revised August 3, 2006
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CY7C1019CV33
Pin Configuration
[1]
48-ball VFBGA
(Top View)
NC
I/O
I/O
V
V
I/O
I/O
NC
SS
CC
1
2
OE
NC
0
NC
1
NC
NC
NC
NC
2
NC
3
A
10
A
A
A
NC
A
A
A
4
A
A
A
A
NC
A
A
A
5
6
A
NC
7
6
CE
NC
NC
NC
I/O
WE
A
I/O
I/O
V
CC
V
I/O
4
A
NC
9
5
4
3
11
12
13
SS
A
B
7
C
6
D
E
F
5
G
8
H
3
2
1
0
14
15
16
Selection Guide
-10 -12 -15 Unit
Maximum Access Time 10 12 15 ns Maximum Operating Current 80 75 70 mA Maximum Standby Current 5 5 5 mA
Note:
1. NC pins are not connected on the die.
Document #: 38-05130 Rev. *F Page 2 of 10
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CY7C1019CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide­lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V DC Voltage Applied to Outputs
in High-Z State
[2]
DC Input Voltage
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
[2]
.................................–0.5V to VCC + 0.5V
[2]
....–0.5V to +4.6V
Electrical Characteristics Over the Operating Range
Parameter Description T e st Con dit ions
V
V
V V I I
I
I
I
OH
OL
IH
IL IX OZ
CC
SB1
SB2
Output HIGH Voltage VCC = Min.,
= –4.0 mA
I
OH
Output LOW Voltage VCC = Min.,
I
= 8.0 mA
OL
Input HIGH Volt age 2.0 V Input LOW Voltage Input Leakage Current GND < VI < V Output Leakage
Current VCC Operating
Supply Current
Automatic CE Power-down Current —TTL Inputs
Automatic CE Power-down Current —CMOS Inputs
[2]
GND < VI < VCC, Output Disabled
VCC = Max., I
= 0 mA,
OUT
f = f
MAX
Max. VCC, CE > V VIN > VIH or
< VIL, f = f
V
IN
Max. V
CC
CE
> VCC – 0.3V,
V
> VCC – 0.3V,
IN
< 0.3V, f = 0
or V
IN
= 1/t
,
CC
RC
IH
MAX
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C 3.3V ± 10%
–10 –12 –15
2.4 2.4 2.4 V
0.4 0.4 0.4 V
+ 0.3 2.0 V
CC
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
–1 +1 –1 +1 –1 +1 µA –1 +1 –1 +1 –1 +1 µA
80 75 70 mA
15 15 15 mA
555mA
Ambient
Temperature V
+ 0.3 2.0 VCC + 0.3 V
CC
CC
UnitMin. Max. Min. Max. Min. Max.
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
(min.) = –2.0V for pulse durations of less than 20 ns.
2. V
IL
3. Tested initially and after any design or process ch anges that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz, Output Capacitance 8 pF
Document #: 38-05130 Rev. *F Page 3 of 10
V
= 5.0V
CC
8pF
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CY7C1019CV33
AC Test Loads and Waveforms
3.3V
OUTPUT
30 pF
R 317
R2
351
(a)
Switching Characteristics
[4]
3.0V
GND
Rise Time: 1 V/ns
90%
10%
Over the Operating Range
ALL INPUT PULSES
(b)
[5]
-10 -12
High-Z characteristics:
90%
10%
Fall Time: 1 V/ns
3.3V
R 317
OUTPUT
5 pF
(c)
-15
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[8]
t
PU
[8]
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
4. AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z charact eristics are t ested for all spe eds using the test load shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3. 0V.
6. t
HZOE
7. At any given temperature and voltage condition, t
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE any of these signals can terminate the write. Th e input data set-up and hold timing shou ld be referenced to the leading edge of the signal that terminates the write.
10.The minimum write cycle time for Write Cycle no. 3 (WE
Read Cycle Time 10 12 15 ns Address to Data Valid 10 12 15 ns Data Hold from Address Change 3 3 3 ns CE LOW to Data Valid OE LOW to Data V alid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[6, 7]
[7]
[6, 7]
CE LOW to Power-Up CE HIGH to Power-Down
[9, 10]
00
333 ns
00
10 12
56
0 ns
567 ns
567 ns
0 ns
10 12
Write Cycle Time 10 12 15 ns CE LOW to Write End 8 9 10 ns Address Set-Up to Write End 8 9 10 ns Address Hold from Write End 0 0 0 ns Address Set-Up to Write Start 0 0 0 ns WE Pulse Width
78
10 ns Data Set-Up to Write End 5 6 8 ns Data Hold from Write End 0 0 0 ns WE HIGH to Low Z WE LOW to High Z
, t
, and t
HZCE
HZWE
[7] [6, 7]
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loa ds. Transition is measure d ±500 mV from steady-state vol tage.
is less than t
HZCE
controlled, OE LOW) is the sum of t
333 ns
567 ns
, t
LZCE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
is less than t
HZOE
LZOE
HZWE
, and t
and tSD.
HZWE
is less than t
for any given device.
LZWE
15 ns
7 ns
15 ns
R2 351
UnitMin. Max. Min. Max. Min. Max.
Document #: 38-05130 Rev. *F Page 4 of 10
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Switching Waveforms
Read Cycle No. 1
[11, 12]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
t
OHA
CY7C1019CV33
t
RC
t
AA
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
LZCE
t
PU
CURRENT
Write Cycle No. 1 (CE Controlled)
ADDRESS
[12, 13]
t
ACE
t
LZOE
[14, 15]
t
DOE
50%
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
t
WC
CE
WE
DATA I/O
Notes:
11.Device is continuously selected. OE is HIGH for read cycle.
12.WE
13.Address valid prior to or coincident with CE
14.Data I/O is high impedance if OE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15.If CE
, CE = VIL.
transition LOW.
= VIH.
Document #: 38-05130 Rev. *F Page 5 of 10
t
SCE
t
SA
t
t
SCE
SD
t
HA
t
HD
t
AW
t
PWE
DATA VALID
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Switching Waveforms (continued)
Write Cycle No. 2 (WE
ADDRESS
CE
Controlled, OE HIGH During Write)
t
SCE
[14, 15]
t
WC
CY7C1019CV33
t
SA
WE
OE
DATA I/O
NOTE 16
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
t
SA
WE
[15]
t
AW
t
PWE
t
SD
t
HA
t
HD
DATAINVALID
t
WC
t
SCE
t
AW
t
PWE
t
HA
NOTE
DATA I/O
16
t
HZWE
Truth Table
CE OE WE
H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC)
Note:
16.During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05130 Rev. *F Page 6 of 10
I/O0–I/O
t
SD
t
HD
DATA VALID
t
LZWE
7
Mode Power
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CY7C1019CV33
Ordering Information
Speed
(ns) Ordering Code
10 CY7C1019CV33-10VC 51-85033 32-pin 400-Mil Molded SOJ Commercial
CY7C1019CV33-10ZXC 51-85095 32-pin TSOP II (Pb-Free) CY7C1019CV33-10ZXI 32-pin TSOP II (Pb-Free) Industrial
12 CY7C1019CV33-12VC 51-85033 32-pin 400-Mil Molded SOJ Commercial
CY7C1019CV33-12ZC 51-85095 32-pin TSOP II CY7C1019CV33-12ZXC 32-pin TSOP II (Pb-Free) CY7C1019CV33-12VI 51-85033 32-pin 400-Mil Molded SOJ Industrial CY7C1019CV33-12BVXI 51-85 150 48-ball VFBGA (Pb-Free)
15 CY7C1019CV33-15VC 51-85033 32-pin 400-Mil Molded SOJ Commercial
CY7C1019CV33-15VXC 51-85033 32-pin 400-Mil Molded SOJ (Pb-Free) CY7C1019CV33-15ZXC 51-85095 32-pin TSOP II (Pb-Free) CY7C1019CV33-15ZXI 51-85095 32-pin TSOP II (Pb-Free) Industrial
Package Diagrams
Package Diagram Package Type
32-pin (400-Mil) Molded SOJ (51-85033)
Operating
Range
Document #: 38-05130 Rev. *F Page 7 of 10
51-85033-*B
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Package Diagrams (continued)
CY7C1019CV33
32-pin TSOP II (51-85095)
51-85095-**
Document #: 38-05130 Rev. *F Page 8 of 10
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Package Diagrams (continued)
TOP VIEW
A1 CORNER
465231
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
CY7C1019CV33
BOTTOM VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
1
65
234
A
B
C
0.25 C
8.00±0.10
A
0.55 MAX.
D
E
F
G
H
A
B
6.00±0.10
0.21±0.05
0.10 C
8.00±0.10
5.25
0.75
0.15(4X)
2.625
1.875
0.75
3.75
B
6.00±0.10
51-85150-*D
SEATING PLANE
C
0.26 MAX.
1.00 MAX
All product and company names mentioned in this document are the trademarks of their respective holders.
A
B
C
D
E
F
G
H
Document #: 38-05130 Rev. *F Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch ange without notice. Cypress Semiconductor Corporation assumes no resp onsib ility for the u se of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY7C1019CV33 128K x 8 Static RAM Document Number: 38-05130
REV. ECN NO.
** 109245 12/16/01 HGK New Data Sheet *A 113431 04/10/02 NSL AC Test Loads split based on speed *B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved I *C 119796 10/11/02 DFP Updated standby current from 5 nA to 5 mA *D 123030 12/17/02 DFP Updated Truth Table to reflect single Chip Enable option *E 419983 See ECN NXR Added 48-ball VFBGA Package
*F 493543 See ECN NXR Removed 8 ns speed bin from Product offering
Issue
Date
Orig. of
Change Description of Change
Added lead-free parts in Ordering Information Table Replaced Package Name column with Package Diagram in the Ordering Information Table
Added note #1 on page #2 Changed the description of I Input Leakage Current in DC Electrical Characteristics table Removed I Updated Ordering Information
parameter from DC Electrical Characteristics table
OS
from Input Load Current to
IX
CY7C1019CV33
limits
CC
Document #: 38-05130 Rev. *F Page 10 of 10
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