CY7C1019BN
128K x 8 Static RAM
Features
•High speed
—t
= 12, 15 ns
AA
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE
and OE options
• Functionally equivalent to CY7C1019
Logic Block Diagram
Functional Description
The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE
), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
through I/O7) is then written into the location
0
through A16).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE
) and Output Enable (OE) LOW while forcing Write
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1019BN is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ packages.
Pin Configurations
/ TSOPII
SOJ
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
16
15
14
13
7
6
SS
CC
5
4
12
11
10
9
8
CE
WE
OE
A
1
0
A
1
2
A
3
2
A
4
I/O
I/O
V
V
I/O
I/O
WE
CE
CC
SS
A
A
A
A
3
5
6
0
7
1
8
9
10
2
3
11
12
4
13
5
14
6
15
16
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
A
ROW DECODER
7
8
512 x 256 x 8
ARRAY
COLUMN
DECODER
9
10
A
A11A13A
A
SENSE AMPS
POWER
DOWN
14
15
12
16
A
A
A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06425 Rev. ** Revised February 1, 2006
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CY7C1019BN
Selection Guide
7C1019BN-12 7C1019BN-15 Unit
Maximum Access Time 12 15 ns
Maximum Operating Current 140 130 mA
Maximum Standby Current 10 10 mA
L 1 1 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
[1]
.................................–0.5V to VCC + 0.5V
[1]
....–0.5V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage VCC = Min., IOH = – 4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 VCC+ 0.3 2.2 VCC+ 0.3 V
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[3]
[1]
GND < VI < V
GND < VI < VCC,
Output Disabled
VCC = Max., I
f = f
MAX
= 1/t
Max. VCC, CE > V
VIN > VIH or
V
< VIL, f = f
IN
Max. VCC,
CE
> VCC – 0.3V,
> VCC – 0.3V,
V
IN
or V
< 0.3V, f = 0
IN
CC
OUT
RC
MAX
= 0 mA,
IH
L20 20
L1 1
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
-12 -15
–0.3 0.8 –0.3 0.8 V
–1 +1 –1 +1 µA
–5 +5 –5 +5 µA
140 130 mA
40 40 mA
10 10 mA
Ambient
[2]
V
CC
UnitMin. Max. Min. Max.
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
(min.) = –2.0V for pulse durations of less than 20 ns.
1. V
IL
is the “Instant On” case temperature.
2. T
A
3. Tested initially and after any design or process ch anges that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 8 pF
Document #: 001-06425 Rev. ** Page 2 of 8
V
CC
= 5.0V
6pF
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AC Test Loads and Waveforms
CY7C1019BN
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
R1 480Ω
R2
255Ω
(a)
167Ω
Switching Characteristics
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
1.73V
[4]
Over the Operating Range
R1 480Ω
(b)
R2
255Ω
3.0V
GND
≤ 3 ns ≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
-12 -15
Parameter Description
UnitMin. Max. Min. Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
5. t
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
8. The minimum write cycle time for Write Cycle no. 3 (WE
and 30-pF load capacitance.
I
OL/IOH
, t
HZOE
HZCE
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that t erminates the write.
Read Cycle Time 12 15 ns
Address to Data Valid 12 15 ns
Data Hold from Address Change 3 3 ns
LOW to Data Valid 12 15 ns
CE
LOW to Data Valid 6 7 ns
OE
LOW to Low Z 0 0 ns
OE
[6]
[5, 6]
[5, 6]
67ns
33 ns
67ns
[7, 8]
HIGH to High Z
OE
LOW to Low Z
CE
HIGH to High Z
CE
LOW to Power-Up 0 0 ns
CE
HIGH to Power-Down 12 15 ns
CE
Write Cycle Time 12 15 ns
LOW to Write End 9 10 ns
CE
Address Set-Up to Write End 8 10 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
Pulse Width 8 10 ns
WE
Data Set-Up to Write End 6 8 ns
Data Hold from Write End 0 0 ns
[6]
[5, 6]
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
HZOE
LOW and WE LOW. CE and WE must be LOW to in itiate a write , and th e tran sitio n of any
33 ns
67ns
is less than t
LZOE
HZWE
, and t
and tSD.
is less than t
HZWE
for any given device.
LZWE
, and t
HIGH to Low Z
WE
LOW to High Z
WE
are specified with a load capacitance of 5 pF as in part (b) of A C Test Loads. T ransition is measured ±500 mV from steady-state volt age.
HZWE
Document #: 001-06425 Rev. ** Page 3 of 8
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CY7C1019BN
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions Min. Max. Unit
V
DR
I
CCDR
[3]
t
CDR
t
R
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
VCC for Data Retention No input may exceed VCC + 0.5V
V
= VDR = 2.0V,
Data Retention Current 300 µA
Chip Deselect to Data Retention Time 0 ns
CC
> VCC – 0.3V,
CE
V
> VCC – 0.3V or VIN < 0.3V
IN
2.0 V
Operation Recovery Time 200 µs
DATA RETENTION MODE
V
CC
t
CDR
CE
[9, 10]
VDR> 2V
3.0V3.0V
t
R
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[10, 1 1]
t
ACE
t
LZOE
t
DOE
50%
t
OHA
t
RC
t
AA
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
50%
HIGH
IMPEDANCE
ICC
ISB
Notes:
9. Device is continuously selected. OE
is HIGH for read cycle.
10.WE
11.Address valid prior to or coincident with CE
, CE = VIL.
transition LOW.
Document #: 001-06425 Rev. ** Page 4 of 8
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Switching Waveforms (continued)
Write Cycle No. 1 (CE
ADDRESS
CE
WE
DATA I/O
Controlled)
[12, 13]
CY7C1019BN
t
WC
t
SCE
t
SA
t
t
AW
t
PWE
SCE
t
SD
DATA VALID
t
HA
t
HD
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[12, 13]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
t
PWE
WE
OE
t
SD
DATA I/O
Notes:
12.Data I/O is high impedance if OE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
13.If CE
14.During this period the I/Os are in the output state and input signals should not be applied.
NOTE 14
= VIH.
t
HZOE
DATAINVALID
t
HA
t
HD
Document #: 001-06425 Rev. ** Page 5 of 8
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Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
Controlled, OE LOW)
[13]
t
SCE
t
CY7C1019BN
WC
t
HA
t
LZWE
t
HD
WE
DATA I/O
NOTE
14
t
AW
t
SA
t
HZWE
t
PWE
t
SD
DATA VALID
Truth Table
CE OE WE I/O0–I/O
7
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Mode Power
Ordering Information
Speed
(ns) Ordering Code
12 CY7C1019BN-12VC 51-85033 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019BN-12ZC 51-85095 32-Lead TSOP Type II
CY7C1019BN-12ZXC 51-85095 32-Lead TSOP Type II (Pb-free)
15 CY7C1019BN-15VC 51-85033 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019BN-15ZXC 51-85095 32-Lead TSOP Type II (Pb-free)
Please contact local sales representative regarding availability of these par ts
Package
Diagram P ackage Type
Operating
Range
Document #: 001-06425 Rev. ** Page 6 of 8
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Package Diagrams
CY7C1019BN
32-pin (400-mil) Molded SOJ (51-85033)
32-pin TSOP II (51-85095)
51-85033-A
51-85033-*B
All product or company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06425 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch ange without notice. Cypress Semiconductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
51-85095-**
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Document History Page
Document Title: CY7C1019BN 128K x 8 Static RAM
Document Number: 001-06425
REV. ECN NO. Issue Date
** 423847 See ECN NXR New Data Sheet
Orig. of
Change Description of Change
CY7C1019BN
Document #: 001-06425 Rev. ** Page 8 of 8
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