Cypress Semiconductor CY7C1019B-15ZI, CY7C1019B-15ZC, CY7C1019B-15VC, CY7C1019B-12ZC, CY7C1019B-12VC Datasheet

C1019V33

CY7C1019B/

CY7C10191B

128K x 8 St atic RAM

Features

• High speed
—t

= 10, 12, 15 ns

AA

• CMOS for optimum speed/power

• Center power/ground pinout

• Automatic power-down when deselected

• Easy memory expansion with CE

and OE options

• Functionally equivalent to CY7C1019

Functional Description

The CY7C1019B/1019 1B is a h igh -pe rform an ce CMO S static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is pro vided by an a ctive LOW Chip En able (CE
active LOW Output Enable (OE

), and three-state d rivers . This

), an

device has an automa tic powe r-down feature th at signifi cantly
reduces power consumption when deselected.

ogic Block Diagram

INPUT BUFFER

A

0

A

1

A

2

A

3

A

CE

WE

OE

4

A

5

A

6

A
A

ROW DECODER

7
8

512 x 256 x 8

ARRAY

COLUMN

DECODER

9

10

A

A

A11A13A

SENSE AMPS

POWER

DOWN

14

15

12

16

A

A

A

Writing to the device is accomplished by taking Chip Enable

) and Write Enable (WE) inputs LOW . Dat a on the eight I/O

(CE
pins (I/O
fied on the address pins (A

through I/O7) is then written into the location speci-

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enabl e (OE) LO W while forcing W rite

) HIGH. Under these conditions, the contents of
the memory locatio n spec ified by the add ress pi ns will a ppe ar
on the I/O pins.

The eight input/output pins (I/O
high-impedance state when the device is deselected (CE

through I/O7) are placed in a

0

HIGH), the outputs are disabled (OE HIGH), or during a wr ite
operation (CE

LOW, and WE LOW).

The CY7C1019B/10191B is available in standard 32-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10191B when ordering parts
with 10 ns t

.

t

AA

, and CY7C1019B when ordering 12 and 15 ns

AA

Configurations

Pin

/ TSOPII

SOJ

Top View

32
31

30
29

28
27
26
25
24
23
22
21
20
19
18

17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

A

1

0

A

1

2

A

3

2

A

4

I/O
I/O

V
V

I/O
I/O

WE

CE

CC

SS

A
A
A

A

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

0

1

2

3

4

5

6

7

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05026 Rev. *A Revised August 13, 2002

CY7C1019B/

CY7C10191B

Selection Guide

7C10191B-10 7C1019B-12 7C1019B-15

Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 150 140 130
Maximum Standby Current (mA) 10 10 10

L − 1 1

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Current into Outputs (LOW) ........................................20 mA

Stat ic Disc ha rge Voltage..... ...... ..... ...... ......................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

[1]

DC Input Voltage

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

[1]

.................................–0.5V to VCC + 0.5V

[1]

....–0.5V to +7.0V

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

Ambient

Temperature

[2]

V

CC

Electrical Characteristics Ov er the Op erat ing Range

7C10191B-10 7C1019B-12 7C1019B-15

Parameter Description Min. Max. Min. Max. Min. Max. Unit

V

V

V

V
I

IX

I

OZ

I

CC

I

SB1

OH

OL

IH

IL

Output HIGH Voltage VCC = Min.,

Output LOW Voltage VCC = Min.,

Input HIGH Voltage 2.2 V

Input LOW Voltage

[1]

Input Load Current GND < VI < V
Output Leakage

Current
VCC Operating

Supply Current

Automatic CE
Power-Down Current
—TTL Inputs

I

SB2

Automatic CE
Power-Down Current
—CMOS Inputs

Capacitance

[3]

Test Conditions

= – 4.0 mA

I

OH

= 8.0 mA

I

OL

CC

GND < VI < VCC,
Output Disabled

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

= 1/t

RC

Max. VCC, CE > V
VIN > VIH or

< VIL, f = f

V

IN

MAX

Max. VCC,

> VCC – 0.3V,

CE
VIN > VCC – 0.3V,

< 0.3V, f = 0

or V

IN

2.4 2.4 2.4 V

0.4 0.4 0.4 V

CC

+ 0.3

2.2 V

CC

+ 0.3

2.2 V
+ 0.3

CC

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

–1+1–1+1–1+1µA
–5+5–5+5–5+5µA

150 140 130 mA

IH

40 40 40 mA

L20 20 20

10 10 10 mA

L − 11

V

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. V

(min.) = –2.0V for pulse d uratio ns of less t han 20 ns.

IL

is the “Instant On” case t emperat ure.

2. T

A

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 8 pF

VCC = 5.0V

6pF

Document #: 38-05026 Rev. *A Page 2 of 9

AC Test Loads and Waveforms

CY7C1019B/

CY7C10191B

5V

OUTPUT

30 pF

INCLUDING
JIG AND
SCOPE

Equivalent to: VENIN EQUIVALENT

OUTPUT

Switching Characteristics

R1 480Ω

(a)

THÉ

167Ω

OUTPUT

R2

255Ω

[4]

Over the Operating Range

5V

INCLUDING
JIG AND
SCOPE

1.73V

5 pF

R1 480Ω

(b)

R2

255Ω

3.0V

GND

≤ 3 ns ≤ 3 ns

ALL INPUT PULSES

90%

10%

90%

10%

7C10191B-10 7C1019B-12 7C1019B-15

Parameter Description Min.Max.Min.Max.Min.Max.Unit

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OL/IOH

5. t

HZOE

6. At any give n temperature and voltag e condition, t

7. The internal write time of the me mory i s defi ned by the ov erla p of CE
signals can termin ate th e write. The inpu t dat a s et-up a nd hold t imin g should be ref erenced to the leadi ng edge of the s ignal t h at termi nates t he write .

8. The minimum write cycle time for Write Cycle no. 3 (WE

Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 1 5 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 101215ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low Z 0 0 0 ns

[6]

[5, 6]

[5, 6]

567ns

333ns

567ns

OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 0 0 ns
CE HIGH to Power-Down 10 12 15 ns

[7, 8]

Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-Up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-Up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z

and 30-pF load cap acit ance.

, t

HZCE

, and t

are specified w ith a l oad c apac itanc e of 5 pF as i n pa rt (b) of AC Test Loa ds. T r ansiti on is mea sured ±500 mV from steady- sta te vol tage.

HZWE

[6]
[5, 6]

333ns

is less than t

HZCE

controlled, OE LOW) is the sum of t

, t

LZCE

HZOE

LOW and WE LOW. CE an d WE mus t be LOW to initiate a write , and the transiti on of any of these

567ns

is less than t

LZOE

, and t

HZWE

is less than t

HZWE

and tSD.

for any given device.

LZWE

Document #: 38-05026 Rev. *A Page 3 of 9

CY7C1019B/

CY7C10191B

Data Retention Characte ristics Over the Operating Range (L Version Only)

Parameter Description Conditions Min. Max. Unit

V

DR

I

CCDR

t

CDR

t

R

[3]

VCC for Data Retention No input may exceed VCC + 0.5V
Data Retention Current 300 µA
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time 200 µs

Data Retention Waveform

V

CC

CE

t

CDR

= VDR = 2.0V,

V

CC

> VCC – 0.3V,

CE

> VCC – 0.3V or VIN < 0.3V

V

IN

DATA RETENTION MODE

VDR> 2V

2.0 V

3.0V3.0V
t

R

Switching Waveforms

Read Cycle No. 1

ADDRESS

DATA OUT

Read Cycle No. 2 (OE Controlled)

ADDRESS

CE

OE

DATA OUT

V

CC

SUPPLY

CURRENT

[9, 10]

PREVIOUS DATA VALID DATA VALID

HIGH IMPEDAN CE

t

LZCE

t

PU

[10, 11]

t

ACE

t

LZOE

t

OHA

t

DOE

50%

t

RC

t

AA

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

50%

HIGH

IMPEDANCE

ICC
ISB

Notes:

9. Device is continuously selected. OE
is HIGH for read cycle .

10. WE

11. Address valid prior to or coincident with CE transiti on LOW.

, CE = VIL.

Document #: 38-05026 Rev. *A Page 4 of 9

Switching Waveforms (continued)

CY7C1019B/

CY7C10191B

Write Cycle No. 1 (CE

Controlled)

[12, 13]

ADDRESS

CE

t

SA

t

AW

WE

DATA I/O

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)

ADDRESS

t

WC

[12, 13]

t

WC

t

PWE

t

SCE

t

SCE

t

SD

DATA VALID

t

HA

t

HD

t

SCE

CE

t

AW

t

SA

t

PWE

WE

OE

t

SD

DATA I/O

Notes:

12. Data I/O is high impedance if OE

13. If CE

14. During this period the I/Os are in the output state and input signals should not be applied.

goes HIGH simultaneous ly with WE going HIGH , the outpu t remains in a high-im pedance state .

NOTE 14

= VIH.

t

HZOE

DATAINVALID

t

HA

t

HD

Document #: 38-05026 Rev. *A Page 5 of 9

Switching Waveforms (continued)

CY7C1019B/

CY7C10191B

Write Cycle No. 3 (WE

ADDRESS

CE

WE

DATA I/O

NOTE

Controlled, OE LOW)

t

SA

14

t

HZWE

[13]

t

AW

t

SCE

t

WC

t

PWE

t

SD

DATA VALID

t

HA

t

LZWE

t

HD

Truth Table

CE OE WE I/O0–I/O

7

H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)

L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)

Mode Power

Ordering Information

Speed

(ns) Ordering Code

10 CY7C10191B-10VC V33 32-Lead 400-Mil Molded SOJ Commercial
12 CY7C1019B-12VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019B-12ZC ZS32 32-Lead TSOP Type II Commercial

15 CY7C1019B-15VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019B-15VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019B-15ZC ZS32 32-Lead TSOP Type II Commercial
CY7C1019B-15ZI ZS32 32-Lead TSOP Type II Industrial

Document #: 38-05026 Rev. *A Page 6 of 9

Package

Name Pa cka ge Type

Operating

Range

Package Diagrams

CY7C1019B/

CY7C10191B

32-Lead (400-Mil) Molded SOJ V33

51-85033-*B

51-85033-A

Document #: 38-05026 Rev. *A Page 7 of 9

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (continued)

CY7C1019B/

CY7C10191B

32-Lead

TSOP II ZS32

All product or company names mentioned in this document may be the trademarks of their respective holders.

51-85095

Document #: 38-05026 Rev. *A Page 8 of 9

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

CY7C1019B/

CY7C10191B

Document Title: CY7C1019B/CY7C10191B 128K x 8 Static RAM
Document Number: 38-05026

REV. ECN NO. Issue Date Orig. of Change Description of Change

** 109949 09/25/01 SZV Change from Spec number: 38-01115 to 38-05026

*A 1161 70 08/14/02 HGK 1. SOJ (400-mil) pa ckage outline replacing inc orrect

SOJ package

2. Pin for pin compatible with CY7C1019

3. Industrial package s added to Ordering Informat ion

Document #: 38-05026 Rev. *A Page 9 of 9