Datasheet CY7C1019L-15VC, CY7C1019L-12VC, CY7C1019L-10VC, CY7C1019-15VC, CY7C1019-12VC Datasheet (Cypress Semiconductor)
...
019
PRELIMINARY
Features
• High speed
—t
= 10 ns
AA
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE
Functional Description
The CY7C1019 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy me mory exp ansio n
is provided by an active L OW chip enable (CE
output ena ble (OE
), and three-state drivers. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Logic Block Diagram
and OE options
), an active LOW
CY7C1019
128K x 8 Static RAM
Writing to the device is accomplished by taking chip enable
) and write enable (WE ) inputs LOW. Data on the eigh t I/O
(CE
pins (I/O
fied on the address pins (A
Reading from the device is accomplished by taking chip enable (CE
enable (WE
the memory locatio n spec ified by the add ress pi ns will a ppe ar
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
The CY7C1019 is available in standard 400-mil-wide SOJs.
through I/O7) is then written into the location speci-
0
through A16).
0
) and output enable (OE) LOW while forcing write
) HIGH. Under these conditions, the contents of
through I/O7) are placed in a
0
LOW, and WE LOW).
Configuration
Pin
SOJ
Top V iew
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1019–2
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
16
15
14
13
7
6
SS
CC
5
4
12
11
10
9
8
CE
WE
OE
A
1
0
A
1
2
A
3
2
A
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1019–1
0
1
2
3
4
5
6
7
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
A
ROW DECODER
7
8
512 x 256 x 8
ARRAY
COLUMN
DECODER
9
10
A
A
A11A13A
SENSE AMPS
POWER
DOWN
14
15
12
16
A
A
A
I/O
I/O
V
I/O
I/O
V
WE
CE
3
5
6
0
7
1
8
CC
9
SS
10
2
3
11
12
A
4
13
A
5
14
A
6
15
A
16
7
Selection Guide
7C1019–10 7C1019–12 7C1019–15
Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 240 220 200
L 210 190 175
Maximum Standby Current (mA) 10 10 10
L 1 1 1
Shaded areas contain advance information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05055 Rev. ** Revised August 31, 2001
PRELIMINARY
Maximum Ratings
(Above which the useful life may be im pai red. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
[1]
................................–0.5V to VCC + 0.5V
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded areas contain advance information.
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Vo lta ge
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[1]
....–0.5V to +7.0V
[1]
GND < VI < VCC,
Output Disabled
VCC = Max.
I
= 0 mA,
OUT
f = f
MAX
Max. VCC, CE > V
VIN > VIH or
< VIL, f = f
V
IN
Max. V
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
or V
IN
T est Conditions
CC
,
= 1/t
RC
IH
MAX
,
CC
< 0.3V, f=0
CY7C1019
Current into Outputs (LOW)........................................20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0°C to +70°C 5V ± 10%
7C1019-10 7C1019-12 7C1019-15
Min. Max. Min. Max. Min. Max. Unit
Ambient
CC
+ 0.3
2.2 V
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
–1 +1 –1+1–1+1µA
–5 +5 –5+5–5+5µA
240 220 200 mA
L
210 190 175
40 40 40 mA
L
20 20 20
10 10 10 mA
L
111
CC
+ 0.3
[2]
2.2 V
+ 0.3
V
CC
CC
V
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
(min.) = –2.0V for pulse durations of l ess t han 20 ns .
1. V
IL
2. T
is the “instant on” case tempera ture.
A
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
Output Capacitance 8 pF
CC
6pF
Document #: 38-05055 Rev. ** Page 2 of 8
PRELIMINARY
CY7C1019
AC Test Loads and Waveforms
Ω
(a)
THÉ
R1 480
167Ω
OUTPUT
R2
Ω
255
[4]
Ov er the Op eratin g Range
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: VENIN EQUIVALENT
OUTPUT
Switching Characteristics
5V
INCLUDING
JIG AND
SCOPE
1.73V
5 pF
R1 480Ω
(b)
1019–3
R2
255
3.0V
GND
Ω
≤ 3ns ≤ 3 ns
7C1019-10 7C1019-12 7C1019-15
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CY CLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Shaded areas contain advance information.
Note:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
5. t
HZOE
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
signals can termi nate t he writ e. The input dat a set -up and hold ti ming should b e refe renced to the lead ing edge of the signal t hat terminat es the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE
Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 33ns
CE LOW to Data Valid 10 12 15 ns
OE LOW to Data Valid 567ns
OE LOW to Low Z 0 00ns
[6]
[5, 6]
[5, 6]
567ns
3 33ns
567ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 00ns
CE HIGH to Power-Down 10 12 15 ns
[7,8]
Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 910ns
Address Set-Up to Write End 7 810ns
Address Hold from Write End 0 00ns
Address Set-Up to Write Start 0 00ns
WE Pulse Width 7 810ns
Data Set-Up to Write End 5 68ns
Data Hold from Write End 0 00ns
WE HIGH to Low Z
WE LOW to High Z
and 30-pF load capacitance.
, t
HZCE
, and t
are specified with a lo ad cap acitance of 5 pF as in pa rt (b) of AC Test Loads. T rans ition i s measur ed ±500 mV from s teady- state voltage.
HZWE
[6]
[5, 6]
3 33ns
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
is less than t
HZOE
LOW and WE LOW . CE and WE must b e LOW to initiat e a write, and th e transition of any of these
567ns
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
ALL INPUT PULSES
90%
10%
for any given device.
LZWE
90%
10%
1019–4
Document #: 38-05055 Rev. ** Page 3 of 8
PRELIMINARY
CY7C1019
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions Min. Max Unit
V
DR
I
CCDR
t
CDR
t
R
VCC for Data Retention No input may exceed VCC + 0.5V
= VDR = 3.0V,
V
Data Retention Current 300 µA
[3]
Chip Deselect to Data Retention Time 0 ns
CC
> VCC – 0.3V,
CE
1
> V
V
IN
CC
– 0.3V or VIN < 0.3V
Operation Recovery Time t
2.0 V
RC
Data Retention Waveform
DATA RETENTION MODE
V
CC
t
CDR
CE
VDR> 2V
3.0V3.0V
t
R
1019–5
Switching Waveforms
Read Cycle No. 1
[9, 10]
ns
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
Notes:
9. Device is continuously selected. OE
10. WE
is HIGH for read cycle .
11. Address valid prior to or coincident with CE
HIGH IMPEDANCE
t
LZCE
t
PU
, CE = VIL.
t
OHA
[10, 11]
t
ACE
t
t
LZOE
50%
transition LOW .
DOE
t
RC
t
AA
1019–6
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
50%
HIGH
IMPEDANCE
ICC
ISB
1019–7
Document #: 38-05055 Rev. ** Page 4 of 8
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE
Controlled)
ADDRESS
CE
WE
DATA I/O
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[12, 13]
t
SA
t
AW
t
WC
[12, 13]
t
PWE
t
SCE
t
SCE
t
SD
DATA VALID
CY7C1019
t
HA
t
HD
1019–8
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
t
PWE
WE
OE
t
SD
DATA I/O
Notes:
12. Data I/O is high impedance if OE
13. If CE
14. During this period the I/Os are in the output state and input signals should not be applied.
goes HIGH simultaneousl y with WE going HIGH, the o utput remai ns in a hig h-impedanc e stat e.
NOTE 14
= VIH.
t
HZOE
DATAINVALID
t
HA
t
HD
1019–9
Document #: 38-05055 Rev. ** Page 5 of 8
Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
WE
DATA I/O
Controlled, OE LOW)
t
SA
NOTE
14
t
HZWE
PRELIMINARY
[13]
t
t
SCE
t
AW
WC
t
PWE
t
SD
DATA VALID
t
HA
t
LZWE
CY7C1019
t
HD
1019–10
Truth Table
CE OE WE I/O0–I/O
7
H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Mode Power
Ordering Information
Speed
(ns) Ordering Code
10 CY7C1019-10VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-10VC V33 32-Lead 400-Mil Molded SOJ
12 CY7C1019-12VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-12VC V33 32-Lead 400-Mil Molded SOJ
15 CY7C1019-15VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-15VC V33 32-Lead 400-Mil Molded SOJ
Shaded area contains advance information.
Package
Name Package Type
Operating
Range
Document #: 38-05055 Rev. ** Page 6 of 8
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
PRELIMINARY
32-Lead (400-Mil) Molded SOJ V33
CY7C1019
Document #: 38-05055 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
PRELIMINARY
Document Title: 7C1019 128K x 8 Static RAM
Document Number: 38-05055
REV. ECN NO.
** 107246 09/10/01 SZV Change from Spec number: 38-00440 to 38-05055
Issue
Date
Orig. of
Change Description of Change
CY7C1019
Document #: 38-05055 Rev. ** Page 8 of 8
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