CY7C1018DV33
1-Mbit (128K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C1018CV33
• High speed
—tAA = 10 ns
• Low Active Power
—ICC = 60 mA @ 10 ns
• Low CMOS Standby Power
—I
= 3 mA
SB2
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE
and OE options
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ
Logic Block Diagram
Functional Description
[1]
The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE
), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
through I/O7) is then written into the location
0
through A16).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE
) and Output Enable (OE) LOW while forcing Write
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.
Pin Configuration
SOJ
Top View
A
1
0
A
1
2
A
3
2
A
4
I/O
I/O
V
V
I/O
I/O
WE
CE
CC
SS
A
A
A
A
3
5
6
0
7
1
8
9
10
2
3
11
12
4
13
5
14
6
15
16
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUTBUFFER
A
0
A
1
A
2
A
CE
WE
3
A
4
A
5
A
6
A
A
ROW DECODER
7
8
128K × 8
ARRAY
COLUMN
DECODER
SENSE AMPS
POWER
DOWN
OE
9
10
13
12
11
A
A
A
A
Note
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, a vailable on the internet at www .cypress.com.
16
14
15
A
A
A
A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
16
15
14
13
7
6
SS
CC
5
4
12
11
10
9
8
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05465 Rev. *D Revised November 8, 2006
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CY7C1018DV33
Selection Guide
–10 (Industrial) Unit
Maximum Access Time 10 ns
Maximum Operating Current 60 mA
Maximum Standby Current 3 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
to Relative GND
CC
[2]
in High-Z State .......................................–0.3V to VCC + 0.3V
[2]
...–0.3V to + 4.6V
DC Input Voltage
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns
DC Electrical Characteristics Over the Operating Range
Parameter Description T e st Con dit ion s
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min.,
I
= –4.0 mA
OH
Output LOW Voltage VCC = Min.,
I
= 8.0 mA
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Leakage Current GND < VI < V
[2]
CC
Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
Automatic CE Power-down
Current—TTL Inputs
Automatic CE Power-down
Current—CMOS Inputs
Max. VCC, CE > V
VIN > VIH or VIN < VIL, f = f
Max. VCC, CE > VCC – 0.3V,
> VCC – 0.3V, or VIN < 0.3V, f = 0
V
IN
= 1/t
RC
IH
[2]
................................–0.3V to VCC + 0.3V
Ambient
Temperature
V
CC
–10 (Industrial)
Min. Max.
2.4 V
0.4 V
+ 0.3 V
CC
–0.3 0.8 V
–1 +1 µA
100MHz 60 mA
83MHz 55 mA
66MHz 45 mA
40MHz 30 mA
10 mA
MAX
3mA
Speed
Unit
Note
(min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
2. V
IL
Document #: 38-05465 Rev. *D Page 2 of 9
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CY7C1018DV33
Capacitance
[3]
Parameter Description T e st Con dit ion s Max. Unit
C
IN
C
OUT
Thermal Resistance
Parameter Description Test Conditions
Θ
JA
Θ
JC
AC Test Loads and Waveforms
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
Output Capacitance 8 pF
[3]
400-Mil
Wide SOJ
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
57.61 °C/W
40.53 °C/W
(Junction to Case)
[4]
ALL INPUT PULSES
90%
10%
(b)
OUTPUT
Z = 50
Ω
50Ω
1.5V
30 pF*
3.0V
GND
Rise Time: 1 V/ns
(a)
90%
Fall Time: 1 V/ns
Unit
10%
High-Z characteristics:
3.3V
OUTPUT
5 pF
R 317 Ω
R2
351Ω
(c)
Notes
3. T ested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05465 Rev. *D Page 3 of 9
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CY7C1018DV33
AC Switching Characteristics
Parameter Description
Read Cycle
[6]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[9]
t
PU
[9]
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
VCC(typical) to the first access 100 µs
Read Cycle Time 10 ns
Address to Data Valid 10 ns
Data Hold from Address Change 3 ns
CE LOW to Data Valid 10 ns
OE LOW to Data Valid 5 ns
OE LOW to Low-Z 0 ns
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up 0 ns
CE HIGH to Power-down 10 ns
[10, 11]
Write Cycle Time 10 ns
CE LOW to Write End 8 ns
Address Set-up to Write End 8 ns
Address Hold from Write End 0 ns
Address Set-up to Write Start 0 ns
WE Pulse Width 7 ns
Data Set-up to Write End 5 ns
Data Hold from Write End 0 ns
WE HIGH to Low-Z
WE LOW to High-Z
Over the Operating Range
[7, 8]
[8]
[7, 8]
[8]
[7, 8]
[5]
–10 (Industrial)
Min. Max.
3ns
3ns
Unit
5ns
5ns
5ns
Notes
5. Test condi tions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
7. t
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10.The internal Write time of the memory is defined by the overlap of CE
11.The minimum Write cycle time for Write Cycle No. 3 (WE
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
POWER
, t
HZCE
, and t
HZOE
signals can terminate the Write . The input dat a set-up and ho ld timing should be referenced t o the leading edge of the signal t hat terminates the Write.
are specified with a load capacitance of 5 pF as in (c) of AC T est Loads. Transition is measured when the outputs enter a high impedance state.
HZWE
Document #: 38-05465 Rev. *D Page 4 of 9
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
HZOE
LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
is less than t
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given device.
LZWE
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CY7C1018DV33
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Max. Unit
V
DR
I
CCDR
[3]
t
CDR
[12]
t
R
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
VCC for Data Retention 2 V
Data Retention Current VCC = VDR = 2.0V , CE > VCC – 0.3V ,
> VCC – 0.3V or VIN < 0.3V
V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
DATA RETENTION MODE
V
V
CC
t
CDR
CE
[13, 14]
DR
> 2V
RC
3.0V3.0V
t
R
3mA
ns
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[14, 15]
t
ACE
t
LZOE
t
OHA
t
DOE
50%
tRC
RC
t
AA
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
Notes
12.Full device operation requires linear V
13.Device is continuously selected. OE
is HIGH for Read cycle.
14.WE
15.Address valid prior to or coincident with CE
ramp from V
CC
, CE = VIL.
transition LOW.
Document #: 38-05465 Rev. *D Page 5 of 9
DR
to V
> 50 µs or stable at V
CC(min.)
CC(min.)
> 50 µs.
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Switching Waveforms (continued)
Write Cycle No. 1 (CE
ADDRESS
CE
WE
Controlled)
[16, 17]
t
SA
CY7C1018DV33
t
WC
t
SCE
t
t
AW
t
PWE
SCE
t
HA
DATA I/O
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
OE
DATA I/O
NOTE 18
t
HZOE
[16, 17]
t
WC
t
SD
DATA VALID
t
PWE
t
SD
DATAINVALID
t
HD
t
HA
t
HD
Notes
16.Data I/O is high impedance if OE
17.If CE
goes HIGH simultaneously with WE g oing HIGH, the outp ut remains in a hi gh-impedance st ate.
18.During this period the I/Os are in the output state and input signals should not be applied.
= VIH.
Document #: 38-05465 Rev. *D Page 6 of 9
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Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
Controlled, OE LOW)
[11, 17]
t
SCE
t
CY7C1018DV33
WC
t
HA
t
LZWE
t
HD
WE
DATA I/O
NOTE 18
t
AW
t
SA
t
HZWE
t
PWE
t
SD
DATA VALID
Truth Table
CE OE WE I/O0–I/O
7
H X X High-Z Power-down Standby (I
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High-Z Selected, Outputs Disabled Active (I
Mode Power
SB
)
CC
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C1018DV33-10VXI 51-85041 32-pin (300-Mil) Molded SOJ (Pb-free) Industrial
Please contact your local Cypress sales representative for availabili ty of these parts.
Package
Diagram
Package Type
)
Operating
Range
Document #: 38-05465 Rev. *D Page 7 of 9
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Package Diagram
Figure 1. 32-pin (300-Mil) Molded SOJ (51-85041)
CY7C1018DV33
PIN 1 I.D
DIMENSIONS IN INCHES
LEAD COPLANARITY 0.004 MAX.
*
0.260
0.275
0.050
TYP.
0.810
0.830
0.026
0.032
0.014
0.020
0.292
0.305
*
0.025
MIN.
0.330
0.340
0.128
0.140
*
All product and company names mentioned in this document are the trademarks of their respective holders.
MIN.
MAX.
0.006
0.012
51-85041-*A
Document #: 38-05465 Rev. *D Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch an ge without notice. Cypress Semiconductor Corporation assumes no resp onsibility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY7C1018DV33, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05465
REV. ECN NO. Issue Date
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 238471 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165)
*B 262950 See ECN RKF Added Data Retention Characteristics table
*C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns
*D 520647 See ECN VKN Converted from Preliminary to Final
Orig. of
Change
Description of Change
Pb-free Offering in the Ordering Information
Added T
Shaded Ordering Information
Spec in Switching Characteristics table
power
Removed Commercial Operating rang e
Removed 8 ns speed bin
Added I
Updated Thermal Resistance table
values for the frequencies 83MHz, 66MHz and 40MHz
CC
Updated Ordering Information Table
Changed Overshoot spec from V
+2V to VCC+1V in footnote #2
CC
CY7C1018DV33
Document #: 38-05465 Rev. *D Page 9 of 9
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