Cypress Semiconductor CY7C1018CV33-8VC, CY7C1018CV33-15VC, CY7C1018CV33-12VC, CY7C1018CV33-10VC Datasheet
CY7C1018CV33
128K x 8 St atic RAM
Features
device has an aut omatic po wer-down fea ture that sig nificantl y
reduces power consumption when deselected.
• Pin- and function-compatible with CY7C1018BV33
• High speed
—t
= 8, 10, 12, 15 ns
AA
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when dese lec ted
• Easy memory expans ion with C E
and OE options
• Available in 300-mil-wide 32-pin SOJ
Functional Description
[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is pr ovided by an ac tive LOW Chip Enable (CE
), an
Writing to the device is accomplished by taking Chip Enable
) and Write Enable ( WE) inputs LOW. Data on the eight I/O
(CE
pins (I/O
specified on the address pins (A
through I/O7) is then written into the location
0
through A16).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE
) and Output Enable (OE) LOW while forcing Write
) HIGH. Unde r these co nditions, t he contents o f
the memory location s pecif ied by th e addres s pins will app ear
on the I/O pins.
The eight input/output pi ns (I/O
high-impedance state when the device is deselected (CE
through I/O7) are placed in a
0
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
active LOW Output Enable ( OE), and thre e-st ate driv ers. Th is
Logic Block Diagram
Pin
Configurations
SOJ
T op V ie w
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
16
15
14
13
7
6
SS
CC
5
4
12
11
10
9
8
CE
WE
OE
A
1
0
A
1
2
A
3
I/O
I/O
V
V
I/O
I/O
WE
A
CE
CC
SS
A
A
A
A
2
4
3
5
6
0
7
1
8
9
10
2
3
11
12
4
13
5
14
6
15
16
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
7
8
ROW DECODER
A
A
512 x 256 x 8
ARRAY
COLUMN
DECODER
9
10
A
A11A13A
A
SENSE AMPS
POWER
DOWN
14
15
12
16
A
A
A
Selection Guide
7C1018CV33-8 7C1018CV33-10 7C1018CV33-12 7C1018CV33-15 Unit
Maximum Acces s Time 8 10 12 15 ns
Maximum Operating Curre nt 95 90 85 80 mA
Maximum Standby Cur r en t 5 5 5 5 mA
Note:
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05131 Rev. *C Revised September 13, 2002
CY7C1018CV33
Maximum Ratings
(Above which the us efu l l ife may be impaired. For us er gui delines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
to Relative GND
CC
DC Voltage Applied to Outputs
[7]
[2]
...–0.5V to + 4.6V
in High-Z State.......................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
OS
CC
SB1
SB2
[3]
Output HIGH Voltage VCC = Min.,
I
= – 4.0 mA
OH
Output LOW Voltage VCC = Min.,
= 8.0 mA
I
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
[2]
GND < VI < VCC,
Output Disabled
VCC = Max.,
V
= GND
OUT
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
Max. VCC, CE > V
VIN > VIH or
VIN < VIL, f = f
Max. V
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
or VIN < 0.3V, f = 0
= 1/t
CC
CC
RC
IH
MAX
,
DC Input Voltage
[2]
................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 3.3V ± 10%
7C1018CV33-87C1018CV33
-10
7C1018CV33
-12
7C1018CV33
2.4 2.4 2.4 2.4 V
0.4 0.4 0.4 0.4 V
CC
+ 0.3
2.0 V
+ 0.3
CC
2.0 V
CC
+ 0.3
2.0 V
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
–1+1–1+1–1+1–1+1µA
–1+1–1+1–1+1–1+1µA
–300 -300 –300 -300 mA
95 90 85 80 mA
15 15 15 15 mA
5555mA
-15
CC
+ 0.3
CC
UnitMin. Max. Min. Max. Min. Max. Min. Max.
V
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
2. V
(min.) = –2.0 V fo r pulse durati ons of l ess tha n 20 ns .
IL
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 8 pF
VCC = 3.3V
8pF
Document #: 38-05131 Rev. *C Page 2 of 7
CY7C1018CV33
AC Test Loads and Waveforms
8-ns devices:
OUTPUT
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0V
GND
Rise Time: 1 V/ns
Z = 50
ALL INPUT PULSES
90%
10%
Switching Characteristics
[5]
Ω
50Ω
1.5V
30 pF*
(a)
90%
10%
(c)
Over the Operating Range
Fall Time: 1 V/ns
10-, 12-, 15-ns devices:
3.3V
OUTPUT
30 pF
R 317Ω
R2
351Ω
(b)
High-Z characteristics:
3.3V
OUTPUT
5 pF
R 317Ω
R2
351Ω
(d)
[6]
7C1018CV33-8 7C1018CV33-10 7C1018CV33-12 7C1018CV33-15
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[9]
t
PU
[9]
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thèvenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
HZOE
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE
signals can termi nate the Wr ite. The input data set-up and ho ld ti ming sh ould b e refe renced to the l eadin g edge of the s ignal t hat termi nates the Wri te.
11. The minimum Write cycle time for Write Cycle No. 3 (WE
Read Cycle Time 8 10 12 15 ns
Address to Data Valid 8 10 12 15 ns
Data Hold from Address
3333 ns
Change
CE LOW to Data Valid 8 10 12 15 ns
OE LOW to Data Valid 5 5 6 7 ns
OE LOW to Low-Z 0 0 0 0 ns
[8]
[7, 8]
[7, 8]
4567 ns
3333 ns
4567 ns
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up 0 0 0 0 ns
CE HIGH to Power-down 8 10 12 15 ns
[10, 11]
Write Cycle Time 8 10 12 15 ns
CE LOW to Write End 7 8 9 10 ns
Address Set-up to Write End 7 8 9 10 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-up to Write Start 0 0 0 0 ns
WE Pulse Width 67810 ns
Data Set-up to Write End 5 5 6 8 ns
Data Hold from Write End 0 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z
, t
, and t
HZCE
HZWE
are specified wi th a l oad cap acit ance of 5 pF as in (d) of AC Te st Lo ads. Transition is me asured ± 500 mV fr om steady-st ate volt age.
[8]
[7, 8]
3333 ns
4567 ns
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
HZOE
LOW and WE LOW. CE and WE must be LOW to initiate a Write, an d the transiti on of any of t hese
is less than t
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given dev ice.
LZWE
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Document #: 38-05131 Rev. *C Page 3 of 7
Switching Waveforms
Read Cycle No. 1
[12, 13]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
CY7C1018CV33
t
RC
t
t
OHA
AA
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDAN CE
t
LZCE
t
PU
CURRENT
Write Cycle No. 1 (CE Controlled)
ADDRESS
CE
[13, 14]
t
ACE
t
LZOE
[15, 16]
t
DOE
50%
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
t
WC
t
SCE
t
SA
t
t
AW
t
PWE
SCE
t
HA
WE
t
HD
DATA I/O
Notes:
12. Device is continuously selected. OE
is HIGH for Read cycle.
13. WE
14. Address valid prior to or coincident with CE transi tion LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE
goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.
, CE = VIL.
t
SD
DATA VALID
Document #: 38-05131 Rev. *C Page 4 of 7
CY7C1018CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE
ADDRESS
CE
Controlled, OE HIGH During Write)
t
SCE
[15, 16]
t
WC
t
SA
WE
OE
DATA I/O
NOTE 17
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
t
SA
WE
[11, 16 ]
t
AW
t
PWE
t
SD
t
HA
t
HD
DATAINVALID
t
WC
t
SCE
t
AW
t
PWE
t
HA
t
LZWE
t
HD
DATA I/O
NOTE
17
t
HZWE
t
SD
DATA VALID
Truth Table
CE OE WE I/O0–I/O
7
H X X High-Z Power-d own Standby (I
X X X High-Z Power-down Standby (I
L L H Data Out Read Active (I
L X L Data In Write Active (I
L H H High-Z Selected, Outputs Disabled Active (I
Note:
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05131 Rev. *C Page 5 of 7
Mode Power
)
SB
)
SB
)
CC
)
CC
)
CC
CY7C1018CV33
Ordering Information
Speed
(ns) Ordering Code
8 CY7C1018CV33-8VC V32 32-lead 300-mil Molded SOJ Commercial
10 CY7C1018CV33-10VC V32 32-lead 300-mil Molded SOJ
12 CY7C1018CV33-12VC V32 32-lead 300-mil Molded SOJ
15
CY7C1018CV33-15VC V32 32-lead 300-mil Molded SOJ
Package Diagram
Package
Name Package Type
32-lead (300-mil) Molded SOJ V32
Operating
Range
51-85041-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05131 Rev. *C Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1018CV33
Document History Page
Document Title: CY7C1018CV33 128K x 8 Static RAM
Document Number: 38-05131
REV. ECN NO.
** 109426 12/14/01 HGK New Data Sheet
*A 113432 04/10/02 NSL AC Test Loads split based on speed
*B 115046 05/30/02 HGK I
*C 116476 09/16/02 CEA Add applications foot note on data sheet, pg 1.
Issue
Date
Orig. of
Change Description of Change
CC
and I
modified
SB1
Document #: 38-05131 Rev. *C Page 7 of 7
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