Datasheet CY7C1019BV33L-15ZC, CY7C1019BV33-10VC, CY7C1018BV33-15VI, CY7C1018BV33-15VC, CY7C1018BV33-12VC Datasheet (Cypress Semiconductor)

019V33

CY7C1019BV33

CY7C1018BV33

128K x 8 Static RAM

Features

• High speed
—t

= 10 ns

AA

• CMOS for optimum speed/power

• Center power/ground pinout

• Automatic power-down when deselected

• Easy memory expansion with CE

and OE options

• Functionally equivalent to CY7C1019V33 and/or

CY7C1018V33

Functional Description

The CY7C1019BV33/CY7C1018BV33 is a high-performance
CMOS static RAM org anized as 131,0 72 words b y 8 bits. Easy
memory expansion is pr ovide d by an activ e LO W Chip Enab le

), an active LOW Out put Enable (OE), and three-state driv-

(CE
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.

Logic Block Diagram

INPUT BUFFER

A

0

A

1

A

2

A

3

A

CE

WE

OE

4

A

5

A

6

A
A

ROW DECODER

7
8

512 x 256 x 8

ARRAY

COLUMN

DECODER

9

12

10

A

A

A11A13A

SENSE AMPS

POWER

DOWN

14

15

16

A

A

A

Writing to the device is accomplished by taking Chip Enable

) and Write Enable (WE) inpu ts LOW. Data on the eight I/O

(CE
pins (I/O
fied on the address pins (A

through I/O7) is then written into the location speci-

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enable ( OE) LOW while forcing Write

) HIGH. Under these conditions, the contents of
the memory location specifie d b y t he addre ss pins w ill a ppear
on the I/O pins.

The eight input/output pins (I/O
high-impedance state when the device is deselected (CE

through I/O7) are placed in a

0

HIGH), the outputs are disabled (OE HIGH), or duri ng a w r it e
operation (CE

LOW, and WE LOW).

The CY7C1019BV33 is available in standard 32-pin TSOP
Type II and 400-mil-wide package. The CY7C1018BV33 is
available in a standard 300-mil-wide package.

Configurations

Pin

SOJ / TSOPII

Top View

32
31

30
29

28
27
26
25
24
23
22
21
20
19
18

17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

A

1

0

A

1

2

A

3

2

I/O
I/O

V
V

I/O
I/O

WE

A

CE

CC

SS

A
A
A

A

4

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

0

1

2

3

4

5

6

7

Selection Guide

7C1019BV33-10
7C1018BV33-10

Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 175 160 145
Maximum Standby Current (mA) 5 5 5

L − 0.5 0.5

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

7C1019BV33-12
7C1018BV33-12

7C1019BV33-15
7C1018BV33-15

June 11, 2001

CY7C1019BV33

CY7C1018BV33

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage ...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Po wer Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

[1]

DC Input Voltage

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

[1]

.................................–0.5V to VCC + 0.5V

Electrical Characteristics

Parameter Description Min. Max. Min. Max. Min. Max. Unit

V

V

V

V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH

OL

IH

IL

Output HIGH Voltage VCC = Min.,

Output LOW Voltage VCC = Min.,

Input HIGH Voltage 2.2 V

Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage

Current
VCC Operating

Supply Current

Automatic CE
Power-Down Current
—TTL Inputs

Automatic CE
Power-Down Current
—CMOS Inputs

[1]

....–0.5V to +7.0V

Over the Operating Range

Test Conditions

= – 4.0 mA

I

OH

= 8.0 mA

I

OL

[1]

CC

GND < VI < VCC,
Output Disab le d

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

Max. V
VIN > VIH or

< VIL, f = f

V

IN

= 1/t

, CE > V

CC

RC

IH

MAX

Max. VCC,
CE > VCC – 0.3V,

> VCC – 0.3V,

V

IN

< 0.3V, f = 0

or V

IN

Range

Commercial 0°C to +70°C 3.3V ± 10%

7C1019BV33-10
7C1018BV33-10

7C1019BV33-12
7C1018BV33-12

2.4 2.4 2.4 V

0.4 0.4 0.4 V

CC

+ 0.3

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

–1+1–1+1–1+1µA
–5+5–5+5–5+5µA

175 160 145 mA

20 20 20 mA

555mA

L − 0.5 0.5

Ambient

Temperature

2.2 V
+ 0.3

[2]

7C1019BV33-15
7C1018BV33-15

CC

2.2 V

CC

+ 0.3

V

CC

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

(min.) = –2.0V f or pulse durat ions of less than 20 ns .

1. V

IL

is the “Instant On” case temper ature.

2. T

A

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,

= 5.0V

V

Output Capacitance 8 pF

CC

6pF

2

AC Test Loads and Waveforms

CY7C1019BV33

CY7C1018BV33

Ω

(a)

THÉ

R1 480

167

OUTPUT

R2

Ω

255

Ω

1.73V

[4]

Over the Operating Range

3.3V

OUTPUT

30 pF

INCLUDING
JIG AND
SCOPE

Equivalent to: VENIN EQUIVALENT

OUTPUT

Switching Characteristics

3.3V

5 pF

INCLUDING
JIG AND
SCOPE

Ω

R1 480

(b)

7C1019BV33-10
7C1018BV33-10

R2

255

3.0V

GND

Ω

≤

3 ns

7C1019BV33-12
7C1018BV33-12

ALL INPUT PULSES

90%

10%

7C1019BV33-15
7C1018BV33-15

90%

10%

≤

3

ns

Parameter Description Min.Max.Min.Max.Min.Max.Unit

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
I

OL/IOH

5. t

HZOE

6. At any given temperature and voltage condition, t

7. The internal wri te tim e of the mem ory is de fin ed b y the overlap of CE
signals can terminate the write. The input data set -up and hold timing sho uld be ref erenced to the leadi ng edge of the signal that terminat es th e write.

8. The minimum write cycle time for Write Cycle no. 3 (WE

Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 10 12 1 5 ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low Z 0 0 0 n s

[6]

[5, 6]

[5, 6]

567ns

333ns

567ns

OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 0 0 ns
CE HIGH to Power-Down 10 12 15 ns

[7, 8]

Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-Up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-Up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z

and 30-pF load cap acitanc e.

, t

HZCE

, and t

are specified with a load capacitan ce of 5 pF as in part (b) of AC Test Loads. T r ansition is measured ±500 mV from steady-state v oltage.

HZWE

[6]

[5, 6]

333ns

is less than t

HZCE

controlled, OE LOW) is the sum of t

, t

LZCE

HZOE

LOW and WE LO W . CE and WE m ust be LO W to initiate a write , and the tr ansition of an y of these

567ns

is less than t

LZOE

, and t

HZWE

is less than t

HZWE

and tSD.

for any giv en device.

LZWE

3

CY7C1019BV33

CY7C1018BV33

Data Retention Characteristics

Over the Operating Range (L Version Only)

Parameter Description Conditions Min. Max. Unit

V

DR

I

CCDR

t

CDR

t

R

[3]

VCC for Data Retention No input may exceed VCC + 0.5V
Data Retention Current 150 µA
Chip Deselect to Data Retention Time 0 ns

VCC = VDR = 2.0V,

> VCC – 0.3V,

CE

> VCC – 0.3V or VIN < 0.3V

V

IN

2.0 V

Operation Recovery Time 200 µs

Data Retention Waveform

DATA RETENTION MODE

V

CC

t

CDR

CE

VDR> 2V

3.0V3.0V
t

R

Switching Waveforms

Read Cycle No. 1

ADDRESS

[9, 10]

t

RC

DATA OUT

PREVIOUS DATA VALID DATA VALID

Read Cycle No. 2 (OE Controlled)

ADDRESS

CE

OE

DATA OUT

V

CC

SUPPLY

CURRENT

Notes:

9. Device is continuously selected. OE
is HIGH f or read cycle .

10. WE

11. Address valid prior to or coincident with CE

HIGH IMPEDANCE

t

LZCE

t

PU

, CE = VIL.

t

OHA

[10, 11]

t

ACE

t

t

LZOE

50%

transition LO W .

DOE

t

AA

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

50%

HIGH

IMPEDANCE

ICC
ISB

4

CY7C1019BV33

CY7C1018BV33

Switching Waveforms

Write Cycle No. 1 (CE

(continued)

Controlled)

[12, 13]

ADDRESS

CE

t

SA

t

AW

WE

DA TA I/O

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)

t

WC

[12, 13]

t

WC

t

PWE

t

SCE

t

SCE

t

SD

DATA VALID

t

HA

t

HD

ADDRESS

t

SCE

CE

t

AW

t

SA

t

PWE

WE

OE

t

SD

DATA I/O

Notes:

12. Data I/O is high impedance if OE

13. If CE

14. During this period the I/Os are in the output state and input signals should not be applied.

goes HIGH simultaneous ly with WE going HIGH , the out put re mains in a hi gh-imp edance st ate .

NOTE 14

= VIH.

t

HZOE

DATAINVALID

t

HA

t

HD

5

CY7C1019BV33

CY7C1018BV33

Switching Waveforms

Write Cycle No. 3 (WE

ADDRESS

CE

WE

DATA I/O

NOTE

(continued)

Controlled, OE LOW)

t

SA

14

t

HZWE

[13]

t

AW

t

SCE

t

WC

t

PWE

t

SD

DATA VALID

t

HA

t

LZWE

t

HD

Truth Tab le

CE OE WE I/O0–I/O

7

H X X High Z Power-Down Standby (ISB)

X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)

Mode Power

6

CY7C1019BV33

CY7C1018BV33

Ordering Information

Speed

(ns) Ordering Code

10 CY7C1018V33-10VC V32 32-Lead 300-Mil Molded SOJ Commercial

CY7C1019BV33-10VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019BV33-10ZC ZS32 32-Lead TSOP Type II

12 CY7C1018BV33-12VC V32 32-Lead 300-Mil Molded SOJ

CY7C1018BV33L-12VC V32 32-Lead 300-Mil Molded SOJ
CY7C1019BV33-12VC V33 32-Lead 400-Mil Molded SOJ

CY7C1019BV33-12ZC ZS32 32-Lead TSOP Type II

CY7C1019BV33L-12VC V33 32-Lead 400-Mil Molded SOJ

CY7C1019BV33L-12ZC ZS32 32-Lead TSOP Type II

15 CY7C1018BV33-15VC V32 32-Lead 300-Mil Molded SOJ

CY7C1018BV33L-15VC V32 32-Lead 300-Mil Molded SOJ
CY7C1018BV33-15VI V32 32-Lead 300-Mil Molded SOJ
CY7C1019BV33-15VC V33 32-Lead 400-Mil Molded SOJ

CY7C1019BV33-15ZC ZS32 32-Lead TSOP Type II

CY7C1019BV33L-15VC V33 32-Lead 400-Mil Molded SOJ

CY7C1019BV33L-15ZC ZS32 32-Lead TSOP Type II

CY7C1019BV33-15VI V33 32-Lead 400-Mil Molded SOJ

CY7C1019BV33-15ZI ZS32 32-Lea d TSOP Type II Industrial

Document #: 38-01053-*B

Package

Name Pac ka ge Type

Operating

Range

7

Package Diagram

CY7C1019BV33

CY7C1018BV33

32-Lead (400-Mil) Molded SOJ V33

32-Lead (300-Mil) Molded SOJ V32

51-85041-A

51-85041

8

Package Diagram

CY7C1019BV33

CY7C1018BV33

32-Lead

TSOP II ZS32

51-85095

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circui try embodied in a Cypress S emiconductor p roduct. Nor does it conv ey or imply an y license under pa tent or other rights. Cypre ss Semiconductor doe s not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.