Datasheet CY7C1012AV33-8BGI, CY7C1012AV33-8BGC, CY7C1012AV33-12BGI, CY7C1012AV33-12BGC, CY7C1012AV33-10BGI Datasheet (Cypress Semiconductor)

CY7C1012AV33

512K x 24 St atic RAM

Features

• High speed
—tAA = 8, 10, 12 ns

• Low active power
—1080 mW (max.)

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

• Automatic power-down when dese lec ted

• TTL-compatible inputs and outputs

• Easy memory expans ion with CE

features

, CE1 and CE2

0

Functional Description

The CY7C1012A V33 is a hi gh-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separately con trolled by th e indi vidua l chi p sel ect s ( CE

). CE0 controls the data on the I/O0–I/O7, while CE

CE

2

controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O
power-down feature that significantly reduces power

–I/O23. This device has an automatic

16

, CE1,

0

consumption when deselected.

Functional Block Diagram

INPUT BUFFER

Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE

) input is LOW. Data on the respective
input/output (I/O) pins is then writ ten into the location spec ified
on the address pins (A
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE

). Asserting all of the chip selects

0–A18

) is ignored while in WRITE

mode.
Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select
controlling that byte is LOW an d write enable (WE
output enable (OE

) remains LOW . Under these conditions , the
contents of th e memory loc ation sp ecified o n the addre ss pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.

The 24 I/O pins (I/O
state when all the chip selects are HIGH or when the output
enable (OE
refer to the truth table of this data sheet.

1

) is HIGH during a READ mode. For further details,

–I/O23) are placed in a high-impedance

0

The CY7C1012AV33 is available in a standard 119-ball BGA.

) HIGH while

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A
A
A

ROW DECODER

7
8
9

10

11

A

A

512K x 24

ARRAY

4096 x 4096

COLUMN

DECODER

12

15

13

A

AAA

A14A

SENSE AMPS

CE0, CE1, CE

CONTROL LOGIC

16

17

18

A

WE
OE

I/O0–I/O
I/O8–I/O
I/O16–I/O

2

7

15

23

Selection Guide

–8 –10 –12 Unit

Maximum Acces s Time 8 10 12 ns
Maximum Operating Curre nt Commercial 300 275 260 mA

Industrial 300 275 260

Maximum CMOS Standby Current Commercial/Industrial 50 50 50 mA

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05254 Rev. *D Revised November 12, 2002

Pin Configurations

CY7C1012AV33

119 BGA

Top View

1234567

A NCAAAAANC
B NC A A CE0 AANC
C I/O
D I/O
E I/O
F I/O
G I/O
H I/O

12
13
14
15
16
17

J NC V
K I/O
L I/O
M I/O
N I/O
P I/O
R I/O

18
19
20
21
22
23

T NC A A WE AANC
U NC A A OE

NC CE1 NC CE2 NC I/O

V

DD

V

SS

V

DD

V

SS

V

DD
SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

ANCNCNCAI/O

I/O
I/O
I/O
I/O
I/O

DNU

I/O
I/O
I/O
I/O

I/O

0
1
2
3
4
5

6
7
8

9
10
11

AANC

Document #: 38-05254 Rev. *D Page 2 of 9

Maximum Ratings

(Above which the us efu l l ife may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High-Z State

[1]

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

V

V

V

V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH

OL

IH

IL

[1]

Output HIGH Voltage VCC = Min.,

Output LOW Voltage VCC = Min.,

Input HIGH Voltage 2.0 V

Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 V
Input Load Current GND < VI < V
Output Leakage Cu rrent GND < V
VCC Operating

Supply Current
Automatic CE

Power-down Current
—TTL Inputs

Automatic CE
Power-down Current
—CMOS Inputs

[1]

....–0.5V to +4.6V

= –4.0 mA

I

OH

= 8.0 mA

I

OL

CC

< VCC, Output Disabled –1+1–1+1–1+1µA

OUT

VCC = Max.,

MAX

= 1/t

RC

f = f
Max. VCC, CE > V

VIN > VIH or
V

< VIL, f = f

IN

Max. V

> VCC – 0.3V,

CE

> VCC – 0.3V,

V

IN

or VIN < 0.3V , f = 0

CC

MAX

,

Commercial 300 275 260 mA
Industrial 300 275 260 mA

IH

Commercial
/Industrial

CY7C1012AV33

[1]

DC Input Voltage

Current into Outputs (LOW).........................................20 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C

[2]

................................–0.5V to VCC + 0.5V

Ambient

Temperature V

CC

–8 –10 –12

UnitMin. Max. Min. Max. Min. Max.

2.4 2.4 2.4 V

0.4 0.4 0.4 V

CC

+ 0.3

2.0 V
+ 0.3

CC

2.0 V

CC

+ 0.3

–1+1–1+1–1+1µA

100 100 100 mA

50 50 50 mA

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. V

(min.) = –2.0 V fo r pulse durati ons of l ess tha n 20 ns .

IL

refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time.

2. CE

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
I/O Capacitance 10 pF

Document #: 38-05254 Rev. *D Page 3 of 9

CY7C1012AV33

AC Test Loads and Waveforms

OUTPUT

Z0= 50Ω

(a)

Rise time > 1 V/ns

[4]

50Ω

= 1.5V

V

TH

30 pF*

* Capacitive Load consists of all compo­nents of the test environment.

ALL INPUT PULSES

3.3V

GND

90%

10%

90%

OUTPUT

10%

Fall time:
> 1 V/ns

3.3V

5 pF

INCLUDING
JIG AND
SCOPE

R1 317 Ω

R2

351Ω

(b)

(c)

AC Switching Characteristics Over the Operating Range

[5]

–8 –10 –12

Parameter Description

UnitMin. Max. Min. Max. Min. Max.

Read Cycle

[6]

t

power

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

t

DBE

t

LZBE

t

HZBE

Write Cycle

t

WC

t

SCE

Notes:

4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
the minimum operating V

5. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and ou tput load ing of the specifi ed

6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t

7. t

8. These parameters are guaranteed by design and are not tested.

9. The internal write time of the memory is defined by the overlap of CE

10. The minimum write cycle time for Write Cycle No. 3 (WE

and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specifie d ot her wise .

I

OL/IOH

is started.

, t

HZOE

±200 mV fro m steady-state voltage.

be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to
the leading edge of the signal that terminates the write.

HZCE

VCC(typical) to the first access 1 1 1 ms
Read Cycle Time 8 10 12 ns
Address to Data Valid 8 10 12 ns
Data Hold from Address Change 3 3 3 ns
CE1, CE2, and CE3 LOW to Data Valid 8 10 12 ns
OE LOW to Data Valid 5 5 6 ns
OE LOW to Low-Z
OE HIGH to High-Z
CE1, CE2, and CE3 LOW to Low-Z
CE1, CE2, or CE3 HIGH to High-Z
CE1, CE2, and CE3 LOW to Power-up
CE1, CE2, or CE3 HIGH to Power-down

[7]

[7]

[7]

[7]

[8]

111 ns

556ns

333 ns

556ns

000 ns

[8]

81012ns
Byte Enable to Data Valid 5 5 6 ns
Byte Enable to Low-Z
Byte Disable to High-Z

[9, 10]

[7]

[7]

111 ns

556ns

Write Cycle Time 8 10 12 ns
CE1, CE2, and CE3 LOW to Write End 6 7 8 ns

(3.0V). As soon as 1 ms (T

, t

HZWE

, normal SRAM operation can begin including reduction in VDD to the data retention (V

DD

time has to be provided initially before a read/write operation

power

, t

HZBE

, and t

LZOE

, t

LZCE

, t

LZWE

, t

are specified with a load capacitance of 5 pF as in part (b) of AC T est Loads. Transition is measured

LZBE

, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must

1

controlled, OE LOW) is the sum of t

HZWE

DD

and tSD.

, 2.0V) voltage.

CCDR

power

) after reaching

Document #: 38-05254 Rev. *D Page 4 of 9

CY7C1012AV33

AC Switching Characteristics Over the Operating Range (continued)

–8 –10 –12

Parameter Description

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

t

BW

Address Set-up to Write End 6 7 8 ns
Address Hold from Write End 0 0 0 ns
Address Set-up to Write Start 0 0 0 ns
WE Pulse Width 678 ns
Data Set-up to Write End 5 5.5 6 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z

[7]
[7]

333 ns

Byte Enable to End of Write 6 7 8 ns

Switching Waveforms

Read Cycle No. 1

ADDRESS

DATA OUT

[11, 12 ]

t

RC

t

t

OHA

PREVIOUS DATA VALID DATA VALID

AA

[5]

UnitMin. Max. Min. Max. Min. Max.

556ns

Read Cycle No. 2 (OE Controlled)

ADDRESS

CE

OE

DATA OUT

V

CC

SUPPLY

CURRENT

Notes:

11. Device is continuously selected. OE
is HIGH for read cycle.

12. WE

13. Address valid prior to or coincident with CE

HIGH IMPEDAN CE

t

LZCE

t

PU

, CE = VIL.

[2, 12, 13]

t

ACE

t

DOE

t

LZOE

50%

transition LOW .

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

50%

HIGH

IMPEDANCE

I

CC

I

SB

Document #: 38-05254 Rev. *D Page 5 of 9

Switching Waveforms (continued)

CY7C1012AV33

Write Cycle No. 1 (CE

Controlled)

[2, 14, 15]

ADDRESS

CE

t

SA

t

AW

WE

DATA I/O

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)

ADDRESS

t

SCE

CE

t

AW

t

SA

WE

t

WC

[14, 15]

t

WC

t

PWE

t

SCE

t

SCE

t

SD

DATA VALID

t

PWE

t

HA

t

HD

t

HA

OE

t

SD

t

WC

DATAINVALID

DATA I/O

NOTE 16

t

HZOE

Write Cycle No. 3 (WE Controlled, OE LOW)

[2, 15]

ADDRESS

t

SCE

CE

t

AW

t

SA

t

PWE

WE

NOTE

DATA I/O

Notes:

14. Data I/O is high impedance if OE

15. If CE

16. During this period the I/Os are in the output state and input signals should not be applied.

goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.

16

= VIH.

t

HZWE

t

SD

DATA VALID

t

HA

t

LZWE

t

HD

t

HD

Document #: 38-05254 Rev. *D Page 6 of 9

Truth Table

CY7C1012AV33

CE

CE

0

CE

1

OE WE I/O0–I/O

2

23

Mode Power

H H H X X High-Z Power-down Standby (ISB)

L H H L H I/O0–I/O7 Data Out Read Active (ICC)
H L H L H I/O8–I/O15 Data Out Read Active (ICC)
H H L L H I/O16–I/O23 Data Out Read Active (ICC)

L L L L H Full Data Out Read Active (ICC)

L H H X L I/O0–I/O7 Data In Write Active (ICC)
H L H X L I/O8–I/O15 Data In Write Active (ICC)
H H L X L I/O16–I/O23 Data In Write Active (ICC)

L L L X L Full Data In Write Active (ICC)

L L L H H High-Z Selected, Outputs Disa bled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code

8 CY7C1012AV33-8BGC BG119 14 × 22 mm 119-ball BGA Commercial

CY7C1012AV33-8BGI

10 CY7C1012AV33-10BGC

CY7C1012AV33-10BGI Industrial

12 CY7C1012AV33-12BGC

CY7C1012AV33-12BGI

Package

Name Package Type

Operating

Range

Industrial

Commercial

Commercial

Industrial

Document #: 38-05254 Rev. *D Page 7 of 9

Package Diagram

CY7C1012AV33

119-ball PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05254 Rev. *D Page 8 of 9

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1012AV33

Document History Page

Document Title: CY7C1012AV33 512K x 24 Static RAM
Document Number: 38-05254

REV. ECN NO.

** 113711 03/11/02 NSL New Data Sheet
*A 117057 07/31/02 DFP Removed 15-ns bin.
*B 117988 09/03/02 DFP Added 8-ns bin.

*C 118992 09/19/02 DFP Change Cin - input capacitance -from 6 pF to 8 pF.

*D 120382 11/15/02 DFP Final data sheet. Added note 4 to “AC Test Loads and Waveforms.”

Issue

Date

Orig. of

Change Description of Change

Change Cout -output capacitance from 8 pF to 10 pF.

Document #: 38-05254 Rev. *D Page 9 of 9