Datasheet CY7C1012AV25-8BGI, CY7C1012AV25-8BGC, CY7C1012AV25-12BGC, CY7C1012AV25-10BGI, CY7C1012AV25-10BGC Datasheet (Cypress Semiconductor)

PRELIMINARY

512K x 24 Static RAM

CY7C1012AV25

Features

• High speed
—tAA = 8, 10, 12 ns

• Low active power
—1080 mW (max.)

• Operating voltages of 2.5 ± 0.2V

• 1.5V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE0, CE1 and CE2

features

Functional Description

The CY7C1012AV25 is a high-performance CMOS static
RAM organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE
controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O16–I/O23. This device has an automatic
power-down feature that significantly reduces power
consumption when deselected.

Functional Block Diagram

INPUT BUFFER

Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A0–A16). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.

Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.

The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.

1

The CY7C1012AV25 is available in a standard 119-ball BGA.

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A
A
A

ROW DECODER

7
8
9

10

11

A

A

512K x 24

ARRAY

4096 x 4096

COLUMN

DECODER

12

15

13

A

AAA

A14A

SENSE AMPS

CE0, CE1, CE

CONTROL LOGIC

16

17

18

A

WE

OE

I/O0–I/O
I/O8–I/O
I/O16–I/O

2

7

15

23

Selection Guide

-8 -10 -12 Unit

Maximum Access Time 8 10 12 ns
Maximum Operating Current Commercial 300 275 260 mA

Industrial 300 275 260

Maximum CMOS Standby Current Commercial/Industrial 50 50 50 mA

CypressSemiconductorCorporation • 3901NorthFirstStreet • SanJose, CA 95134 • 408-943-2600
Document #: 38-05337 Rev. ** Revised January 27, 2003

Pin Configurations

PRELIMINARY

CY7C1012AV25

119 BGA

Top View

1 2 3 4 5 6 7

A NC A A A A A NC
B NC A A CE0 A A NC
C I/O
D I/O
E I/O
F I/O
G I/O
H I/O

12
13
14
15
16
17

J NC V
K I/O
L I/O
M I/O
N I/O
P I/O
R I/O

18
19
20
21
22
23

NC CE1 NC CE2 NC I/O

V

DD

V

SS

V

DD

V

SS

V

DD
SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

I/O
I/O
I/O
I/O
I/O

DNU

I/O
I/O
I/O
I/O

I/O

A NC NC NC A I/O

T NC A A WE A A NC
U NC A A OE A A NC

0
1
2
3
4
5

6
7
8

9
10
11

Document #: 38-05337 Rev. ** Page 2 of 9

PRELIMINARY

CY7C1012AV25

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND
DC Voltage Applied to Outputs

in High-Z State

[1]

....................................–0.5V to VCC + 0.5V

[1]

....–0.5V to +3.6V

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

V

V

V

V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH

OL

IH

IL

[1]

Output HIGH Voltage VCC = Min.,

IOH = –1.0 mA

Output LOW Voltage VCC = Min.,

IOL = 1.0 mA

Input HIGH Voltage 2.0 V

Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 V
Input Load Current GND < VI < V
Output Leakage Current GND < V
VCC Operating

Supply Current
Automatic CE

Power-down Current
—TTL Inputs

Automatic CE
Power-down Current
—CMOS Inputs

VCC = Max.,
f = f

MAX

Max. VCC, CE > V
VIN > VIH or
VIN < VIL, f = f

Max. VCC,
CE > VCC – 0.2V,
VIN > VCC – 0.2V,

CC

< VCC, Output Disabled –1 +1 –1 +1 –1 +1 µA

OUT

Commercial 300 275 260 mA

= 1/t

RC

Industrial 300 275 260 mA

IH

MAX

Commercial
/Industrial

or VIN < 0.2V, f = 0

DC Input Voltage

[1]

................................–0.5V to VCC + 0.5V

Current into Outputs (LOW).........................................20 mA

Operating Range

Range

Commercial 0°C to +70°C 2.5V ± 0.2V
Industrial –40°C to +85°C

-8 -10 -12

[2]

2.0 2.0 2.0 V

–1 +1 –1 +1 –1 +1 µA

Ambient

Temperature V

CC

UnitMin. Max. Min. Max. Min. Max.

0.4 0.4 0.4 V

CC

+ 0.3

2.0 V
+ 0.3

CC

2.0 V

CC

+ 0.3

100 100 100 mA

50 50 50 mA

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.

2. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time.

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 2.5V 8 pF
I/O Capacitance 10 pF

Document #: 38-05337 Rev. ** Page 3 of 9

PRELIMINARY

Ω

CY7C1012AV25

AC Test Loads and Waveforms

OUTPUT

Z0= 50Ω

(a)

Rise time > 1 V/ns

[4]

50Ω

= VDD/2

V

TH

30 pF*

* Capacitive Load consists of all compo­nents of the test environment.

ALL INPUT PULSES

2.5V

GND

90%

10%

90%

OUTPUT

10%

Fall time:
> 1 V/ns

2.5V

5 pF

INCLUDING
JIG AND
SCOPE

R1 317

R2

351Ω

(b)

(c)

AC Switching Characteristics Over the Operating Range

[5]

-8 -10 -12

Parameter Description

UnitMin. Max. Min. Max. Min. Max.

Read Cycle

[6]

t

power

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

t

DBE

t

LZBE

t

HZBE

Write Cycle

t

WC

t

SCE

Notes:

4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (T
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (V

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise.

6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
is started.

7. t

8. These parameters are guaranteed by design and are not tested.

9. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be

10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t

, t

HZOE

±200 mV from steady-state voltage.

LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the write.

VCC(typical) to the first access 1 1 1 ms
Read Cycle Time 8 10 12 ns
Address to Data Valid 8 10 12 ns
Data Hold from Address Change 3 3 3 ns
CE1, CE2, and CE3 LOW to Data Valid 8 10 12 ns
OE LOW to Data Valid 5 5 6 ns
OE LOW to Low Z
OE HIGH to High Z
CE1, CE2, and CE3 LOW to Low Z
CE1, CE2, or CE3 HIGH to High Z
CE1, CE2, and CE3 LOW to Power-up
CE1, CE2, or CE3 HIGH to Power-down

[7]

[7]

[7]

[7]

[8]

[8]

1 1 1 ns

5 5 6 ns

3 3 3 ns

5 5 6 ns

0 0 0 ns

8 10 12 ns
Byte Enable to Data Valid 5 5 6 ns
Byte Enable to Low Z
Byte Disable to High Z

[9, 10]

[7]

1 1 1 ns

[7]

5 5 6 ns

Write Cycle Time 8 10 12 ns
CE1, CE2, and CE3 LOW to Write End 6 7 8 ns

, 1.5V) voltage.

CCDR

time has to be provided initially before a read/write operation

power

, t

, t

HZCE

HZWE

HZBE

, and t

LZOE

, t

LZCE

, t

LZWE

, t

are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured

LZBE

and tSD.

HZWE

) after reaching the

power

Document #: 38-05337 Rev. ** Page 4 of 9

PRELIMINARY

CY7C1012AV25

AC Switching Characteristics Over the Operating Range (continued)

-8 -10 -12

Parameter Description

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

t

BW

Address Set-Up to Write End 6 7 8 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 6 7 8 ns
Data Set-Up to Write End 5 5.5 6 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z

[7]
[7]

3 3 3 ns

Byte Enable to End of Write 6 7 8 ns

Data Retention Waveform

DATA RETENTION MODE

V

CC

CE

t

CDR

VDR> 1.5V

[5]

UnitMin. Max. Min. Max. Min. Max.

5 5 6 ns

2.3V2.3V
t

R

Switching Waveforms

Read Cycle No. 1

ADDRESS

DATA OUT

Read Cycle No. 2 (OE Controlled)

ADDRESS

CE

OE

DATA OUT

V

CC

SUPPLY

CURRENT

Notes:

11. Device is continuously selected. OE, CE = VIL.

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

[11, 12]

t

OHA

PREVIOUS DATA VALID DATA VALID

[2, 12, 13]

t

ACE

t

DOE

t

t

LZCE

LZOE

50%

HIGH IMPEDANCE

t

PU

t

RC

t

AA

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

50%

HIGH

IMPEDANCE

I

CC

I

SB

Document #: 38-05337 Rev. ** Page 5 of 9

Switching Waveforms (continued)

Write Cycle No. 1 (CE Controlled)

ADDRESS

CE

WE

DATA I/O

[2, 14, 15]

PRELIMINARY

t

WC

t

SCE

t

SA

t

AW

t

PWE

t

t

SCE

SD

t

HD

CY7C1012AV25

t

HA

DATA VALID

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)

ADDRESS

t

SCE

CE

t

AW

t

SA

WE

OE

DATA I/O

Write Cycle No. 3 (WE Controlled, OE LOW)

ADDRESS

CE

WE

NOTE 16

t

HZOE

[2, 15]

t

SCE

t

AW

t

SA

[14, 15]

t

WC

t

WC

t

PWE

t

PWE

t

SD

DATAINVALID

t

HA

t

HD

t

HA

t

LZWE

t

HD

DATA I/O

Notes:

14. Data I/O is high impedance if OE = VIH.

15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

16. During this period the I/Os are in the output state and input signals should not be applied.

NOTE 16

t

HZWE

t

SD

DATA VALID

Document #: 38-05337 Rev. ** Page 6 of 9

Truth Table

PRELIMINARY

CY7C1012AV25

CE

CE

0

CE

1

OE WE I/O0–I/O

2

23

Mode Power

H H H X X High-Z Power-down Standby (ISB)

L H H L H I/O0–I/O7 Data Out Read Active (ICC)
H L H L H I/O8–I/O15 Data Out Read Active (ICC)
H H L L H I/O16–I/O23 Data Out Read Active (ICC)

L L L L H Full Data Out Read Active (ICC)

L H H X L I/O0–I/O7 Data In Write Active (ICC)
H L H X L I/O8–I/O15 Data In Write Active (ICC)
H H L X L I/O16–I/O23 Data In Write Active (ICC)

L L L X L Full Data In Write Active (ICC)

L L L H H High-Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code

8 CY7C1012AV25-8BGC BG119 14 × 22 mm 119-ball BGA Commercial

CY7C1012AV25-8BGI Industrial

10 CY7C1012AV25-10BGC Commercial

CY7C1012AV25-10BGI Industrial

12 CY7C1012AV25-12BGC Commercial

CY7C1012AV25-12BGI Industrial

Package

Name Package Type

Operating

Range

Document #: 38-05337 Rev. ** Page 7 of 9

Package Diagram

PRELIMINARY

119-lead PBGA (14 x 22 x 2.4 mm) BG119

CY7C1012AV25

51-85115-*B

All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05337 Rev. ** Page 8 of 9

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

PRELIMINARY

Document History Page

Document Title: CY7C1012AV25 512K x 24 Static RAM
Document Number: 38-05337

REV. ECN NO.

** 119630 01/29/03 DFP New Data Sheet

Issue

Date

Orig. of

Change Description of Change

CY7C1012AV25

Document #: 38-05337 Rev. ** Page 9 of 9