Cypress Semiconductor CY7C109-12ZC, CY7C109-25ZI, CY7C109-20ZI, CY7C109-12VC, CY7C109-10VC Datasheet
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128K x 8 Static RAM
CY7C109
CY7C1009
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05032 Rev. ** Revised August 24, 2001
009
Features
• High speed
—t
AA
= 10 ns
• Low active power
—1017 mW (max., 12 ns)
• Low CMOS standby power
—55 mW (max.), 4 mW (Low power version)
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion w ith CE
1
, CE2, and OE options
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS st atic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provid ed by an active L OW chip enable (CE
1
), an
active HIGH chip enable (CE
2
), an active LOW output enable
(OE
), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE
1
) and write enable (WE)
inputs LOW and chip enable two (CE
2
) input HIGH. Data on
the eight I/O pins (I/O
0
through I/O7) is then written into the
location specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE
) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O7) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operat ion (CE
1
LOW, CE2 HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
14
15
Logic Block Diagram Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512x256x8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A13A
12
A
A
10
CE
1
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
151718
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
109–1
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
109–2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
T op View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
109–3
Selection Guide
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009-15
7C109-20
7C1009-20
7C109-25
7C1009-25
7C109-35
7C1009-35
Maximum Access Time (ns) 10 12 15 20 25 35
Maximum Operating Current (mA) 195 185 155 140 135 125
Maximum CMOS Standby Current (mA) 10 10 10 10 10 10
Maximum CMOS Standby Current (mA)
Low Power Version
2 2 2 — — —
Shaded areas contain preliminary information.
CY7C109
CY7C1009
Document #: 38-05032 Rev. ** Page 2 of 12
Maximum Ratings
(Above which the useful life may be im pai red. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to VCC + 0.5V
DC Input Voltage
[1]
................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Electrical Characteristics Ov er the Op erat ing Ran ge
[3]
Test Conditions
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009–15
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= –4.0 mA
2.4 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+ 0.3
2.2 V
CC
+ 0.3
2.2 V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1 +1 –1+1–1+1µA
I
OZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5 +5 –5+5–5+5µA
I
OS
Output Short
Circuit Current
[3]
VCC = Max.,
V
OUT
= GND
–300 –300 –300 mA
I
CC
VCC Operating
Supply Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
195 185 155 mA
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE1 > V
IH
or CE2 < VIL,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
45 45 40 mA
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE
1
> VCC – 0.3V,
or CE2 < 0.3V,
V
IN
> VCC – 0.3V,
or V
IN
< 0.3V, f=0
10 10 10 mA
L
222
Shaded areas contain preliminary information.
CY7C109
CY7C1009
Document #: 38-05032 Rev. ** Page 3 of 12
Electrical Characteristics Ov er the Op erat ing Ran ge (con tin ued)
7C109-20
7C1009-20
7C109-25
7C1009-25
7C109-35
7C1009-35
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= –4.0 mA
2.4 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+ 0.3
2.2 V
CC
+ 0.3
2.2 V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
I
IX
Input Load Current GND < VI < V
CC
–1+1–1+1–1+1µA
I
OZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5+5–5+5–5+5µA
I
OS
Output Sh ort
Circuit Current
[3]
VCC = Max.,
V
OUT
= GND
–300 –300 –300 mA
I
CC
VCC Operating
Supply Current
VCC = Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
140 135 125 mA
I
SB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. V
CC
, CE1 > V
IH
or CE2 < VIL,
V
IN
> VIH or
V
IN
< VIL, f = f
MAX
30 30 25 mA
I
SB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE
1
> VCC – 0.3V,
or CE
2
< 0.3V,
V
IN
> VCC – 0.3V,
or V
IN
< 0.3V, f=0
10 10 10 mA
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 5.0V
9pF
C
OUT
Output Capacitance 8 pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of l ess than 20 ns .
2. T
A
is the “instant on” case tempera ture.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
109–3
109–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤ 3ns ≤ 3 ns
OUTPUT
R1 480
Ω
R1 480Ω
R2
255
Ω
R2
255
Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
CY7C109
CY7C1009
Document #: 38-05032 Rev. ** Page 4 of 12
Switching Characteristics
[3, 5]
Over the Operating Range
7C109-10
7C1009-10
7C109-12
7C1009-12
7C109-15
7C1009-15
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 10 12 15 ns
t
AA
Address to Data Valid 10 12 15 ns
t
OHA
Data Hold from Address Change 3 33ns
t
ACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
10 12 15 ns
t
DOE
OE LOW to Data Va lid 567ns
t
LZOE
OE LOW to Low Z 0 00ns
t
HZOE
OE HIGH to High Z
[6, 7]
567ns
t
LZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[7]
3 33ns
t
HZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[6, 7]
567ns
t
PU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
0 00ns
t
PD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
10 12 15 ns
WRITE CY CLE
[8,9]
t
WC
Write Cycle Time 10 12 15 ns
t
SCE
CE1 LOW to Write End, CE2 HIGH to Write End 8 10 12 ns
t
AW
Address Set-Up to Write End 8 10 12 ns
t
HA
Address Hold from Write End 0 00ns
t
SA
Address Set-Up to Write Start 0 00ns
t
PWE
WE Pulse Width 8 10 12 ns
t
SD
Data Set-Up to Write End 6 78ns
t
HD
Data Hold from Write End 0 00ns
t
LZWE
WE HIGH to Low Z
[7]
3 33ns
t
HZWE
WE LOW to High Z
[6, 7]
567ns
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a lo ad cap acitance of 5 pF as in pa rt (b) of AC Test Loads. Trans ition i s measur ed ±500 mV from s teady- state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE2 HIGH, and WE LOW . CE1 and WE must be LOW and CE2 HIGH to initiate a wri te,
and the transition of an y of these signals can ter minate the w rite. Th e inp ut dat a set- up and hold ti ming sho uld be refere nced t o the leading edge of the si gnal that termin ates
the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and TSD.
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