CY7C107BN
CY7C1007BN
1M x 1 Static RAM
Features
•High speed
—t
= 15 ns
AA
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
automatic power-down feature that reduces power
consumption by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the input pin
(D
IN
address pins (A
) and three-state drivers. These devices have an
) is written into the memory location specified on the
through A19).
0
Reading from the devices is accomplished by taking Chip
Enable (CE
) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(D
) pin.
OUT
The output pin (D
when the device is deselected (CE
operation (CE
and WE LOW).
) is placed in a high-impedance state
OUT
HIGH) or during a write
The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ
LogicBlockDiagram Pin Configuration
SOJ
A
A
A
A
A
A
NC
A
A
A
A
D
OUT
WE
GND
10
11
12
13
14
15
16
17
18
19
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
IN
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
512 x 2048
ARRA
ROW DECODER
COLUMN
DECODER
Y
D
OUT
SENSE AMPS
POWER
DOWN
CE
V
A
A
A
A
A
A
NC
A
A
A
A
D
CE
CC
9
8
7
6
5
4
3
2
1
0
IN
9
A
A10A11A
13
A12A14A16A
15
A17A18A
19
Selection Guide
Maximum Access Time (ns) 15
Maximum Operating Current (mA) 80
Maximum CMOS Standby Current I
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06426 Rev. ** Revised February 1, 2006
SB2
WE
7C107BN-15
7C1007BN-15
(mA) 2
[+] Feedback
CY7C107BN
CY7C1007BN
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................-65°C to +150°C
Ambient Temperature with
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Power Applied..............................................-55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
Relative to GND
CC
.................................... -0.5V to VCC + 0.5V
[1]
..................................-0.5V to VCC + 0.5V
[1]
.....-0.5V to +7.0V
Commercial 0°C to +70°C 5V ± 10%
Industrial -40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description T est Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Leakage Current GND < VI < V
[1]
CC
Output Leakage Current GND < VI < VCC,
Output Disabled
Output Short Circuit
[3]
Current
VCC Operating Supply
Current
Automatic CE Power-Down
Current— TTL Inputs
Automatic CE Power-Down
Current — CMOS Inputs
[4]
VCC = Max., V
VCC = Max., I
MAX
= 1/t
f = f
= GND -300 mA
OUT
= 0 mA,
OUT
RC
Max. VCC, CE > VIH, VIN >V
V
< VIL, f = f
IN
MAX
Max. VCC, CE > VCC – 0.3V,
V
> VCC – 0.3V or VIN < 0.3V, f = 0
IN
Range Ambient Temperature
7C107BN-15
7C1007BN-15
Min. Max. Unit
+ 0.3 V
CC
-0.3 0.8 V
-1 +1 mA
–5 +5 mA
80 mA
IH
or
20 mA
2mA
[2]
V
CC
Parameter Description Test Conditions Max. Unit
: Addresses Input Capacitance TA = 25 × C, f = 1 MHz,
C
IN
: Controls 10 pF
C
IN
C
OUT
Notes:
(min.) = –2.0V for pulse durations of less than 20 ns.
1. V
IL
is the “Instant On” case temperature.
2. T
A
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process ch anges that may affect these parameters.
Output Capacitance 10 pF
Document #: 001-06426 Rev. ** Page 2 of 7
V
CC
7pF
= 5.0V
[+] Feedback
CY7C107BN
CY7C1007BN
AC Test Loads and Waveforms
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalentto: THÉ VENIN EQUIVALENT
Switching Characteristics
R1 480
R2
255Ω
(a) (b)
OUTPUT 1.73V
167Ω
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
[5]
Over the Operating Range
Parameter Description Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
6. At any given temperature and voltage condition, t
7. t
8. The internal write time of the memory is defined by the overlap of CE
and 30-pF load capacitance.
I
OL/IOH
and t
HZCE
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
[8]
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage .
HZWE
Read Cycle Time 15 ns
Address to Data Valid 15 ns
Data Hold from Address Change 3 ns
CE LOW to Data Valid 15 ns
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 ns
CE HIGH to Power-Down 15 ns
Write Cycle Time 15 ns
CE LOW to Write End 12 ns
Address Set-Up to Write End 12 ns
Address Hold from Write End 0 ns
Address Set-Up to Write Start 0 ns
WE Pulse Width 12 ns
Data Set-Up to Write End 8 ns
Data Hold from Write End 0 ns
WE HIGH to Low Z
WE LOW to High Z
HZCE
R1 480Ω
[6]
[6, 7]
[6]
[6, 7]
is less than t
ALL INPUT PULSES
90%
90%
10%
≤ 3
ns
R2
255Ω
3.0V
GND
≤ 3
10%
ns
7C107BN-15
7C1007BN-15
3ns
7ns
3ns
7ns
and t
LZCE
LOW and WE LOW. CE and WE must be LOW to initiate a write, a nd the t ransition of a ny
is less than t
HZWE
for any given device.
LZWE
Document #: 001-06426 Rev. ** Page 3 of 7
[+] Feedback
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
[10, 11]
PREVIOUS DATA VALID DATA VALID
t
OHA
CY7C107BN
CY7C1007BN
t
RC
t
AA
Read Cycle No. 2
[11, 12]
ADDRESS
CE
t
LZCE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
PU
CURRENT
Write Cycle No. 1 (CE Controlled)
ADDRESS
CE
WE
t
RC
t
ACE
t
HZCE
DATA VALID
t
PD
50%
[13]
t
WC
t
SA
t
AW
t
PWE
t
SCE
t
50%
HA
HIGH
IMPEDANCE
I
CC
I
SB
DATA IN
DATA OUT
Notes:
9. No input may exceed V
10.Device is continuously selected, CE
11. WE
is HIGH for read cycle.
12.Address valid prior to or coincident with CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
13.If CE
HIGH IMPEDANCE
+ 0.5V.
CC
= VIL.
transition LOW.
Document #: 001-06426 Rev. ** Page 4 of 7
t
SD
DATA VALID
t
HD
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 2 (WE
ADDRESS
CE
Controlled)
[13]
t
SCE
CY7C107BN
CY7C1007BN
t
WC
WE
DATA IN
DATA OUT
t
SA
DATA UNDEFINED
t
AW
t
HZWE
t
PWE
t
SD
DATA VALID
HIGH IMPEDANCE
t
HD
t
LZWE
t
HA
Truth Table
CE WE D
OUT
H X High Z Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L High Z Write Active (ICC)
Mode Power
Ordering Information
Speed
(ns) Ordering Code
15 CY7C107BN-15VC 51-85032 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007BN-15VC 51-85031 28-Lead (300-Mil) Molded SOJ
CY7C1007BN-15VXC 51-85031 28-Lead (300-Mil) Molded SOJ (Pb-free)
CY7C107BN-15VI 51-8 5032 28-Lead (400-Mil) Molded SOJ Industrial
Please contact local sales representative regarding availability of these parts
Package
Diagram Package Type
Operating
Range
Document #: 001-06426 Rev. ** Page 5 of 7
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Package Diagrams
28-Lead (400-Mil) Molded SOJ (51-85032)
PIN 1 I.D
114
CY7C107BN
CY7C1007BN
.435
.445
.395
.405
15 28
.720
.730
.128
.148
.050
TYP.
.026
.032
.025 MIN.
.015
.020
28-Lead (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
3. DIMENSIONS IN INCHES
MIN.
MAX.
PIN 1 ID
114
SEATING PLANE
0.004
DIMENSIONS IN INCHES
.360
.380
DETAIL
EXTERNAL LEAD DESIGN
A
51-85032.*B
51-85032-*B
MIN.
MAX.
.007
.013
15 28
0.697
0.713
0.050
TYP.
A
All product or company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06426 Rev. ** Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch an ge without notice. Cypress Semiconductor Corporation assumes no resp onsibility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
0.291
0.300
0.025 MIN.
0.120
0.140
0.330
0.350
SEATING PLANE
0.004
0.013
0.019
OPTION 1 OPTION 2
0.007
0.013
0.262
0.272
0.026
0.032
0.014
0.020
51-85031-*C
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Document History Page
Document Title: CY7C107BN/CY7C1007BN 1M x 1 Static RAM
Document Number: 001-06426
REV. ECN NO.
** 423847 See ECN NXR New Data Sheet
Issue
Date
Orig. of
Change Description of Change
CY7C107BN
CY7C1007BN
Document #: 001-06426 Rev. ** Page 7 of 7
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