07B
CY7C107B
CY7C1007B
1M x 1 Static RAM
Features
• High speed
—t
= 12 ns
AA
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
automatic power-down feature that reduces power consumption by more than 65% when deselected.
) and thre e-state driver s. These devices have an
Writing to the devices is accomplished by taking Chip Enable
) and Write Enab le (WE) inputs LOW . Da ta on the input pi n
(CE
) is written into the memory location specified on the ad-
(D
IN
dress pins (A
through A19).
0
Reading from the devices is accomp lishe d by takin g Chip Enable (CE
) LOW while Writ e Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified by the address pi ns will appea r on t he data output ( D
pin.
The output pin (D
when the devic e is deselected (CE
operation (CE
and WE LOW).
) is placed in a high-impedance state
OUT
HIGH) or during a write
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
LogicBlockDiagram Pin Configuration
SOJ
A
A
A
A
A
A
NC
A
A
A
A
D
OUT
WE
GND
10
11
12
13
14
15
16
17
18
19
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
IN
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
512x2048
ARRA
COLUMN
DECODER
Y
D
OUT
SENSE AMPS
POWER
DOWN
CE
V
CC
A
9
A
8
A
7
A
6
A
5
A
4
NC
A
3
A
2
A
1
A
0
D
IN
CE
107B-2
OUT
)
9
A
A10A11A
13
A12A14A16A
15
A17A18A
19
Selection Guide
7C107B-12
7C1007B-12
Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05030 Rev. ** Revised September 7, 2001
WE
107B-1
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
90 80 75 70 60
2 2 2 2 2
[+] Feedback
CY7C107B
CY7C1007B
Maximum Ratings
(Above which the useful life may be impaired. For user guid elines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
Relative to GND
CC
.......................................−0.5 V to VCC + 0.5V
[1]
....................................−0.5V to VCC + 0.5V
[1]
.....−0.5V to +7.0V
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
OS
CC
SB1
SB2
Output HIGH
VCC = Min., IOH = −4.0 mA 2.4 2.4 2.4 V
Voltage
Output LOW
VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[1]
Input Load Current GND < VI < V
Output Leakage
Current
Output Short
Circuit Current
[3]
VCC Operating
Supply Current
Automatic CE
Power-Down
Current— TTL Inputs
Automatic CE
Power-Down
Current—
CMOS Inputs
GND < VI < VCC,
Output D isab led
VCC = Max., V
VCC = Max.,
= 0 mA,
I
OUT
= 1/t
f = f
MAX
Max. V
V
IN
f = f
Max. V
CE
V
IN
VIN < 0.3V, f = 0
, CE > VIH,
CC
>V
or VIN < VIL,
IH
MAX
,
CC
> VCC – 0.3V ,
> VCC – 0.3V or
CC
= GND −300 −300 −300 mA
OUT
RC
Current into Outputs (LOW)........................................ 20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Ambient
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
Min. Max. Min. Max. Min. Max. Unit
2.2 VCC+
0.3
2.2 VCC+
0.3
−0.3 0.8 −0.3 0.8 −0.3 0.8 V
−1+1−1+1−1+1µA
–5+5–5+5–5+5µA
90 80 75 mA
20 20 20 mA
222mA
[2]
7C107B-20
7C1007B-20
2.2 VCC+
0.3
V
CC
V
Notes:
(min.) = –2.0V for pulse durations of less than 20 ns.
1. V
IL
2. T
is the “Instant On” case temperature.
A
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05030 Rev. ** Page 2 of 9
[+] Feedback
Electrical Characteristics Over the Operating Range (continued)
CY7C107B
CY7C1007B
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH
VCC = Min., IOH = −4.0 mA 2.4 2.4 V
Voltage
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic CE
Power-Down
Current—TTL Inputs
Automatic CE
Power-Down
Current—CMOS Inputs
[4]
[1]
CC
GND < VI < VCC,
Output Disabled
[3]
VCC = Max., V
OUT
VCC = Max.,
= 0 mA,
I
OUT
= 1/t
f = f
MAX
RC
Max. VCC, CE > VIH,
>VIH or VIN < VIL,
V
IN
f = f
MAX
Max. V
CE
V
IN
V
IN
,
CC
> VCC – 0.3V ,
> VCC – 0.3V or
< 0.3V , f = 0
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Min. Max. Min. Max. Unit
+ 0.3 2.2 V
CC
+ 0.3 V
CC
−0.3 0.8 −0.3 0.8 V
−1+1−1+1µA
−5+5−5+5µA
= GND −300 −300 mA
70 60 mA
20 20 mA
22mA
Parameter Description Test Conditions Max. Unit
: Addr e sses Input Capacitance TA = 25°C, f = 1 MHz,
C
IN
CIN: Controls 10 pF
C
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Output Capacitance 10 pF
V
CC
= 5.0V
7pF
Document #: 38-05030 Rev. ** Page 3 of 9
[+] Feedback
AC Test Loads and Waveforms
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalentto: THÉ VENIN EQUIVALENT
OUTPUT 1.73V
R1 480
OUTPUT
R2
255Ω
INCLUDING
(a) (b)
167Ω
5V
5pF
JIG AND
SCOPE
R1 480Ω
R2
255Ω
107-3
3.0V
GND
≤ 3
10%
ns
CY7C107B
CY7C1007B
ALL INPUT PULSES
90%
90%
10%
107-4
≤ 3
ns
Switching Characteristics
[5]
Over the Operating Range
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and out p ut lo ad i n g of t h e s p eci f ie d
I
OL/IOH
6. At any given temperature and voltage condition, t
7. t
HZCE
8. The internal write time of the memory is defined by the overlap of CE
signals can terminate the write . The input data set-up and hold timing shoul d be referenced to the leading edge of the sign al that terminates the wr ite.
Read Cycle Time 12 15 20 25 35 ns
Address to Data Valid 12 15 20 25 35 ns
Data Hold from Address
33333ns
Change
CE LOW to Data Valid 12 15 20 25 35 ns
CE LOW to Low Z
CE HIGH to High Z
[6]
[6, 7]
33333ns
6781010ns
CE LOW to Power-Up 0 0 0 0 0 ns
CE HIGH to Power-Down 12 15 20 25 35 ns
[8]
Write Cycle Time 12 15 20 25 35 ns
CE LOW to Write End 10 12 15 20 25 ns
Address Set-Up to Write
10 12 15 20 25 ns
End
Address Hold from Write
00000ns
End
Address Set-Up to Write
00000ns
Start
WE Pulse Width 10 12 15 20 25 ns
Data Set-Up to Write End 7 8 10 15 20 ns
Data Hold from Write End 0 0 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
and 30-pF load capacitance.
and t
are specified with a lo ad cap acitance of 5 pF as in pa rt (b) of AC Test Loads. Trans ition i s measur ed ±500 mV from steady-state volt age.
HZWE
[6]
[6, 7]
33333ns
6781010ns
is less than t
HZCE
and t
LZCE
LOW and WE LOW. CE and WE must be LOW to initiate a write, an d the transition of any of these
HZWE
is less than t
for any given d evice.
LZWE
Document #: 38-05030 Rev. ** Page 4 of 9
[+] Feedback
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
Read Cycle No. 2
ADDRESS
CE
[10, 11]
PREVIOUS DATA VALID DATA VALID
[11, 12]
t
OHA
CY7C107B
CY7C1007B
t
RC
t
AA
107-6
t
RC
t
LZCE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
PU
CURRENT
Write Cycle No. 1 (CE Controlled)
ADDRESS
CE
WE
DATA IN
t
ACE
t
HZCE
DATA VALID
t
PD
50%
[13]
t
WC
t
SA
t
AW
t
PWE
t
SCE
t
t
SD
t
HD
50%
HA
HIGH
IMPEDANCE
I
CC
I
SB
107-7
DATA VALID
DATA OUT
Notes:
9. No input may exceed V
10. Device is continuously selected, CE
11. WE
is HIGH for read cycle .
12. Address valid prior to or coi ncident with CE
HIGH IMPEDANCE
+ 0.5V .
CC
= VIL.
transition LOW.
Document #: 38-05030 Rev. ** Page 5 of 9
107-8
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled)
ADDRESS
CE
[13]
CY7C107B
CY7C1007B
t
WC
t
SCE
DATA IN
DATA OUT
Note:
13. If C E
t
t
SA
WE
DATA UNDEFINED
goes HIGH simultaneousl y with WE going HIGH, the o utput remai ns in a hig h-impedanc e stat e.
AW
t
HZWE
t
PWE
t
SD
DATA VALID
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
107-9
Document #: 38-05030 Rev. ** Page 6 of 9
[+] Feedback
Truth Table
CY7C107B
CY7C1007B
CE WE D
H X High Z Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L High Z Write Active (ICC)
OUT
Mode Power
Ordering Information
Speed
(ns) Ordering Code
12 CY7C107B-12VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-12VC V28 28-Lead (300-Mil) Molded SOJ Commercial
15 CY7C107B-15VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-15VC V28 28-Lead (300-Mil) Molded SOJ Commercial
15 CY7C107B-15VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C1007B-15VI V28 28-Lead (300-Mil) Molded SOJ Industrial
20 CY7C107B-20VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-20VC V28 28-Lead (300-Mil) Molded SOJ Commercial
25 CY7C107B-25VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-25VC V28 28-Lead (300-Mil) Molded SOJ Commercial
Contact factory for “L” version availability.
Package Diagrams
Package
Name Package Type
28-Lead (400-Mil) Molded SOJ V28
Operating
Range
Document #: 38-05030 Rev. ** Page 7 of 9
51-85032-A
[+] Feedback
ng so indemnifies Cypress Semiconductor against all charges.
28-Lead (300-Mil) Molded SOJ V21
CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
[+] Feedback
Document Title: CY7C107B/CY7C1007B 1M x 1 Static RAM
Document Number: 38-05030
REV. ECN NO.
** 109950 12/02/01 SZV Change from Spec number: 38-01116 to 38-05030
Issue
Date
Orig. of
Change Description of Change
CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 9 of 9
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