Datasheet CY7C0430V-133BGC, CY7C0430V-100BGI, CY7C0430V-100BGC Datasheet (Cypress Semiconductor)

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30V

PRELIMINARY

Synchronous QuadPort™ Static RAM

Features

• True four-ported memory cells which allow simultaneous access of the same memory location

• Synchronous Pipelined device

—64K x 18 organization

• Pipelined output mode allows fast 133-MHz operation

• High Bandwidth up to 10 Gb ps (133 MHz x 1 8 bits wi de x 4 ports)

• 0.25-micron CMOS for optimum speed/power

• High-speed clock to data access 4.7 ns (max.)

• 3.3V Low operating power

—Active = 750mA (maximum) —Standby = 1mA (maximum)

Top Level Logic Block Diagram

Port 1 Operation-Control Logic Blocks

R/W

0P1

1P1

CLK

[1]

Port-1

Control

Logic

CY7C0430V

3.3V 64K x 18

• Counter wrap-ar ound cont r ol —Internal mask register co ntrols counter wrap-ar ound

—Counter-Interrupt flags to indicate wrap-around

• Counter readback on address lines

• Mask register readback on address lines

• Interrupt flags for message passin g

• Master reset for all ports

• Width and depth expansion capabi litie s

• Dual Chip Enabl es on all ports for easy depth expans ion

• Separate upper-byte and lower-byte controls on all

ports

• 272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)

• Commercial and Industrial temperature ranges

• IEEE 1149.1 JTAG boundary scan

• BIST (Built In Self Test) controller

MRST

TMS TCK

TDI

CLKBIST

Reset

Logic

JTAG

Controller

BIST

TDO

I/O

0P1

- I/O

17P1

CLK

0P1–A15P1

MKLD

CNTLD

CNTINC

CNTRD

MKRD

CNTRST

CNTINT

INT

P1 P1

P1 P1 P1 P1

Mask Reg/

Port 1

I/O

Port 1

Counter/

Address

Decode

Port 2 Logic Blocks

Notes:

1. Port 1 Control Logic Block is detailed on page 2.

2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

For the most recent information, visi t the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Port 1

RAM

Array

Port 2 Port 3

[2]

Port 4 Logic Blocks

Port 4

Port 3 Logic Blocks

[2]

November 18, 199 9

PRELIMINAR Y

Port 1 Operation-Contr ol Logic Block Dia gr am:

(Address Readback is independent of CEs)

R/W

CE CE

0P1 1P1

W R

CY7C0430V

MRST

0P1–A15P1

CNTRD

MKRD MKLD

CNTINC

CNTLD

CNTRST

CLK

MRST

CNTINT

P1 P1

Priority

Decision

Logic

I/O

9P1

0P1

–I/O

17P1

8P1

Addr. Read Back

Port 1

Readback Register

Port 1

Mask Register

Port 1

Counter/

Address Register

R/W

0P1

1P1

CLK

MRST

P1 P1

Port-1

I/O

Control

Port 1

Address Decode

Port 1

Interrupt

Logic

Port

INT

RAM

Array

ort

PRELIMINAR Y

CY7C0430V

Functional Description

The CY7C0430V is a 1-Mb synchronous true four-port Static RAM. This is a high-speed, low-power 3.3V CMOS dual-port static RAM. Four ports are provided, permitting independent, simultaneous ac cess f or reads from any location in memory. A particular port can write to a certain location while other p orts are reading that location simultaneously. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address and data lines allow for minimal set-up and hold time.

Data is registered for decreased cycle time. Clock to data valid

= 4.7 ns. Each port contains a burst counter on the input

CD2

address register. After externally loading the counter with the initial address the counter will self-increment the address internally (more details to foll o w ). Th e inte rnal write pulse width is independent of the duration of the R/W internal write pulse is self-tim ed to all o w the sho rtest possible cycle times.

A HIGH on CE down the internal circuitry to reduce the static power consumption. One cycle is req uired w ith c hip en ab les asserted to reac tivate the outputs.

Counter enable inpu ts are provided to stall the operat ion of the address input and utiliz e the internal addres s generated b y the

or LOW on C E1 for one clo ck cycle wi ll power

input signal. The

inter nal counter for fast interleaved mem ory application s. A port's burst counter is loaded with an external address when the port's Counter Load pin (CNTLD the port's Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-toHIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTINC memory array and will loop back to the start. Counter Reset (CNTRST register is used to control the counter wrap. The counter and mask register operations are described in more details in the following sections.

The counter or mask register values can be read back on the bidirectional address lines by activating MKRD spectively.

The new features added to th e QuadPort™ standard synchronous dual-ports include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, readback of mask register value on address lines, interrupt flags for messag e passing, BIST, JT A G for boundary scan, and asynchronous Maste r Reset.

is deasserted. The counter can address the entire

) is used to reset the burst counter. A counter-mask

) is asserted LOW. When

or CNTRD re-

as compared t o

Pin Configuration

1234567891011121314151617181920

I/O17P2I/O15P2I/O13P2I/O11P2I/O9P2I/O16P1I/O14P1I/O12P1I/O10P1I/O10P4I/O12P4I/O14P4I/O16P4I/O9P3I/O11P3I/O13P3I/O15P3I/O17P3 LB

PRELIMINAR Y

272-Ball Grid Array (BGA)

Top View

CY7C0430V

VDD1 UB

A14P1A15P1CE1P1CE0

VSS1 A12P1A13P1 OE

A10P1A11P1MKRD

A7P1A8P1A9P1CNTINT

VSS1 A5P1A6P1CNTINC

A3P1A4P1MKLD

VDD1 A1P1A2P1VDD GND

A0P1INT

A0P2INT

VDD1 A1P2A2P2CLK

A3P2A4P2MKLD

VSS1 A5P2A6P2CNTINC

I/O16P2I/O14P2I/O12P2I/O10P2I/O17P1I/O13P1I/O11P1TMS TDI I/O11P4I/O13P4I/O17P4I/O10P3I/O12P3I/O14P3I/O16P3UBP4VDD1

R/WP1I/O15P1VSS2 VSS2 I/O9P1 TCK TDO I/O9P4VSS2 VSS2 I/O15P4R/WP4CE0P4CE1P4A15P4A14

VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP4A13P4A12P4VSS1

CNTRD

CNTLD

CNTRSTP1CLK

CNTRSTP2 VSS

CNTLD

GND

MKRDP4A11P4A10

CNTRD

CNTINT

P4A9P4A8P4

CNTINC

P4A6P4A5P4

MKLDP4A4P4A3

CNTLD

[3]

GND

[3]

GND

[3]

GND

[3]

GND

[3]

GND

[3]

GND

[3]

GND

[3]

GND

VDD A2P4A1P4VDD1

CLKP4CNTRST

VSS CNTRST

CLKP3A2P3A1P3VDD1

MKLDP3A4P3A3

CNTLD

CNTINC

P3A6P3A5P3

VSS1

INTP4 A0

INTP3 A0

VSS1

A7 P4

A7P2A8P2A9P2CNTINT

A10P2A11P2MKRD

VSS1 A12P2A13P2 OE

A14P2A15P2CE1P2 CE0

VDD1 UB

I/O8P1I/O6P1I/O4P1I/O2P1I/O0P11/O7P2I/O5P2I/O3P2I/O1P2I/O1P3I/O3P3I/O5P3I/O7P3I/O0P4I/O2P4I/O4P4I/O6P4I/O8P4LB

LB P2

CNTRD

VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP3A13P3A12P3VSS1

R/WP2I/O6P2VSS2 VSS2 I/O0P2NC NC I/O0P3VSS2 VSS2 I/O6P3R/WP3CE0P3CE1P3A15P3A14

I/O7P1I/O5P1I/O3P1I/O1P1I/O8P2I/O4P2I/O2P2MRST

Note:

3. Central Leads are for thermal dissipation only. They are connected to device V

CNTINT

P3A9P3A8P3

MKRDP3A11P3A10

CNTRD

CLKBIST I/O2P3I/O4P3I/O8P3I/O1P4I/O3P4I/O5P4I/O7P4UB

A7 P3

VDD1

PRELIMINAR Y

CY7C0430V

Selection Guide

CY7C0430V

-133

(MHz) 133 100

MAX2

Max Access Time (ns) (Clock to Data) 4.7 5.0 Max Operating Current I Max Standby Current for I Max Standby Current for I

(mA) 750 600

(mA) (All ports TTL Level) 200 150

SB1

(mA) (All ports CMOS Level) 1.0 1.0

SB3

CY7C0430V

-100

Pin Definitions

Port 1 Port 2 Port 3 Port 4 Description

0P1–A15P1

I/O

–I/O

0P1

CLK

,CE

0P1

R/W

MRST Master Reset Input. Thi s is one signal for All P orts. MRST

CNTRST

MKLD

CNTLD

CNTINC

17P1

1P1

0P2–A15P2

I/O

–I/O

0P2

CLK

,CE

0P2

R/W

CNTRST

MKLD

CNTLD

CNTINC

17P2

1P2

0P3–A15P3

I/O

–I/O

0P3

CLK

,CE

0P3

R/W

CNTRST

MKLD

CNTLD

CNTINC

17P3

1P3

0P4–A15P4

I/O

–I/O

0P4

CLK

,CE

0P4

R/W

CNTRST

MKLD

CNTLD

CNTINC

Address Input/Output. Data Bus Input/Output.

17P4

Clock Input. This input can be free running or strobed. Maximum cloc k input ra te is f

MAX

Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. For read operations bo th the LB

and OE signals mu st be asserted to drive output data on the lower byte of the d ata pins.

Upper Byte Select Input. Same funct ion as LB, b ut to the upper byte.

Chip Enable Input. T o select any port, both CE0 AND CE1

1P4

must be asserted to their active states (CE0 ≤ VIL and

≥ VIH).

Output Enable Input. This sig nal mus t be asserted LOW to enable the I/O data lines during read operations. OE is asynchronous input.

Read/Write Enable Input. This sig nal is asserted LO W to write to the dual port memory array . For read oper ations, assert this pin HIGH.

is an asynchronous input. Asserting MRST forms all of the reset functi ons as described in the te xt. A

operation is required at power-up.

MRST Counter Reset Input. Asserting this signal LOW resets

the burst address counter of its respective port to zero. CNTRST

is second to MRST in priority with respect to

counter and mask register operations. Mask Register Load input. Asserting this signal LOW

loads the mask register with the external address available on the address lines. MKLD priority over CNTLD

operation.

operation has higher

Counter Load Inpu t. Asserting this si gnal LO W loads th e burst counter with the external address present on the address pins.

Counter Increment Input. Asserting this signal LOW increments the b urst address counter of its respective port on each rising edge of CLK.

LOW per-

PRELIMINAR Y

CY7C0430V

Pin Definitions

(continued)

Port 1 Port 2 Port 3 Port 4 Description

CNTRD

Counter Readbac k Input. When asserted LOW, the internal address val ue of the counter wil l be read back on the address lines. During CNTRD and CNTINC

must be HIGH. Count er readback operati on

operation, both CNTLD

has higher priority over mask register readback operation. Counter readback operation is ind epe nde nt o f port chip enables . If addres s readb ac k op erati on oc curs w ith

= LOW , CE1 = HIGH), the data

from the

CD2

MKRD

chip enables activ e (CE lines (I/Os) will be three-stat ed. The readbac k timing will be valid after one no-operation cycle plus t rising edge of the next cycle.

Mask Register Readback Input. When asserted LOW, the value of the mask register will be readback on address lines. During mask register readback operation, all counter and MKLD

inputs must be HIGH (see Counter and Mask Register Oper ations truth table). Mask re gister readback op erati on is indepe ndent o f po rt chip enab les . If address readback operation occurs with chip enables

= LOW, CE1 = HIGH), the data lines (I/Os)

from the rising edge of the

CD2

CNTINT

active (CE will be three-stated. The read bac k will be v al id after o ne no-operation cycle plus t next cycle.

Counter Interrupt flag output. Flag is asserted LOW for one clock cycle when the counter wraps around to location zero.

INT

Interrupt flag output. Interrupt permits communications between all f o ur ports. The upp er f our mem ory locations can be used for m essage passing. Example of operation:

is asserted LOW when another port writes to the

INT

mailbox location of Port 4. Flag is cleared when Port 4 reads the contents of its mailbox. The same operation is applicable to Ports 1, 2, and 3.

TMS JTAG Test Mode Select Input. It contr ols th e a dvance of

JTAG TAP state machine. State machine transitions occur on the rising edge of TCK.

TCK JT AG Test Clock Input. This can be CLK of any port or an

external clock connected to the JTAG TAP.

TDI JTAG Test Data Input. This is the only data input. TDI

inputs will shift data serially in to the selected register.

TDO JT AG Test Data Output. This is the only data output. TDO

transitions occur on the falling edge of TCK. TDO normally three-stated except when captured data is shifted out of the JTAG TAP.

CLKBIST BIST Clock Input. GND Thermal ground for heat dissipation. V V V V V V

SS DD SS1 DD1 SS2 DD2

Ground Input. Power Input. Address lines ground Input. Address lines power Input. Data lines ground Input. Data lines power Input.

PRELIMINAR Y

CY7C0430V

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

1-4

MAX

° °

≥

C to + 150°C

C to + 125°C

+0.5V

Indust. 413 750 330 600 mA

Com’l. mA

Indust. 80 200 60 150 mA

Com’l. mA

Indust. 170 349 128 263 mA

Com’l. mA

Indust. 0.5 1 0.5 1 mA

Com’l.

Indust. 110 200 83 151 mA

Com’l. mA

Storage Temperature................................ –65

Ambient Temperature with

Power Applied............................................–55

Supply Voltage to Ground Potential..............–0.5V to + 4.6V

DC Voltage Applied to

Outputs in High Z State............................–0.5V to V

Electrical Characteristics

Over the Operating Range

Parameter Description

V V I

SB1

SB2

SB3

SB4

IH IL

Output HIGH Voltage (V

= Min., I

= –4.0 mA)

Output LOW Voltage (V

= Min., I

= +4.0 mA)

Input HIGH Voltage 2.0 2.0 V Input LOW Voltage 0.8 0.8 V Output Leakage Current –10 10 –10 10 Operating Current (V

= 0 mA) Outputs Disabled

OUT

= Max.,

Standby Current (4 Ports toggling at TTL Levels ,0 active) CE

, f = f

MAX

Standby Current (4 Ports toggling at TTL Levels , 1 active) | CE3 | CE

VIH, f = f

CE1 | CE2

MAX

Standby Current (4 Ports CMOS Level, 0 active) CE

1-4

≥

VIH, f = 0

Standby Current (3 Ports CMOS Level, 1 Port TTL active) CE

| CE3 | CE

VIH, f = f

DC Input Voltage .....................................–0.5V to V

Output Current into Outputs (LO W).............................20 mA

Static Discharge Voltage ...........................................>2001V

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V ± 150 mV Industrial –40

CY7C0430V

-133 -100

Min. Typ Max Min. Typ Max

2.4 2.4 V

0.4 0.4 V

Ambient

Temperature V

C to +85°C 3.3V ± 150 mV

+0.5V

Unit

JTAG TAP Electrical Characteristics

Over the Operati ng Rang e

Parameter Description Test Conditions Min. Max. Unit

V V V V I

OH1 OL1 IH IL

Output HIGH Voltage I

= −4.0 mA 2.4 V

Output LOW Voltage IOL = 4.0 mA 0.4 V Input HIGH Voltage 2.0 V Input LOW Voltage 0.8 V Input Leakage Current GND ≤ VI ≤ V

–100 100

Capacitance

Parameter Description Test Conditions Max. Unit

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

= 3.3V

Output Capacitance 8 pF

8 pF

AC Test Load

Z0 = 50

OUTPUT

PRELIMINAR Y

Ω

[4]

R = 50

Ω

OUTPUT

Z0 = 50

5 pF

Ω

R = 50

Ω

CY7C0430V

(a) Normal Load

TDO

Note:

4. Test Conditions: C = 10 pF.

=50

VTH=1.5V

(b) Three-State Delay

1.5V

Ω

GND

C= 10 pF

3.0V

GND

10%

90%

10%

ALL INPUT PULSES

PRELIMINAR Y

CY7C0430V

Switching Characteristics

Over the Industrial Operating Range

Parameter Description

MAX2

CYC2

CH2

CL2

SCLD

HCLD

SCINC

HCINC

SCRST

HCRST

SCRD

HCRD

SMLD

HMLD

SMRD

HMRD

OLZ

OHZ

CD2

CA2

CM2

CKHZ

CKLZ

SINT

RINT

SCINT

RCINT

[5]

[6]

Maximum Frequency 133 100 MHz Clock Cycle Time 7.5 10 ns Clock HIGH Time 3 4 ns Clock LO W Tim e 3 4 ns Clock Rise Time 2 3 ns Clock Fall Time 2 3 ns Address Set-up Time 2.5 3 ns Address Hold Time 0.5 0.5 ns Chip Enable Set-up Time 2.5 3 ns Chip Enable Hold Time 0.5 0.5 ns R/W Set-up Time 2.5 3 ns R/W Hold Time 0.5 0.5 ns Input Data Set-up Time 2.5 3 ns Input Data Hold Time 0.5 0.5 ns Byte Set-up Time 2.5 3 ns Byte Hold Time 0.5 0.5 ns CNTLD Set-up Time 2.5 3 ns CNTLD Hold Time 0.5 0.5 ns CNTINC Set-up Time 2.5 3 ns CNTINC Hold Time 0.5 0.5 ns CNTRST Set-up Time 2.5 3 ns CNTRST Hold Time 0.5 0.5 ns CNTRD Set-up Time 2.5 3 ns CNTRD Hold Time 0.5 0.5 ns MKLD Set-up Time 2.5 3 ns MKLD Hold Time 0.5 0.5 ns MKRD Set-up Time 2.5 3 ns MKRD Hold Time 0.5 0.5 ns Output Enable to Data Valid 6.5 8 ns OE to LOW Z 1 1 ns OE to HIGH Z 1 6 1 7 ns Clock to Data Valid 4.7 5 ns Clock to Counter Address Readback Valid 4.7 5 ns Clock to Mask Register readback Valid 4.7 5 ns Data Output Hold After Clock HIGH 1 1 ns Clock HIGH to Output High Z 1 4.8 1 6.8 ns Clock HIGH to Output LOW Z 1 1 ns Clock to INT Set Time 1 6.5 1 8 ns Clock to INT Reset Time 1 6.5 1 8 ns Clock to CNTINT Set Time 1 6.5 1 8 ns Clock to CNTINT Reset Time 1 6.5 1 8 ns

CY7C0430V

–133 –100

Min. Max. Min. Max.

Unit

PRELIMINAR Y

CY7C0430V

Switching Characteristics

Over the Industrial Operating Range (contin ue d)

Parameter Description

Master Reset Timing

RSS

RSR

RSF

RScntint

Master Reset Pulse Width 7.5 10 ns Master Reset Set-up Time 6.0 8.5 ns Master Reset Recovery Time 7.5 10 ns Master Reset to Interrupt Flag Reset Time 6.5 8 ns Master Reset to Counter Interrupt Flag Reset Time 6.5 8

Port to Port Delays

CCS

Notes:

5. This parameter is guaranteed by design, but it is not production tested.

6. Valid for both address and data outputs.

Clock to Clock Set-up Time 6.5 9 ns

CY7C0430V

–133 –100

Min. Max. Min. Max.

Unit

PRELIMINAR Y

JTAG Timing and Switching W aveforms

Parameter Description

JTAG

TCYC

TMSS

TMSH

TDIS

TDIH

TDOV

TDOX

Maximum JTAG TAP Controller Frequency 10 10 MHz TCK Clock Cycle Time 100 100 ns TCK Clock High Time 40 40 ns TCK Clock Low Time 40 40 ns TMS Setup to TCK Clock Rise 10 10 ns TMS Hold After TCK Clock Rise 10 10 ns TDI Setup to TCK Clock Rise 10 10 ns TDI Hold after TCK Clock Rise 10 10 ns TCK Clock Low to TDO Valid 20 20 ns TCK Clock Low to TDO Invalid 0 0 ns

CY7C0430V

–133 –100

Min. Max. Min. Max.

Unit

Test Clock TCK

Test Mode Select TMS

Test Data-In TDI

Test Data-Out TDO

TMSS

TDIS

TDOX

TMSH

TDIH

TDOV

TCYC

Switching Waveforms

Master Reset

MRST

ALL ADDRESS/ DATA LINES

ALL OTHER INPUTS

TMS

CNTINT

INT

TDO

RSS

RSF

INACTIVE

PRELIMINAR Y

RSR

ACTIVE

CY7C0430V

Read Cycle

ADDRESS

DATA

[7, 8, 9, 10, 11]

CLK

R/W

t t

OUT

SW SA

CYC2

CH2

1 Latency

CKLZ

CL2

n+1

CD2

n+2

n+1

OHZ

n+3

n+2

OLZ

Notes:

is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.

7. OE

8. CNTLD

9. The output is disabled (high-impedance state) by CE

10. Addresses do not have to be accessed sequentially. Note 8 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference

11. CE

= VIL, MKLD= VIH, CNTINC = x, and MRST=CNTRST = VIH.

only.

is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH.

=VIH following the next rising edge of the clock.

PRELIMINAR Y

CY7C0430V

Switching Waveforms

[12, 13]

Bank Select Read

CLK

ADDRESS

DATA

ADDRESS

DATA

(B1)

OUT(B1)

(B2)

OUT(B2)

(continued)

CYC2

CH2

CL2

CD2

CKHZ

CD2

CKLZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CYC2

[14, 15, 16, 17]

CL2

Read-to-Write-to-Read (OE = VIL)

CH2

CLK

R/W

n+1

CD2

n+2

CKHZ

tSDt

n+2

n+3

CKLZ

n+4

CD2

n+3

ADDRESS

DATA

OUT

NO OPERATION WRITEREAD READ

Notes:

12. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress Quadport device from this data sheet. ADDRESS

13. LB = UB = OE = CNTLD = VIL; MRST= CNTRST= MKLD = VIH.

14. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.

15. LB

= UB = CNTLD = VIL; MRST= CNTRST= MKLD =VIH.

16. Addresses do not have to be accessed sequentially since CNTLD= VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only.

17. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

= ADDRESS

(B1)

(B2)

PRELIMINAR Y

CY7C0430V

Switching Waveforms

Read-to-Write-to-Read (OE

CH2

CLK

R/W

ADDRESS

DATA

OUT

(continued)

Controlled)

CYC2

CL2

[14, 15, 16, 17]

n+1

CD2

OHZ

n+2

tSDt

n+2

n+3

n+4

CKLZ

n+5

CD2

n+4

READ READWRITE

Read with Address Counter Advance

CYC2

CH2

CL2

[18, 19]

CLK

ADDRESS

SCLD

HCLD

CNTLD

SCINC

CNTINC

CD2

DATA

OUT

x–1

EXTERNAL

READ

READ WITH COUNTER

ADDRESS

Notes:

18. CE

19. The “Internal Address” is equal to the “Ext ernal Address” when CNTLD

= OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.

HCINC

= VIL.

n+1

COUNTER HOLD

n+2

READ WITH COUNTER

n+3

PRELIMINAR Y

CY7C0430V

Switching Waveforms

(continued)

Write with Address Counter Advance

CYC2

CLK

ADDRESS

INTERNAL

ADDRESS

CNTLD

CNTINC

DATA

CH2

SAD

SCN

WRITE EXTERN A L

ADDRESS

HAD

HCN

CL2

[19, 20]

n+1

WRITE WITH

COUNTER

n+1

WRITE COUNTER

HOLD

n+2

n+3

n+4

WRITE WITH COUNTER

Note:

= LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = V

20. CE

IH.

PRELIMINAR Y

CY7C0430V

Switching Waveforms

SCRST

[16, 21, 22]

CH2

HCRST

Counter Reset

CLK

ADDRESS

INTERNAL

ADDRESS

R/W

CNTLD

CNTINC

CNTRST

DATA

(continued)

CYC2

CL2

tSWt

SDtHD

SAtHA

SCLD

HCLD

n+1

DATA

OUT

COUNTER

RESET

Notes:

= LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH.

21. CE

22. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

PRELIMINAR Y

CY7C0430V

Switching Waveforms

(continued)

Load and Read Address Counter

CYC2

CLK

A0-A15

CNTLD

CNTINC

CNTRD

INTERNAL

ADDRESS

DATA

OUT

SCLD

x–1

CH2

EXTERNAL

ADDRESS

HCLD

LOAD

CL2

SCINC

[23]

HCINC

CD2

READ DATA WITH COUNTER

n+1

Note 24

CKLZ

SCRD

n+2

n+1

HCRD

n+2

CA2

CKHZ

Note 25

n+2

[26]

CKLZ

CKHZ

n+2

READ INTERNAL ADDRESS

Notes:

= OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH.

23. CE

24. Address in output mode. Host must not be driving address bus after time t

25. Address in input mode. Host can drive address bus after t

26. This is the value of the address counter being read out on the address lines.

CKHZ

in next clock cycle.

CKLZ

PRELIMINAR Y

CY7C0430V

Switching Waveforms

Load and Read Mask Register

CH2

(continued)

[27]

CYC2

CL2

CLK

HMLD

A0-A15

SMLD

MKLD

MKRD

MASK INTERNAL

VALUE

LOAD

MASK REGISTER

VALUE

Notes:

= OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH.

27. CE

28. This is the value of the Mask Register read out on the address lines.

SMRD

Note 24

CKLZ

HMRD

READ

MASK-REGISTER

CA2

Note 25

CKHZ

[28]

n+2

VALUE

PRELIMINAR Y

CY7C0430V

Switching Waveforms

Port 1 Write to Port 2 Read

CH2

CLK

PORT-1 ADDRESS

R/W

CKHZ

PORT-1

DATA

CYC2

CLK

PORT-2 ADDRESS

R/W

CH2

(continued)

[29, 30, 31]

CYC2

CL2

CCS

CKLZ

CD2

PORT-2

DATA

OUT

Notes:

= OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH.

29. CE

30. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If t data will be read out.

31. If t

< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*t

CCS

minimum specified value, then Port 2 will read the most recent data (written by Port 1) (t

CYC2

+ t

CYC2

) after the rising edge of Port 2's clock.

CD2

) after the ris ing ed ge o f P o rt 2's cl ock . If t

CD2

is violated , indet erminate

CCS

PRELIMINAR Y

CY7C0430V

Switching Waveforms

Counter Interrupt

CLK

EXTERNAL

ADDRESS

SMLD

MKLD

CNTLD

CNTINC

COUNTER

INTERNAL

ADDRESS

CNTINT

[32, 33, 34]

007Fh

CH2

(continued)

CYC2

CL2

xx7Dh

HMLD

SCLD

HCLD

SCINC

xx7Dh

HCINC

xx7Eh

xx7Fh

SCINT

xx00h

RCINT

Mailbox Interrupt Timing

CLK

PORT-1 ADDRESS

INT

CLK

PORT-2 ADDRESS

Notes:

= OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.

32. CE

33. CNTINT

34. CNTINC

35. CE

36. Address “FFFE” is the mailbox location for Port 2.

37. Port 1 is configured for Write operation, and Port 2 is configured for Read operation.

38. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.

39. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.

is always driven.

goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “don’t care.”

= OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.

[35, 36, 37, 38, 39]

CYC2

CH2

CYC2

CH2

CL2

SAtHA

FFFE

CL2

SAtHA

SINT

m+1

n+1

RINT

FFFE

n+2

m+3

n+3

m+4

PRELIMINAR Y

CY7C0430V

Table 1. Read/Write and Enable Operation

(Any Port)

[40, 41, 42]

Inputs Outputs

–

OE CLK CE

R/W I/O

I/O

Operation

X H X X High-Z Deselected X X L X High-Z Deselected X L H L D L L H H D

OUT

Write Read

H X L H X High-Z Outputs Disabled

Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)

[40, 43, 44]

CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation

X L X X X X X X Master-

Reset

Counter/Address Register Reset and Mask Register Set (resets entire chip as per reset state table)

H L X X X X X Reset Counter/Address Register Reset H H L X X X X Load Load of Address Lines into Mask Register H H H L X X X Load Load of Address Lines into Counter/Address

H H H H L X X Incre-

Counter Increment

ment

H H H H H L X Read-

Readback Counter on Address Lines

back

H H H H H H L Read-

Readback Mask Register on Address Lines

back

H H H H H H H Hold Counter Hold

Notes:

40. “X” = “don’t care,” “H” = V is an asynchronous input signal.

41. OE

42. When CE changes state, deselection and read happen after one cycle of latency.

= OE = VIL; CE1 = R/W = VIH.

43. CE

44. Counter operation and mask register operation is independent of Chip Enables.

, “L” = VIL.

PRELIMINAR Y

CY7C0430V

Master Reset

for P ort 1, FFFE is the mai lbo x f or Port 2, FFFD is the mailbox

for Port 3, and FFFC is the mailbox for Port 4. Ta ble 3 sh ows The QuadPort undergoes a complete reset by taking its Master Reset (MRST

) input LOW. The Master Reset input can switch asynchronousl y to the cloc ks. A Mast er Reset initiali zes the internal burst counters to zero, and the counter mask registers to all ones (co mpletely unmask ed). A Mas ter Rese t also forces the Mailbox Interrupt (INT rupt (CNTINT takes all registered control signals to a deselected read

[45]

state

) flags HIGH, resets the BIST controller, and

. A Master Reset must be performed on the QuadPort

) flags and the Counter Inter-

after power-up.

Interrupts

The upper four memory locations may be used for message passing and permit communications between ports. Ta b l e 3 shows the interrupt operation for all ports. For the 1-Meg QuadPort, the highest memory location FFFF is the mailbox

that in order to set Por t 1 INT to address FFFF will as se rt INT tion by Por t 1 will reset INT the other port’s mailb ox, the Interrupt flag (INT the mailbo x belongs to is as serted LOW. The Interrupt is reset when the own er (port) of the mai lbo x reads the cont ents of t he mailbox. The interrupt flag is set in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-through mode (i.e., it follows the clock edge of the reading port).

Each port can read the other port’s mailbox without resetting the interrupt. If an applica tion does not req uire message pas sing, INT pins should be treated as no-connect and should be left floating. at the same time INT

When two ports or more write to the same mailbo x

will be as serted but t he c onte nts of the

mailbox are not guaranteed to be valid.

flag, a write by any other port

LOW. A read of FFFF loca-

HIGH. When o n e port wr it es t o

) of the port that

Table 3. Interrupt Operation Example

Port 1 Port 2 Port 3 Port 4

Function A

Set Port 1 INT

Reset Port 1 INT

0P1–15P1

Flag X L FFFF X FFFF X FFFF X

Flag FFFF H X X X X X X

INT

0P2–15P2

INT

0P3–15P3

INT

0P4–15P4

Set Port 2 INTP2 Flag FFFE X X L FFFE X FFFE X Reset Port 2 IN TP2 Flag X X FFFE H X X X X

INT

Set Port 3 INT Reset Port 3 INT

Flag FFFD X FFFD X X L FFFD X

Flag X X X X FFFD H X X

Set Port 4 INTP4 Flag FFFC X FFFC X FFFC X X L Reset Port 4 IN TP4 Flag X X X X X X FFFC H

Note:

45. During Master Reset the control signals will be set to a deselected read state: CE CNTINCI

= VIH; CE1I = V

The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.

IL.

= LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI =

PRELIMINAR Y

CY7C0430V

Address Counter Control Operations

Counter enab le inputs are prov ided to stall the oper ation of the address input and utilize the in ternal address generat ed by the internal counter for the fast interleaved memory applications. A por t’s burst counter is loaded with the port’s Counter Load pin (CNTLD asserted, the address counter will incremen t on eac h LOW to HIGH transition of that port’s clock signal. This will rea d/wr ite one word from/into each successive address location until CNTINC the counter can addre ss the entire m emory arra y and will lo op back to start. Counter Reset (CNTRST Burst Cou nte r ( the M ask Registe r val ue i s unaf fect ed ). W he n using the counter in readba ck mode, the internal addres s value of the counter will be read back on the address lines when Counter Readbac k Sign al (C NTRD

). When the port’s Coun ter Increment (C NTINC) is

is deasserted. Depending o n the mask register state ,

) is used to reset the

) is asserted. Figure 1 pro-

Read back

Mask

Bidirectional Address Lines

CNTRD

MKRD

MKLD

= 1

vides a block diagram of the readback operation. Table 2 lists control signals req uired for cou nter operations . The signals are listed based on their priority. For example, master reset takes precedence over counter reset, and counter load has lower priority than mask regi ste r lo ad (described below ). All c oun ter operations are independent of Chip Enables (CE When the address readback operation is performed the data I/Os are three-stated (if CEs are active) and one-clock cycle (no-operation cycle) latency is experienced. The address will be read at time t the no-operation cycle. The read back address can be either of the burst co unter or the mask r egist er base d on t he levels of Counter R ead signal (CNT RD signal (MKRD). Both signals are synchronized to the port's clock as shown i n Table 2. Counter read has a higher priority than mask read.

Addr. Read Back

from the rising edge of th e clo c k following

CA2

) and Mask Register Read

Memory

Array

and CE1).

CNTINC

CNTLD

CNTRST

CLK

Counter/

Address

= 1

Figure 1. Counter and Mask Register Read Back on Address Lines

Counter-Mask Register

PRELIMINAR Y

CY7C0430V

Example:

CNTINT

Load Counter-Mask Register = 3F

Load Address

Counter = 8

Max Address

Max + 1 Address

Figure 2. Programmable Counter-Mask Register Operation

Note:

46. The “X” in this diagram represents the counter upper-bits.

2152

0’s

1010101

242

Blocked Address Counter Address

X’s

1X0X0X0

242

1X1X1X1

0X0X0X0

[46]

Mask Register bit-0

Address Counter bit-0

The burst co unte r has a mask register that controls when a nd where the counter wra ps. An interrupt flag (CNTINT

) is asserted for one clock cycle when the unmasked portion of the counter address wr aps around from all ones (CNTIN C

must be asserted) to all zeros. The example in Figure 2 shows the counter mask register loaded with a mask value of 003F unmasking the first 6 bits with bit “0” as the LSB and bit “15” as the MSB. The m aximum va lue the mask regist er can be loaded with is FFFF. Setting the mask regist er to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of XXX8. The “blocked” addresses (in this case, the 6th address through the 15th address) are load ed with an address b ut do not increment once loaded. The c oun ter add res s wi ll sta rt at address XXX8. With CNTINC

asser ted LOW, th e counter will increme nt its internal address v alu e till it rea ches the ma sk re gister v alue of 3F and wraps around the memory block to location XXX0. Therefore, the counter uses the mask-register to define wrap-around point. The mask register of every port is loaded when MKLD

(mask register load) for that port is LOW. When MKRD is LOW, the value of the mask register can be rea d out on address lines in a mann er si mi lar to counter read back operation (see Table 2 for required conditions).

When the b urs t c ou nter is l oa ded wit h a n add res s hi ghe r th an the mask register value, the higher addresses will form the masked portion of the counter addres s and are called b loc ked addresses. The blocked addresses will not be changed or affected b y the cou nter increment o perat ion. The only ex ception is mask register bit 0. It can be masked to allow the address counter to increme nt by two . If the mask register bit 0 is l oaded with a logic value of “0,” then address counter bit 0 is masked and can not be changed during counter increment operation. If the loaded value for address counter bit 0 i s “0,” the counter

will increment by two and the address values are even. If the loaded value for address counter bit 0 is “1,” the counter will increment by two and the address values are odd. This operations allows the user to achieve a 36-bit interface using any two ports, where the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit word in e ven memo ry locations, and the oth er half in odd me mory locations. CNTINT

will be asserted when the unmasked portion of the counter wraps to all zeros. Loading mask register bit 0 with “1” allows the counter to increment the address value sequentially.

Ta b l e 2 groups th e operations of the mask re gister with the operations of the addr ess counte r . Addres s counter and mask register signals are all synchronized to the port's clock CLK. Master reset (MRST

) is the only asynch ronous signa l listed on Ta bl e 2 . Signals are listed based on their priority going from left column to right column with MRST LOW on MRST

will reset both counter regi ster to all zeros and

being the highest. A

mask register to all ones. On the other hand, a LOW on CNTRST

will only clear the address counter register to zeros

and the mask register will remain intact. There are four operations for the counter and mask register:

1. Load operation: When CNTLD

or MKLD is LOW, the address counter or the mask register is loaded with the address val ue presented at the address lines. T his value r anges from 0 to FFFF (64 K). The mask reg ister loa d opera tion has a higher priority over the address counter load operation.

2. Increment: Once the address c ou nte r i s loa ded w i th an external address, th e counter can internally increm ent the address value by asserting CNTINC

LOW. The counter can

PRELIMINAR Y

CY7C0430V

address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation.

3. Readback: the in ternal v alue of either the burst co unte r or the mask register can be read out on the address lines when CNTRD priority over ma sk regi ster read bac k. A no -oper ation d ela y cycle is experienced when readback operation is performed. The address will be valid after t readback) or t port's clock rising edge. Address readback operation is independent of the port's chip ena b l es (CE dress readback occurs while the port is enabled (chip enables active), the data lines (I/Os) will be three-stated.

4. Hold operation: In order to hold the value of the address counter at certain address, all signals in Table 2 have to be HIGH. This operation has the least priority. This operation is useful in man y applications whe re wait states are need ed or when address is available few cycles ahead of data.

The counter and mask regi ster opera tions are totall y independent of port chip enables.

or MKRD is LOW. Counter readback has higher

(for counter

(for mask readback) from the following

CM2

CA2

and CE1). If ad-

IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built- In - S e lf -Test (MBIST)

The CY7C0430V incorporat es a serial boundary scan tes t access port (TAP). This por t operates in accordance with IEEE Standard 1149.1-1900. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices us ing 114 9.1 fu ll y compliant TAPs. The TAP operates using JEDEC stand ard 3. 3V I/O l ogic l e v els . It is com pose d of three input connec tions and one output connection require d by the test logic defined by the standard. Memory BIST circuitry will also be controlled through the TAP interface. All MBIST instructions are compliant to the JTAG standard. An external clock (CLKBIST) is provided to allow the user to r un BIST a t speeds higher than 100 MHz. CLKBIST is multiple xed internally with the ports clocks during BIST operation.

Disabling the JTAG Feature

It is possible to operate the QuadPort without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are in-

ternally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. CLKBIST must be tied LOW to disable the MBIST. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

Test Access Port (TAP) - Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on th e rising e dge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to giv e comm ands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is use d to s erially in pu t information into t he regi sters and can be connec ted to the inp ut o f any of the registers . The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data Out (TDO)

The TDO output p in i s use d to se rial ly cl ock data-out from t he registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram (FSM)). The outpu t ch anges on the falli ng e dge of TC K. TDO is connected to the leas t si gni fic an t bit (LSB ) of an y r egister.

Performing a TAP Reset

A Reset is performed by f orcing TMS HIGH (V edges of TCK. This RESET does not af fect the operati on of the QuadP ort and may be p erformed while th e device i s operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the QuadPort test circuitry. Only one register can be selected at a time through the instruction reg isters. Data is serially loa ded into the T DI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

Instruction Register

Four-bit ins tructions can be serially lo ad ed i nto the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the following JTAG/BIST Controller diagram . Upon power-up , the instruction registe r is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” patt ern to allow f or fault isolation of the board level serial test path.

Bypass Register

To save time when serially sh ifting data through registers, it is sometimes adv a ntageo us to sk ip certain de vice s. The b ypas s register is a si ngle-bit re gister tha t can be placed be tween TD I and TDO pins. This allows data to be shifted through the QuadPort with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and output pins on the QuadPor t. The boundary scan register is loaded with the c ontents of the QP Inpu t and Outpu t ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring.

) for five rising

PRELIMINAR Y

CY7C0430V

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Captu re-DR state when t he IDCO DE comm and is loaded in the instruction register. The IDCODE is hardwired into the QuadPor t and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other inf ormation described in the Identific ation Register Defi nitions table.

TAP Instruction Set

Sixteen diff erent instructio ns are possib le with the 4- bit instruction register. All combinations are listed in Table 6, Instruction Codes. Seven of these instructions (codes) are listed as RESERVED and should not be used. The other nine instructions are described in detail below.

The TAP controller used in this QuadPort is fully compliant to the 1149.1 con ven tion. The TAP controller can be u sed to load address, data or control signals into the QuadPor t and can preload the Input or ou tput b uff e rs. The Qua dPort implements all of the 1149.1 instructions except INTEST. Table 6 lists all instructions.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction regis ter through the TDI and TDO pins. To execute the in struction onc e it is sh ifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandat ory 1149.1 in str uction which is to be executed whene v er th e instruc tion reg ister i s loade d with a ll 0s . EXTEST allows cir cuitry exter nal to the Q uadPort package t o be tested. Boundary-scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results.

IDCODE

The IDCODE inst ruction causes a vendor -specific, 32 -bit code to be loaded into the instruction register. It also places the instruction register bet we en the TDI an d TDO p ins and allo ws the IDCODE to be s hifted ou t of the de v ice when t he TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the in struction register up on power-up or whenev er the TAP controller is given a test logic reset state.

High-Z

The High-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all QuadPort outputs into a High-Z state.

SAMPLE / PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapsh ot of data on the in puts an d output pi ns is c aptured in the boundary scan register.

The user must be a ware that the TAP controller clock can onl y operate at a f requency up to 10 MHz, whil e the QuadP ort cloc k operates more than an orde r of magnitude faster. Because there is a large difference in the clock fr equencies, it i s possible that during the Capture-DR st ate, an input or output will undergo a transition. The TAP may then try to capture a signal whi le in transition (metastable state). This will not harm the device,

but there is no gu arant ee as to th e v alue that wi ll be cap tured. Repeatabl e resul ts may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the QuadPor t signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold time s. Once the d ata is capture d, it is possi ble to sh ift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. If the TAP controller goes into the Update-DR state, the sampled data will be updated.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TD O pi ns. The adv antage of the BYP ASS ins truction is that it shortens the boundary scan path when mul tip le devices are connected together on a board.

CLAMP

The optional CLAMP instruction a llow s the sta te of the s ignals driven from QuadPort pins to be determined from the boundary-scan register while the BYPASS register is selected as the serial path between TDI a nd TD O. CLAMP controls boundary cells to 1 or 0.

RUNBIST

RUNBIST instruct ion provides the user with a means of ru nning a user-accessible self-test function within the QuadPor t as a result of a sing le in struction. This permits all com ponen ts on a board that offer the RUNBIST instruction to execute th eir self-tests concurrently, providing a quick check for the board. The QuadPort MBIST provides two modes of operation once the TAP controller is loaded with the RUNBIST instruction:

Non-Debug Mode (Go-NoGo)

The non-debug mode is a go-nogo test used simply to run BIST and obtain pass-fail information after the test is run. In addition to that, the total number of failures encountered can be obtaine d. Thi s i nformat ion is use d to aid the d ebug mod e (explained next) of ope ration. The pass-fail inform ation and failure count is scanned out using the JTAG interface. An MBIST Result Register (MRR) will be used to store the pass-fail res ul ts. The MRR is a 25-bi t re gis ter tha t w il l be connected between TDI and TDO during the internal scan (INT_SCAN) operati on. The MRR will co ntain the total n umber of fail read cycles of the entire MBIST sequence. MRR[0] (bit

0) is the Pass/Fail bit. A “1” indicates some type of failure occurred, and a “0” indicates entire memory pass.

In order to run BIST in non-debug mode, the 2-bit MBIST Control Register (MCR) is loaded with the default value “00”, and the TAP controller’s finite state machine (FSM), which is synchronous to TCK, transition s to Run Test/Idle state. The entire MBIST test wi ll be per formed with a deter ministic number of TCK cycles depending on the TCK and CLKBIST frequency.

CLKBIST[]

CYC

--------------------------------------------

TCK[]

is total number of TCK cycles required to run MBIST.

mSPC+×=

SPC is the Synchronization Padding Cycles (4–6 cycles) m is a constant represents the number of re ad and write oper-

ations required to run MBIST algorithms (31,195,136).

PRELIMINAR Y

CY7C0430V

Once the entire MBIST se qu enc e is com pl ete d, su ppl yi ng extra TCK or CLKBIST cycles will have no effect on the MBIST controller state or the pass-fail status.

Debug Mode

With the RUNBIST instruction loaded and the MCR loaded with the value of “01”, and the FSM transitions to RUN_TEST/I DLE state, th e MBIST goes into R UNBIST-debug mode. The debug mode w i ll be us ed to pr ovi de co mp le te failure analysis inf o rmation at the bo ard le vel. It is recommended that the user runs the non-debug mode first and then the debug mode in ord er to sa v e test ti me and to set an up per bound on the number of scan outs that will be needed. The failure data will be scanned out automatically once a failure occurs using the JTAG TAP interface. The failure data will be represented by a 100-bit packet given below. The 100-bit Memory debug Register (MDR) will be connected between TDI and TDO, and wi ll be shifted out on TDO , which is sync hroniz ed to TCK.

Figure 3 i s a repr esentati on of th e 100-bit MDR packet. Th e packet follows a 2-bit header that has a logic “1” value, and represents two TCK cycles. MDR[97:26] represent the BIST comparator values of all four ports (each port has 18 data lines). A value of “1” indicates a bit failure. The scanned out data is from MSB to LSB. MDR[25:10] represent the failing address (MSB to LSB). The state of the BIST controller is scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0” in bit 2 means test not complete. The user has to monitor this bit at every pac ket to determine if more f ailure pac kets need to

be scanned out at the end of the BIST operations. If the value is “0” then BIST must be repeated to capture the next failing packet. If it is “1,” it means that the last failing packets have been scanned out. A trailer similar to the header represents the end of a packet.

MCR_SCAN

This instruction will connect the Memory BIST Control Register (MCR) between TDI and TDO. The default value (upon master reset) is “00”. Shift_DR state will allow modifying the MCR to extend the MBIST functionality.

MBIST Control States

Thirty-five states are lis ted in Table 7. Four data algorithms are used in debug mode: moving inversion (MIA), march_2 (M2A), checkerboard (CBA), and unique address algorithm (UAA). Only Port 1 can write MIA, M2A, and CBA data to the memory. All four ports can read any algorithm data from the QP memory. Ports 2, 3, and 4 will only write UAA data.

Boundary Scan Cells (BSC)

Table 9 lists all QuadPort I/Os with their associated BSC. Notice that the cells have even numbers. Every I/O has two boundary scan cells. Bidi rectional signals (address lines, da talines) require two cells so that one (the odd cell) is used to control a three-state buffer. Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout.

99 98

1 1

P4_IO(17-9)

61 26

P4_IO(8-0)

A(15-0)

MBIST_State

P/F

TD 10

1 1

P3_IO(17-9) P1_IO(17-9)P2_IO(17-9)

P3_IO(8-0) P1_IO(8-0)P2_IO(8-0)

Figure 3. MBIST Debug Register Packet

PRELIMINAR Y

CY7C0430V

TAP Controller State Diagram (FSM)

TEST-LOGIC RESET

RUN_TEST/

IDLE

[47]

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

SELECT IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-DR

EXIT2-DR

UPDATE-DR

Note:

47. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

PAUSE-IR

EXIT2-IR

UPDATE-IR

PRELIMINAR Y

JTAG/BIST TAP Controller Block Diagram

MBIST Control Register (MCR)

TDI

MBIST Result Register (MRR) 31 30 29 0

Bypass Register (BYR)

1 0

3 2 1 0

Instruction Register (IR)

24 23 0

CY7C0430V

Selection Circuitry

TDO

CLKBIST

99 0

BIST CONTROLLER

MEMORY CELL

Identification Register (IDR)

MBIST Debug Register (MDR)

0391

Boundary Scan Register (BSR)

TAP CONTROLLER

(MUX)

TCK TMS MRST

JTAG Timing Wave form

Test Clock TCK

Test Mode Select TMS

Test Data-In TDI

PRELIMINAR Y

TMSS

TDIS

CY7C0430V

TMSH

TDIH

TCYC

Test Data-Out TDO

TDOX

Table 4. Identification Register Definitions

Instruction Field Value Description

Revision Number (31:28)

Cypress Devic e ID (27:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

0h Reserved for version number

C000h Define s Cypress part number

34h Allows unique identification of QuadPort vendor

1 Indicate the presence of an ID register

TDOV

PRELIMINAR Y

Table 5. Scan Registers Sizes

Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 MBIST Control (MCR) 2 MBIST Result (MRR) 25 MBIST Debug (MDR) 100 Boundary Scan (BSR) 392

Table 6. Instruction Identification Codes

Instruction Code Description

EXTEST 0000 Captures the Input/Output ring contents. Pla ces the boundary scan register

(BSR) between the TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

CY7C0430V

IDCODE 0111 Loads the ID reg ister (IDR) with the v endor ID c ode and places th e registe r

HIGHZ 0110 Places the boundary scan registe r between TDI a nd TDO . F orces all Qu ad-

CLAMP 0101 Controls boundary to 1/0. Uses BYR. SAMPLE/PRELOAD 0001 Captures the Input/Output ring contents. Places the boundary scan register

RUNBIST 1000 Invokes MBIST. Places the MBIST Debug re gister (MDR) between TDI an d

INT_SCAN 0010 Scans out pass-fail information. Places MBIST Result Register (MRR) be-

MCR_SCAN 0011 Presets RUNBIST mode. Places MBIST Control Register (MCR) between

RESERVED All other codes Seven combinations are reserved. Do not use other than the above.

Table 7. MBIST Control States

States Code State Name Description

000001 movi_zeros Port 1 write all zeros to the QP memory using Moving Inversion Algorithm

000011 movi_1_upcnt Up count from 0 to 64K (depth of QP). All ports read 0s, then P ort 1 writes 1s

000010 movi_0_upcnt Up count from 0 to 64K. All p orts read 1s, then P ort 1 writes 0s, the n all ports

000110 movi_1_downcnt Down count from 64K to 0. MIA_r0w1r1. 000111 movi_0_downcnt Down count MIA_r1w0r0. 000101 movi_read Read all 0s.

between TDI and TDO.

Port output drivers to a High-Z state. Uses BYR.

(BSR) between TDI and TDO.

TDO.

tween TDI and TDO.

TDI and TDO.

(MIA).

to all memory locations using MIA, then all ports read 1s. MIA read0_write1_read1 (MIA_r0w1r1).

read 0s (MIA_r1w0r0).

000100 mar2_zeros Port 1 write all zeros to memory using March2 Algorithm (M2A). 001100 mar2_1_upcnt Up count M2A_r0w1r1.

PRELIMINAR Y

Table 7. MBIST Control States

States Code State Name Description

001101 mar2_0_upcnt Up count M2A_r1w0r0. 001111 mar2_1_downcnt Down count M2A_r0w1r1. 001110 mar2_0_downcnt Down count M2A_r1w0r0. 001010 mar2_read Read all 0s.

001011 chkr_w Port 1 writes topological checkerboard data to memory. 001001 chkr_r All ports read topological checkerboard data. 001000 n_chkr_w Port 1 write inverse topological checkerboard data. 011000 n_chkr_r All ports read inverse topological checkerboard data.

011001 uaddr_zeros2 Port 2 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write2 Port 2 writes every address value into its memory location (UAA). 011010 uaddr_read2 All ports read UAA data. 011110 uaddr_ones2 Port 2 writes all ones to memory. 011111 n_uaddr_write2 Port 2 writes inverse address value into memory. 011101 n_uaddr_read2 All ports read inverse UAA data.

011001 uaddr_zeros3 Port 3 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write3 Port 3 writes every address value into its memory location (UAA). 011010 uaddr_read3 All ports read UAA data. 011110 uaddr_ones3 Port 3 writes all ones to memory. 011111 n_uaddr_write3 Port 3 writes inverse address value into memory. 011101 n_uaddr_read3 All ports read inverse UAA data.

CY7C0430V

011001 uaddr_zeros4 Port 4 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write4 Port 4 writes every address value into its memory location (UAA). 011010 uaddr_read4 All ports read UAA data. 011110 uaddr_ones4 Port 4 writes all ones to memory. 011111 n_uaddr_write4 Port 4 writes inverse address value into memory. 011101 n_uaddr_read4 All ports read inverse UAA data.

110010 complete Test complete.

Table 8. MBIST Control Register (MCR)

MCR[1:0] Mode

00 Non-Debug 01 Debug 10 Reserved 11 Reserved

PRELIMINAR Y

CY7C0430V

Table 9. Boundary Scan Order

Cell # Signal Name Bump (Ball) ID

2 A0_P4 K20 4 A1_P4 J19 6 A2_P4 J18 8 A3_P4 H20 10 A4_P4 H19 12 A5_P4 G19 14 A6_P4 G18 16 A7_P4 F20 18 A8_P4 F19 20 A9_P4 F18 22 A10_P4 E20 24 A11_P4 E19 26 A12_P4 D19 28 A13_P4 D18 30 A14_P4 C20 32 A15_P4 C19 34 CNTINT_P4 F17 36 CNTRST_P4 K18 38 MKLD_P4 H18 40 CNTLD_P4 H17 42 CNTINC_P4 G17 44 CNTRD_P4 E17 46 MKRD_P4 E18 48 LB_P4 A20 50 UB_P4 B19 52 OE_P4 D17 54 R/W_P4 C16 56 CE1_P4 C18 58 CE0_P4 C17 60 INT_P4 K19 62 CLK_P4 K17 64 A0_P3 L20 66 A1_P3 M19 68 A2_P3 M18 70 A3_P3 N20 72 A4_P3 N19 74 A5_P3 P19 76 A6_P3 P18 78 A7_P3 R20 80 A8_P3 R19 82 A9_P3 R18

Table 9. Boundary Scan Order

Cell # Signal Name Bump (Ball) ID

84 A10_P3 T20 86 A11_P3 T19 88 A12_P3 U19 90 A13_P3 U18 92 A14_P3 V20 94 A15_P3 V19 96 CNTINT_P3 R17 98 CNTRST_P3 L18 100 MKLD_P3 N18 102 CNTLD_P3 N17 104 CNTINC_P3 P17 106 CNTRD_P3 T17 108 MKRD_P3 T18 110 LB_P3 Y20 112 UB_P3 W19 114 OE_P3 U17 116 R/W_P3 V16 118 CE1_P3 V18 120 CE0_P3 V17 122 INT_P3 L19 124 CLK_P3 M17 126 IO0_P4 Y15 128 IO1_P4 W15 130 IO2_P4 Y16 132 IO3_P4 W16 134 IO4_P4 Y17 136 IO5_P4 W17 138 IO6_P4 Y18 140 IO7_P4 W18 142 IO8_P4 Y19 144 IO0_P3 V12 146 IO1_P3 Y11 148 IO2_P3 W12 150 IO3_P3 Y12 152 IO4_P3 W13 154 IO5_P3 Y13 156 IO6_P3 V15 158 IO7_P3 Y14 160 IO8_P3 W14 162 IO0_P1 Y6 164 IO1_P1 W6

(continued)

PRELIMINAR Y

CY7C0430V

Table 9. Boundary Scan Order

Cell # Signal Name Bump (Ball) ID

166 IO2_P1 Y5 168 IO3_P1 W5 170 IO4_P1 Y4 172 IO5_P1 W4 174 IO6_P1 Y3 176 IO7_P1 W3 178 IO8_P1 Y2 180 IO0_P2 V9 182 IO1_P2 Y10 184 IO2_P2 W9 186 IO3_P2 Y9 188 IO4_P2 W8 190 IO5_P2 Y8 192 IO6_P2 V6 194 IO7_P2 Y7 196 IO8_P2 W7 198 A0_P2 L1 200 A1_P2 M2 202 A2_P2 M3 204 A3_P2 N1 206 A4_P2 N2 208 A5_P2 P2 210 A6_P2 P3 212 A7_P2 R1 214 A8_P2 R2 216 A9_P2 R3 218 A10_P2 T1 220 A11_P2 T2 222 A12_P2 U2 224 A13_P2 U3 226 A14_P2 V1 228 A15_P2 V2 230 CNTINT_P2 R4 232 CNTRST_P2 L3 234 MKLD_P2 N3 236 CNTLD_P2 N4 238 CNTINC_P2 P2 240 CNTRD_P2 T4 242 MKRD_P2 T3 244 LB_P2 Y1 246 UB_P2 W2

(continued)

Table 9. Boundary Scan Order

Cell # Signal Name Bump (Ball) ID

248 OE_P2 U4 250 R/W_P2 V5 252 CE1_P2 V3 254 CE0_P2 V4 256 INT_P2 L2 258 CLK_P2 M4 260 A0_P1 K1 262 A1_P1 J2 264 A2_P1 J3 266 A3_P1 H1 268 A4_P1 H2 270 A5_P1 G2 272 A6_P1 G3 274 A7_P1 F1 276 A8_P1 F2 278 A9_P1 F3 280 A10_P1 E20 282 A11_P1 E2 284 A12_P1 D2 286 A13_P1 D3 288 A14_P1 C1 290 A15_P1 C2 292 CNTINT_P1 F4 294 CNTRST_P1 K3 296 MKLD_P1 H3 298 CNTLD_P1 H4 300 CNTINC_P1 G4 302 CNTRD_P1 E4 304 MKRD_P1 E3 306 LB_P1 A1 308 UB_P1 B2 310 OE_P1 D4 312 R/W_P1 C5 314 CE1_P1 C3 316 CE0_P1 C4 318 INT_P1 K2 320 CLK_P1 K4 322 IO9_P2 A6 324 IO10_P2 B6 326 IO11_P2 A5 328 IO12_P2 B5

(continued)

PRELIMINAR Y

CY7C0430V

Table 9. Boundary Scan Order

Cell # Signal Name Bump (Ball) ID

330 IO13_P2 A4 332 IO14_P2 B4 334 IO15_P2 A3 336 IO16_P2 B3 338 IO17_P2 A2 340 IO9_P1 C9 342 IO10_P1 A10 344 IO11_P1 B9 346 IO12_P1 A9 348 IO13_P1 B8 350 IO14_P1 A8 352 IO15_P1 C6 354 IO16_P1 A7 356 IO17_P1 B7 358 IO9_P3 A15 360 IO10_P3 B15 362 IO11_P3 A16 364 IO12_P3 B16 366 IO13_P3 A17 368 IO14_P3 B17 370 IO15_P3 A18 372 IO16_P3 B18 374 IO17_P3 A19 376 IO9_P4 C12 378 IO10_P4 A11 380 IO11_P4 B12 382 IO12_P4 A12 384 IO13_P4 B13 386 IO14_P4 A13 388 IO15_P4 C15 390 IO16_P4 A14 392 IO17_P4 B14

(continued)

PRELIMINARY

Ordering Informat ion

64K x 18 3.3V Synchronous QuadPort SRAM

Speed

(MHz) Ordering Code

133 CY7C0430V-133BGC BG272

CY7C0430V-133BGI BG272

100 CY7C0430V-100BGC BG272

CY7C0430V-100BGI BG272

Document #: 38-00882

Package Diagram

272-Ball Grid Array (27 x 27 x 2.33 mm) BG272

Package

Name Package Type

272-Ball Grid Array (BGA) 272-Ball Grid Array (BGA) 272-Ball Grid Array (BGA) 272-Ball Grid Array (BGA)

CY7C0430V

Operating

Range

Commercial Industrial Commercial Industrial

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circui try embodied in a Cypre ss Semiconductor product. Nor d oes it conv ey or imply any license under patent or ot her rights. Cypre ss Semiconductor does not autho rize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Datasheet CY7C0430V-133BGC, CY7C0430V-100BGI, CY7C0430V-100BGC Datasheet (Cypress Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual