30V
PRELIMINARY
Synchronous QuadPort™ Static RAM
Features
• True four-ported memory cells which allow simultaneous access of the same memory location
• Synchronous Pipelined device
—64K x 18 organization
• Pipelined output mode allows fast 133-MHz operation
• High Bandwidth up to 10 Gb ps (133 MHz x 1 8 bits wi de
x 4 ports)
• 0.25-micron CMOS for optimum speed/power
• High-speed clock to data access 4.7 ns (max.)
• 3.3V Low operating power
—Active = 750mA (maximum)
—Standby = 1mA (maximum)
Top Level Logic Block Diagram
Port 1 Operation-Control Logic Blocks
UB
P1
LB
P1
R/W
P1
OE
P1
CE
0P1
CE
1P1
CLK
P1
[1]
Port-1
Control
Logic
CY7C0430V
3.3V 64K x 18
• Counter wrap-ar ound cont r ol
—Internal mask register co ntrols counter wrap-ar ound
—Counter-Interrupt flags to indicate wrap-around
• Counter readback on address lines
• Mask register readback on address lines
• Interrupt flags for message passin g
• Master reset for all ports
• Width and depth expansion capabi litie s
• Dual Chip Enabl es on all ports for easy depth expans ion
• Separate upper-byte and lower-byte controls on all
ports
• 272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)
• Commercial and Industrial temperature ranges
• IEEE 1149.1 JTAG boundary scan
• BIST (Built In Self Test) controller
MRST
TMS
TCK
TDI
CLKBIST
Reset
Logic
JTAG
Controller
BIST
TDO
I/O
0P1
- I/O
17P1
CLK
P1
A
0P1–A15P1
MKLD
CNTLD
CNTINC
CNTRD
MKRD
CNTRST
CNTINT
P1
INT
18
16
P1
P1
P1
P1
P1
P1
P1
Mask Reg/
Port 1
I/O
Port 1
Counter/
Address
Decode
Port 2 Logic Blocks
Notes:
1. Port 1 Control Logic Block is detailed on page 2.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
For the most recent information, visi t the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Port 1
RAM
Array
Port 2 Port 3
[2]
Port 4 Logic Blocks
Port 4
Port 3 Logic Blocks
[2]
[2]
November 18, 199 9
PRELIMINAR Y
Port 1 Operation-Contr ol Logic Block Dia gr am:
(Address Readback is independent of CEs)
R/W
CE
CE
LB
OE
UB
0P1
1P1
P1
P1
P1
P1
W
R
CY7C0430V
MRST
A
0P1–A15P1
CNTRD
MKRD
MKLD
CNTINC
CNTLD
CNTRST
CLK
MRST
CNTINT
P1
P1
P1
P1
P1
P1
P1
P1
16
Priority
Decision
Logic
I/O
I/O
9P1
0P1
–I/O
–I/O
17P1
8P1
9
9
Addr.
Read
Back
Port 1
Readback
Register
Port 1
Mask Register
Port 1
Counter/
Address
Register
LB
UB
R/W
CE
0P1
CE
1P1
OE
P1
CLK
MRST
P1
P1
P1
P1
Port-1
I/O
Control
Port 1
Address
Decode
Port 1
Interrupt
Logic
Port
Port
INT
1
Po
r
t
4
RAM
Array
3
2
P1
ort
P
2
PRELIMINAR Y
CY7C0430V
Functional Description
The CY7C0430V is a 1-Mb synchronous true four-port Static
RAM. This is a high-speed, low-power 3.3V CMOS dual-port
static RAM. Four ports are provided, permitting independent,
simultaneous ac cess f or reads from any location in memory. A
particular port can write to a certain location while other p orts
are reading that location simultaneously. The result of writing
to the same location by more than one port at the same time
is undefined. Registers on control, address and data lines allow for minimal set-up and hold time.
Data is registered for decreased cycle time. Clock to data valid
= 4.7 ns. Each port contains a burst counter on the input
t
CD2
address register. After externally loading the counter with the
initial address the counter will self-increment the address internally (more details to foll o w ). Th e inte rnal write pulse width
is independent of the duration of the R/W
internal write pulse is self-tim ed to all o w the sho rtest possible
cycle times.
A HIGH on CE
down the internal circuitry to reduce the static power consumption. One cycle is req uired w ith c hip en ab les asserted to reac tivate the outputs.
Counter enable inpu ts are provided to stall the operat ion of the
address input and utiliz e the internal addres s generated b y the
or LOW on C E1 for one clo ck cycle wi ll power
0
input signal. The
inter nal counter for fast interleaved mem ory application s. A
port's burst counter is loaded with an external address when
the port's Counter Load pin (CNTLD
the port's Counter Increment pin (CNTINC) is asserted, the
address counter will increment on each subsequent LOW-toHIGH transition of that port's clock signal. This will read/write
one word from/into each successive address location until
CNTINC
memory array and will loop back to the start. Counter Reset
(CNTRST
register is used to control the counter wrap. The counter and
mask register operations are described in more details in the
following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD
spectively.
The new features added to th e QuadPort™
standard synchronous dual-ports include: readback of
burst-counter internal address value on address lines,
counter-mask registers to control the counter wrap-around,
readback of mask register value on address lines, interrupt
flags for messag e passing, BIST, JT A G for boundary scan, and
asynchronous Maste r Reset.
is deasserted. The counter can address the entire
) is used to reset the burst counter. A counter-mask
) is asserted LOW. When
or CNTRD re-
as compared t o
3
Pin Configuration
1234567891011121314151617181920
I/O17P2I/O15P2I/O13P2I/O11P2I/O9P2I/O16P1I/O14P1I/O12P1I/O10P1I/O10P4I/O12P4I/O14P4I/O16P4I/O9P3I/O11P3I/O13P3I/O15P3I/O17P3 LB
LB
A
P1
PRELIMINAR Y
272-Ball Grid Array (BGA)
Top View
CY7C0430V
P4
VDD1 UB
B
A14P1A15P1CE1P1CE0
C
VSS1 A12P1A13P1 OE
D
A10P1A11P1MKRD
E
A7P1A8P1A9P1CNTINT
F
VSS1 A5P1A6P1CNTINC
G
A3P1A4P1MKLD
H
VDD1 A1P1A2P1VDD GND
J
A0P1INT
K
A0P2INT
L
VDD1 A1P2A2P2CLK
M
A3P2A4P2MKLD
N
VSS1 A5P2A6P2CNTINC
P
I/O16P2I/O14P2I/O12P2I/O10P2I/O17P1I/O13P1I/O11P1TMS TDI I/O11P4I/O13P4I/O17P4I/O10P3I/O12P3I/O14P3I/O16P3UBP4VDD1
P1
R/WP1I/O15P1VSS2 VSS2 I/O9P1 TCK TDO I/O9P4VSS2 VSS2 I/O15P4R/WP4CE0P4CE1P4A15P4A14
P1
VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP4A13P4A12P4VSS1
P1
CNTRD
P1
P1
P1
P1
CNTLD
P1
P1
CNTRSTP1CLK
P1
P2
CNTRSTP2 VSS
P1
P2
CNTLD
P2
P2
P2
GND
GND
GND
P4
MKRDP4A11P4A10
CNTRD
P4
CNTINT
P4A9P4A8P4
CNTINC
P4A6P4A5P4
MKLDP4A4P4A3
CNTLD
P4
[3]
[3]
[3]
GND
GND
[3]
[3]
GND
GND
[3]
[3]
GND
GND
[3]
[3]
GND
GND
[3]
GND
[3]
[3]
GND
[3]
[3]
GND
[3]
[3]
GND
VDD A2P4A1P4VDD1
CLKP4CNTRST
P4
VSS CNTRST
P3
CLKP3A2P3A1P3VDD1
MKLDP3A4P3A3
CNTLD
P3
CNTINC
P3A6P3A5P3
VSS1
INTP4 A0
INTP3 A0
VSS1
P4
A7
P4
P4
P4
P3
P3
A7P2A8P2A9P2CNTINT
R
A10P2A11P2MKRD
T
VSS1 A12P2A13P2 OE
U
A14P2A15P2CE1P2 CE0
V
VDD1 UB
W
Y
P2
I/O8P1I/O6P1I/O4P1I/O2P1I/O0P11/O7P2I/O5P2I/O3P2I/O1P2I/O1P3I/O3P3I/O5P3I/O7P3I/O0P4I/O2P4I/O4P4I/O6P4I/O8P4LB
LB
P2
P2
CNTRD
P2
P2
VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP3A13P3A12P3VSS1
P2
R/WP2I/O6P2VSS2 VSS2 I/O0P2NC NC I/O0P3VSS2 VSS2 I/O6P3R/WP3CE0P3CE1P3A15P3A14
P2
I/O7P1I/O5P1I/O3P1I/O1P1I/O8P2I/O4P2I/O2P2MRST
Note:
3. Central Leads are for thermal dissipation only. They are connected to device V
4
CNTINT
P3A9P3A8P3
MKRDP3A11P3A10
CNTRD
P3
CLKBIST I/O2P3I/O4P3I/O8P3I/O1P4I/O3P4I/O5P4I/O7P4UB
.
SS
A7
P3
P3
P3
VDD1
P3
P3
PRELIMINAR Y
CY7C0430V
Selection Guide
CY7C0430V
-133
(MHz) 133 100
f
MAX2
Max Access Time (ns) (Clock to Data) 4.7 5.0
Max Operating Current I
Max Standby Current for I
Max Standby Current for I
(mA) 750 600
CC
(mA) (All ports TTL Level) 200 150
SB1
(mA) (All ports CMOS Level) 1.0 1.0
SB3
CY7C0430V
-100
Pin Definitions
Port 1 Port 2 Port 3 Port 4 Description
A
0P1–A15P1
I/O
–I/O
0P1
CLK
P1
LB
P1
UB
P1
CE
,CE
0P1
OE
P1
R/W
P1
MRST Master Reset Input. Thi s is one signal for All P orts. MRST
CNTRST
MKLD
CNTLD
CNTINC
P1
P1
P1
P1
17P1
1P1
A
0P2–A15P2
I/O
–I/O
0P2
CLK
P2
LB
P2
UB
P2
CE
,CE
0P2
OE
P2
R/W
P2
CNTRST
MKLD
P2
CNTLD
CNTINC
P2
P2
P2
17P2
1P2
A
0P3–A15P3
I/O
–I/O
0P3
CLK
P3
LB
P3
UB
P3
CE
,CE
0P3
OE
P3
R/W
P3
CNTRST
MKLD
P3
CNTLD
CNTINC
P3
P3
P3
17P3
1P3
A
0P4–A15P4
I/O
–I/O
0P4
CLK
P4
LB
P4
UB
P4
CE
,CE
0P4
OE
P4
R/W
P4
CNTRST
MKLD
P4
CNTLD
CNTINC
P4
P4
P4
Address Input/Output.
Data Bus Input/Output.
17P4
Clock Input. This input can be free running or strobed.
Maximum cloc k input ra te is f
MAX
.
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. For
read operations bo th the LB
and OE signals mu st be asserted to drive output data on the lower byte of the d ata
pins.
Upper Byte Select Input. Same funct ion as LB, b ut to the
upper byte.
Chip Enable Input. T o select any port, both CE0 AND CE1
1P4
must be asserted to their active states (CE0 ≤ VIL and
≥ VIH).
CE
1
Output Enable Input. This sig nal mus t be asserted LOW
to enable the I/O data lines during read operations. OE
is asynchronous input.
Read/Write Enable Input. This sig nal is asserted LO W to
write to the dual port memory array . For read oper ations,
assert this pin HIGH.
is an asynchronous input. Asserting MRST
forms all of the reset functi ons as described in the te xt. A
operation is required at power-up.
MRST
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST
is second to MRST in priority with respect to
counter and mask register operations.
Mask Register Load input. Asserting this signal LOW
loads the mask register with the external address available on the address lines. MKLD
priority over CNTLD
operation.
operation has higher
Counter Load Inpu t. Asserting this si gnal LO W loads th e
burst counter with the external address present on the
address pins.
Counter Increment Input. Asserting this signal LOW increments the b urst address counter of its respective port
on each rising edge of CLK.
LOW per-
5
PRELIMINAR Y
CY7C0430V
Pin Definitions
(continued)
Port 1 Port 2 Port 3 Port 4 Description
CNTRD
P1
CNTRD
P2
CNTRD
P3
CNTRD
P4
Counter Readbac k Input. When asserted LOW, the internal address val ue of the counter wil l be read back on the
address lines. During CNTRD
and CNTINC
must be HIGH. Count er readback operati on
operation, both CNTLD
has higher priority over mask register readback operation. Counter readback operation is ind epe nde nt o f port
chip enables . If addres s readb ac k op erati on oc curs w ith
= LOW , CE1 = HIGH), the data
0
from the
CD2
MKRD
P1
MKRD
P2
MKRD
P3
MKRD
P4
chip enables activ e (CE
lines (I/Os) will be three-stat ed. The readbac k timing will
be valid after one no-operation cycle plus t
rising edge of the next cycle.
Mask Register Readback Input. When asserted LOW, the
value of the mask register will be readback on address
lines. During mask register readback operation, all
counter and MKLD
inputs must be HIGH (see Counter
and Mask Register Oper ations truth table). Mask re gister
readback op erati on is indepe ndent o f po rt chip enab les .
If address readback operation occurs with chip enables
= LOW, CE1 = HIGH), the data lines (I/Os)
0
from the rising edge of the
CD2
CNTINT
P1
CNTINT
P2
CNTINT
P3
CNTINT
P4
active (CE
will be three-stated. The read bac k will be v al id after o ne
no-operation cycle plus t
next cycle.
Counter Interrupt flag output. Flag is asserted LOW for
one clock cycle when the counter wraps around to location zero.
INT
P1
INT
P2
INT
P3
INT
P4
Interrupt flag output. Interrupt permits communications
between all f o ur ports. The upp er f our mem ory locations
can be used for m essage passing. Example of operation:
is asserted LOW when another port writes to the
INT
P4
mailbox location of Port 4. Flag is cleared when Port 4
reads the contents of its mailbox. The same operation is
applicable to Ports 1, 2, and 3.
TMS JTAG Test Mode Select Input. It contr ols th e a dvance of
JTAG TAP state machine. State machine transitions occur on the rising edge of TCK.
TCK JT AG Test Clock Input. This can be CLK of any port or an
external clock connected to the JTAG TAP.
TDI JTAG Test Data Input. This is the only data input. TDI
inputs will shift data serially in to the selected register.
TDO JT AG Test Data Output. This is the only data output. TDO
transitions occur on the falling edge of TCK. TDO normally three-stated except when captured data is shifted out
of the JTAG TAP.
CLKBIST BIST Clock Input.
GND Thermal ground for heat dissipation.
V
V
V
V
V
V
SS
DD
SS1
DD1
SS2
DD2
Ground Input.
Power Input.
Address lines ground Input.
Address lines power Input.
Data lines ground Input.
Data lines power Input.
6
PRELIMINAR Y
CY7C0430V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
1-4
MAX
1
°
°
≥
|
C to + 150°C
C to + 125°C
+0.5V
CC
Indust. 413 750 330 600 mA
Com’l. mA
Indust. 80 200 60 150 mA
Com’l. mA
Indust. 170 349 128 263 mA
Com’l. mA
Indust. 0.5 1 0.5 1 mA
Com’l.
Indust. 110 200 83 151 mA
Com’l. mA
Storage Temperature................................ –65
Ambient Temperature with
Power Applied............................................–55
Supply Voltage to Ground Potential..............–0.5V to + 4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
Electrical Characteristics
Over the Operating Range
Parameter Description
V
V
V
V
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
OH
OL
IH
IL
Output HIGH Voltage
(V
CC
= Min., I
= –4.0 mA)
OH
Output LOW Voltage
(V
CC
= Min., I
= +4.0 mA)
OH
Input HIGH Voltage 2.0 2.0 V
Input LOW Voltage 0.8 0.8 V
Output Leakage Current –10 10 –10 10
Operating Current (V
= 0 mA) Outputs Disabled
I
OUT
= Max.,
CC
Standby Current (4 Ports toggling
at TTL Levels ,0 active) CE
, f = f
V
IH
MAX
Standby Current (4 Ports toggling
at TTL Levels , 1 active)
| CE3 | CE
<
VIH, f = f
4
CE1 | CE2
MAX
Standby Current (4 Ports CMOS
Level, 0 active) CE
1-4
≥
VIH, f = 0
Standby Current (3 Ports CMOS
Level, 1 Port TTL active) CE
| CE3 | CE
CE
2
<
VIH, f = f
4
DC Input Voltage .....................................–0.5V to V
CC
Output Current into Outputs (LO W).............................20 mA
Static Discharge Voltage ...........................................>2001V
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V ± 150 mV
Industrial –40
CY7C0430V
-133 -100
Min. Typ Max Min. Typ Max
2.4 2.4 V
0.4 0.4 V
Ambient
Temperature V
C to +85°C 3.3V ± 150 mV
°
DD
+0.5V
Unit
µ
A
µ
A
JTAG TAP Electrical Characteristics
Over the Operati ng Rang e
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
I
OH1
OL1
IH
IL
X
Output HIGH Voltage I
= −4.0 mA 2.4 V
OH
Output LOW Voltage IOL = 4.0 mA 0.4 V
Input HIGH Voltage 2.0 V
Input LOW Voltage 0.8 V
Input Leakage Current GND ≤ VI ≤ V
DD
–100 100
Capacitance
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= 3.3V
V
Output Capacitance 8 pF
CC
8 pF
7
µ
A
AC Test Load
Z0 = 50
OUTPUT
PRELIMINAR Y
Ω
[4]
C
R = 50
Ω
OUTPUT
Z0 = 50
5 pF
Ω
R = 50
Ω
CY7C0430V
(a) Normal Load
TDO
Z
0
(c) TAP Load
Note:
4. Test Conditions: C = 10 pF.
=50
VTH=1.5V
VTH=1.5V
(b) Three-State Delay
1.5V
Ω
50
Ω
GND
C= 10 pF
3.0V
GND
10%
t
R
90%
90%
10%
t
F
ALL INPUT PULSES
8
PRELIMINAR Y
CY7C0430V
Switching Characteristics
Over the Industrial Operating Range
Parameter Description
f
MAX2
t
CYC2
t
CH2
t
CL2
t
R
t
F
t
SA
t
HA
t
SC
t
HC
t
SW
t
HW
t
SD
t
HD
t
SB
t
HB
t
SCLD
t
HCLD
t
SCINC
t
HCINC
t
SCRST
t
HCRST
t
SCRD
t
HCRD
t
SMLD
t
HMLD
t
SMRD
t
HMRD
t
OE
t
OLZ
t
OHZ
t
CD2
t
CA2
t
CM2
t
DC
t
CKHZ
t
CKLZ
t
SINT
t
RINT
t
SCINT
t
RCINT
[5]
[5]
[6]
[6]
Maximum Frequency 133 100 MHz
Clock Cycle Time 7.5 10 ns
Clock HIGH Time 3 4 ns
Clock LO W Tim e 3 4 ns
Clock Rise Time 2 3 ns
Clock Fall Time 2 3 ns
Address Set-up Time 2.5 3 ns
Address Hold Time 0.5 0.5 ns
Chip Enable Set-up Time 2.5 3 ns
Chip Enable Hold Time 0.5 0.5 ns
R/W Set-up Time 2.5 3 ns
R/W Hold Time 0.5 0.5 ns
Input Data Set-up Time 2.5 3 ns
Input Data Hold Time 0.5 0.5 ns
Byte Set-up Time 2.5 3 ns
Byte Hold Time 0.5 0.5 ns
CNTLD Set-up Time 2.5 3 ns
CNTLD Hold Time 0.5 0.5 ns
CNTINC Set-up Time 2.5 3 ns
CNTINC Hold Time 0.5 0.5 ns
CNTRST Set-up Time 2.5 3 ns
CNTRST Hold Time 0.5 0.5 ns
CNTRD Set-up Time 2.5 3 ns
CNTRD Hold Time 0.5 0.5 ns
MKLD Set-up Time 2.5 3 ns
MKLD Hold Time 0.5 0.5 ns
MKRD Set-up Time 2.5 3 ns
MKRD Hold Time 0.5 0.5 ns
Output Enable to Data Valid 6.5 8 ns
OE to LOW Z 1 1 ns
OE to HIGH Z 1 6 1 7 ns
Clock to Data Valid 4.7 5 ns
Clock to Counter Address Readback Valid 4.7 5 ns
Clock to Mask Register readback Valid 4.7 5 ns
Data Output Hold After Clock HIGH 1 1 ns
Clock HIGH to Output High Z 1 4.8 1 6.8 ns
Clock HIGH to Output LOW Z 1 1 ns
Clock to INT Set Time 1 6.5 1 8 ns
Clock to INT Reset Time 1 6.5 1 8 ns
Clock to CNTINT Set Time 1 6.5 1 8 ns
Clock to CNTINT Reset Time 1 6.5 1 8 ns
CY7C0430V
–133 –100
Min. Max. Min. Max.
Unit
9
PRELIMINAR Y
CY7C0430V
Switching Characteristics
Over the Industrial Operating Range (contin ue d)
Parameter Description
Master Reset Timing
t
RS
t
RSS
t
RSR
t
RSF
t
RScntint
Master Reset Pulse Width 7.5 10 ns
Master Reset Set-up Time 6.0 8.5 ns
Master Reset Recovery Time 7.5 10 ns
Master Reset to Interrupt Flag Reset Time 6.5 8 ns
Master Reset to Counter Interrupt Flag Reset Time 6.5 8
Port to Port Delays
t
CCS
Notes:
5. This parameter is guaranteed by design, but it is not production tested.
6. Valid for both address and data outputs.
Clock to Clock Set-up Time 6.5 9 ns
CY7C0430V
–133 –100
Min. Max. Min. Max.
Unit
10
PRELIMINAR Y
JTAG Timing and Switching W aveforms
Parameter Description
f
JTAG
t
TCYC
t
TH
t
TL
t
TMSS
t
TMSH
t
TDIS
t
TDIH
t
TDOV
t
TDOX
Maximum JTAG TAP Controller Frequency 10 10 MHz
TCK Clock Cycle Time 100 100 ns
TCK Clock High Time 40 40 ns
TCK Clock Low Time 40 40 ns
TMS Setup to TCK Clock Rise 10 10 ns
TMS Hold After TCK Clock Rise 10 10 ns
TDI Setup to TCK Clock Rise 10 10 ns
TDI Hold after TCK Clock Rise 10 10 ns
TCK Clock Low to TDO Valid 20 20 ns
TCK Clock Low to TDO Invalid 0 0 ns
CY7C0430V
CY7C0430V
–133 –100
Min. Max. Min. Max.
t
t
TH
TL
Unit
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TMSS
t
TDIS
t
t
t
TDOX
TMSH
TDIH
t
TDOV
t
TCYC
11
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