Cypress Semiconductor CY7C0251-35AC, CY7C0251-25AI, CY7C0251-25AC, CY7C0251-15AI, CY7C0251-15AC Datasheet
...
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with Sem, Int, Bus
y
CY7C024/0241
CY7C025/0251
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Januar
y 8,
1999
5
1
Features
• True Dual-P orted memory cells which allow
simultaneous reads of the same memory location
• 4K x 16 organizatio n (CY7C024)
• 4K x 18 organizatio n (CY7C0241)
• 8K x 16 organizatio n (CY7C025)
• 8K x 18 organizatio n (CY7C0251)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
CC
= 150 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores inc luded to permit software handshaki ng
between ports
•INT
flag for port-to-po rt commu n ic a ti o n
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Av ailable in 84-pin PLCC and 100-pin TQFP
• Pin-compatibl e and functionally equivalent to
IDT7024/IDT7025
Functional Description
The CY7C024/0241 and CY7C025/0251 are low-power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAM s. Various arbitration schemes are included on the CY7C024/0241
and CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads
and writes to any location in memory . The CY7C024/0241 and
CY7C025/0251 can be utilized as standalone 16-/18-bit dual-port static RAMs or multiple devices can be combined in
order to function as a 32-/36-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing
32-/36-bit or wider memory applications without the need for
separate mast er and s la v e d e vice s o r addi tion al di scret e logic .
Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphic s me mo ry.
Each port has independent control pins: Chip Enable (CE
),
Read or Write Enable (R/W
), and Output Enable (OE). T w o flags
are provided on each port (BUSY
and INT). BUSY signals that the
port is tr yi ng to access the same location cur rently being acce ssed
by the other port. The Inte rrupt Flag (INT
) permits co mmunication
between ports or systems by means of a mail box. The semaphores
are used to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphore logic is comprised
of eight shared latches. Only o ne side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shar ed
resource is in use. An a utomatic power-down feature is controlled
independently on each port by a chip select (CE
) pin.
The CY7C024/0241 and CY7C025/0251 are available in
84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin
Thin Quad Plastic Flatpack (TQFP).
Static RAM wit h Sem , Int, Bu sy
CY7C024/0241
CY7C025/0251
2
v
Notes:
1. BUSY
is an output in master mode and an input in slave mode.
2. I/O0 –I/O8 on the CY7C0241/0251.
3. I/O9 –I/O17 on the CY7C0241/0251.
7C024–1
R/W
L
UB
L
LB
L
CE
L
OE
L
A
0L
R/W
R
UB
R
CE
R
OE
R
CE
L
OE
L
UB
L
UB
R
I/O8L–I/O
15L
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
SEM
L
SEM
R
BUSY
L
INT
L
INT
R
M/S
CONTROL
I/O
LB
L
LB
R
I/O0L–I/O
7L
R/W
L
R/W
R
LB
R
CE
R
OE
R
A
0R
I/O8RI/O
15R
BUSY
R
I/O
0R
I/O
7R
(CY7C025/0251) A
12L
A
12R
(CY7C025/0251)
[1] [1]
Logic Block Diagram
–
–
ADDRESS
DECODER
A
11L
A
11R
[2]
[3]
[2]
[3]
CY7C024/0241
CY7C025/0251
3
Pin Configurations
Notes:
4. A
12L
on the CY7C025/0251.
5. A
12R
on the CY7C025/0251.
L
L
L
7C024–1
Top View
84-Pin PLCC
A
7L
OE
CE
NC
I/O
I/O
I/O
I/O
I/O
I/O
A
6L
A
5L
A
4L
A
3L
A
2L
INT
L
BUSY
L
M/S
BUSY
R
A
1R
A
2R
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
15L
V
CC
I/O
0R
I/O
2R
I/O
1R
I/O
3R
I/O
4R
I/O
5R
AAA
A
A
3R
A
4R
A
5R
A
6R
I/O
6R
I/O
7R
I/O
8R
GND
I/O
14L
A
1L
I/O
R/W
SEM
UB
A
0L
GND
INT
R
A
0R
GND
GND
7L6L5L4L3L
2L
0L
L
L
11L
10L
9L
8L
I/O
1L
V
CC
LB
L
OE
CE
I/O
I/O
I/O
I/O
I/O
A
A
A
A
GND
I/O
R/W
SEM
UB
9R
10R
11R
12R
13R
15R
R
R
R
R
10R
9R
8R
7R
I/O
14R
R
LB
R
A
11R
NC
GND
V
CC
63
62
61
60
59
58
57
56
55
54
535251504948
47
46454443
1234567891011
12
13
14
15
16
17
18
19
20
21
64
65
66
67
68
69
70
71
72
73
74
75767778798081828384
42414039383736353433
32
31
30
29
28
27
26
25
24
23
22
CY7C024/5
[4]
[5]
Top View
100-Pin TQFP
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
15L
V
CC
GND
I/O
1R
I/O
2R
V
CC
9091
A
3L
M/S
BUSY
R
I/O
14L
GND
I/O
12L
I/O
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
I/O9LI/O8LI/O7LI/O6LI/O5LI/O4LI/O3LI/O
2L
GND
I/O1LI/O
0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
7C024–2
I/O
0R
I/O7RI/O8RI/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
Œ
R
R/W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C024/5
R/W
L
[4]
[5]
CY7C024/0241
CY7C025/0251
4
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chi p E nable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A0L–A
11/12L
A0R–A
11/12R
Address
I/O0L–I/O
15/17L
I/O0R–I/O
15/17R
Data Bus Input/Output
SEML SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
INT
L
INT
R
Interrup t F lag
BUSY
L
BUSY
R
Busy Flag
M/S Master or Slave Select
V
CC
Power
GND Ground
Pin Configurations
(continued)
Top Vi ew
100-Pin TQFP
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
I/O
11L
I/O
12L
I/O
16L
V
CC
GND
I/O
1R
I/O
2R
V
CC
9091
A
3L
M/S
BUSY
R
I/O
15L
GND
I/O
13L
I/O
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
I/O9LI/O7LI/O6LI/O5LI/O4LI/O3LI/O
2L
I/O
10L
GND
I/O1LI/O
0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
7C024–3
I/O
0R
I/O
7R
I/O
16R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C0241/0251
I/O
8L
I/O
17L
I/O
8R
I/O
17R
R/W
L
[5]
[4]
CY7C024/0241
CY7C025/0251
5
Maximum Ratings
(Above which the useful lif e m ay be impaired. For user guidelines, not tested.)
Storage Temperature ...... .......... .. ... .......... ..–65
°
C to +150°C
Ambient Temperature with
Power Applied .............................................–55
°
C to +125°C
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC V oltage Applied to Outputs
in High Z State...............................................–0.5V to +7.0V
DC Input Voltage
[6]
......................................... –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................... ............... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................. ............ ...... >200 mA
Selection Guide
7C024/0241–15
7C025/0251–15
7C024/0241–25
7C025/0251–25
7C024/0241–35
7C025/0251–35
7C024/0241–55
7C025/0251–55
Maximum Access Time (ns) 15 25 35 55
Typical Operating Current (mA) 190 170 160 150
Typical Standby Current for I
SB1
(mA) 50 40 30 20
Operating Range
Range
Ambient
T em perature V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Electrical Characteristics
Over the Op erating Range
Parameter Description Test Conditions
7C024/0241–15
7C025/0251–15
7C024/0241–25
7C025/0251–25
UnitMin. Typ. Max. Min. Typ. Max.
V
OH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 V
V
IL
Input LOW Voltage –0.7 0.8 –0. 7 0.8 V
I
IX
Input Leakage Current GND ≤ VI ≤ V
CC
–10 +10 –10 +10 µA
I
OZ
Output Leakage
Current
Output Disabled,
GND ≤ V
O
≤ V
CC
–10 +10 –10 +10 µA
I
CC
Operating Current VCC = Max., I
OUT
= 0 mA,
Outputs Disabled
Com’l 190 300 170 250 mA
Ind 200 320 170 290
I
SB1
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
f = f
MAX
[7]
Com’l 5070 4060mA
Ind 50 70 75
I
SB2
Standby Current
(On e Port TTL Level)
CEL or CER ≥ VIH,
f = f
MAX
[7]
Com’l 120 180 100 150 mA
Ind 120 180 100 170
I
SB3
Standby Current
(Both Ports CMOS
Lev els)
Both Ports CE
and CER ≥
V
CC
– 0.2V, VIN ≥ VCC – 0.2V
or V
IN
≤ 0. 2V, f = 0
[7]
Com’l 3 15 3 15 mA
Ind 3 15 3 15
I
SB4
Standby Current
(Both Ports CMOS
Lev els)
One Port C EL or
CE
R
≥ VCC – 0.2V,
V
IN
≥ V
CC
– 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = f
MAX
[7]
Com’l 110 160 90 130 mA
Ind 110 160 90 150
Notes:
6. Pulse width < 20 ns.
7. f
MAX
= 1/tRC = All inputs cycl ing at f = 1/tRC (except outpu t enab le) . f = 0 means no ad dress or contr ol li nes change . T his applies only to i np uts at C MOS level standby I
SB3
.
CY7C024/0241
CY7C025/0251
6
Electrical Characteristics
Over the Op erating Range (continued)
7C024/0241–35
7C025/0251–35
7C024/0241–55
7C025/0251–55
Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Unit
V
OH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 V
V
IL
Input LOW Voltage –0.7 0.8 –0.7 0.8 V
I
IX
Input Leakage Current GND ≤ VI ≤ V
CC
–10 +10 –10 +10 µA
I
OZ
Output Leakage Current Output Disabled, GND ≤ VO ≤ V
CC
–10 +10 –10 +10 µA
I
CC
Operating Curr ent VCC = Max., I
OUT
= 0 mA,
Outputs Disabled
Com’l 160 230 150 230 mA
Ind 160 260 150 260
I
SB1
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
f = f
MAX
[7]
Com’l 30 50 20 50 mA
Ind 30 65 20 65
I
SB2
Standby Current
(One P ort TTL Level)
CEL or CER ≥ VIH,
f = f
MAX
[7]
Com’l 8 5 135 75 135 mA
Ind 85 150 75 150
I
SB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE
and CER ≥
V
CC
– 0.2V , VIN ≥ VCC – 0.2V
or V
IN
≤ 0.2V, f = 0
[7]
Com’l 3 15 3 15 mA
Ind 3 15 3 15
I
SB4
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CE
R
≥ VCC – 0.2V ,
V
IN
≥ VCC – 0.2V or VIN ≤ 0.2V,
Active P ort Outputs , f = f
MAX
[7]
Com’l 8 0 120 70 120 mA
Ind 80 135 70 135
Capacitance
[8]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 5.0V
10 pF
C
OUT
Output Capacitance 10 pF
AC Test Loads and Waveforms
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
3.0V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
(a) Normal Load(Load
1)
R1= 893
Ω
5
V
OUTPUT
R2= 347
Ω
C= 30
pF
V
TH
=1.4V
OUTPUT
C=
30pF
(b) Thévenin Equivalent (Load 1)
(c)Three-State Delay(Load
3)
C = 30 pF
OUTPUT
Load (Load 2)
7C024–8 7C024–9 7C024–10
7C024–11 7C024–12
R1= 893
Ω
R2= 347
Ω
5V
OUTPUT
C= 5pF
R
TH
=250
Ω
≤
≤
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