Cypress Semiconductor CY7C006-25JI, CY7C006-25JC, CY7C006-25AC, CY7C006-15JC, CY7C006-15AC Datasheet

with Sem, Int, Busy

Features

• True dual-ported memory cells which allow
simultaneous reads of the same memory location

• 16K x 8 organizat ion (CY7C006)

• 16K x 9 organizat ion (CY7C016)

• 0.65-micron CMOS for optim um speed/power

• High-speed access: 15 ns

• Low op e rating pow er: I

= 140 mA (typ.)

CC

• Fully asy nchronous operation

• Automatic power-down

• TTL compatible

• Expandab le dat a bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device

• Busy arbitration scheme provided

• Semaphores i ncluded to per mit software hand shaking
between ports

flag for port-to-port communication

•INT

• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7 C016) TQFP

• Pin compatible and functional equivalent to
IDT7006/IDT7016

Functional Description

The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration

CY7C006
CY7C016

16K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

schemes are included on the CY7C006/016 to handle situa­tions when mul tiple processors access t he same pi ece of d ata.
Two ports are provided, permitting independent, asynchro­nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas­ter/slave dual-port static RAM. An M/S
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi­processor designs, communications status buffering, and du­al-port video/grap hics memory.

Each port has independent control pins: Chip Enable (CE
Read or Write Enable (R/W
flags, BUSY

and INT, are provided on each port. BUSY signals

), and Output Enable (OE). Two

that the port is trying to access the same location currently
being accessed by t he other port. The Int errupt fla g (INT
mits communication between ports or systems b y means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indica te that a shared r esource i s
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re­source is in use. An automatic power-down feature is con­trolled independently on each port by a Chip Enable (CE
or SEM

pin.

The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.

pin is provided for im-

),

) per-

) pin

R/W

CE
OE

I/O

I/O

BUSY

A

A

13L

L

L
L

8L
7L

0L

[1,2]

L

0L

SEM

L

[2]

INT

L

Logic Block Diagram

(7C016)I/O

Notes:

1. BUSY

2. Interrupt: push-pull output and requires no pull-up resistor.

is an output in master mode and an input in slave mode.

ADDRESS

DECODER

CE
OE

R/W

I/O

CONTROL

L

L
L

MEMORY

ARRAY

INTERRUPT

SEMAPHORE

ARBITRATION

M/S

I/O

CONTROL

ADDRESS
DECODER

CE

R

OE

R

R/W

R

SEM
INT

R
[2]

R

R/W

R

CE

R

OE

R

I/O8R(7C016)
I/O

7R

I/O

0R

[1,2]

BUSY

R

A

13R

A

0R

C006-1

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 22, 1999

Pin Configurations

I/O
I/O
I/O
I/O

GND
I/O
I/O

V

GND

I/O
I/O
I/O

V

I/O
I/O
I/O
I/O6

CY7C006
CY7C016

68-Pin PLCC

Top View

)

[3]

8L

L

L

0L

OE

I/O1LI/O

NC(I/O

987654321

10

2L

11

3L
4L

12

5L

13
14

6L

15

7L

16
17

CC

18

0R

19

1R

20

2R

21

CC

22

23

3R

24

4R
5R

25

R

26

2930313233683467356636653764386339

)

R

7R

[3]

OE

8R

I/O

R

R/W

R

R

CE

SEM

CELSEMLR/W

CY7C006

NC

NC(I/O

NC

A

13R

13L

A

GND

CC

V

12RA11RA10R

A

12LA11LA10LA9LA8LA7LA6L

A

62

40

4127422843

6R

A9RA8RA7RA

61

60

A

5L

59

A

4L

58

A

3L

57

A

2L

56

A

1L

55

A

0L

54

INT

L

BUSY

53
52
51
50
49

48
47
46
45
44

5R

A

GND
M/S
BUSY

INT

A

0R

A

1R

A

2R

A

3R

A

4R

L

R

R

C006-2

Note:

3. I/O for CY7C016 only.

I/O
I/O

I/O
I/O
GND
I/O
I/O

V

GND
I/O
I/O
I/O

V
I/O
I/O
I/O

64-Pin TQFP

Top View

L

L

L

0L

OE

I/O1LI/O

R/W

2L
3L

4L
5L

1
2
3
4

13L

CC

V

A

CELSEM

12LA11LA10LA9LA8LA7LA6L

A

5

6L
7L

CC

6
7
8

CY7C006

9

0R
1R
2R

CC

3R
4R
5R

10
11
12
13
14

15
16

17641863196220612160225923582457255626552754285329523051315032

R

R

R

R

6R

7R

OE

I/O

I/O

R/W

SEM

CE

A

13R

A

GND

12RA11RA10R

A9RA8RA7RA

5L

A

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

5R

6R

A

A

4L

A

3L

A

2L

A

1L

A

0L

INT
BUSY
GND
M/S

BUSY
INT
A

0R

A

1R

A

2R

A

3R

A

4R

L

L

R

R

C006-3

2

CY7C006
CY7C016

Pin Configurations

(continued)

NC

I/O

2L

I/O

3L

I/O

4L

I/O

5L

GND

I/O

6L

I/O

7L

V

CC

NC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

NC

80-Pin TQFP

Top View

L

L

8L

1L

OE

I/O0LI/O

I/O

8079787776757473727170696867666465

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

16
17
18
19
20

2122232425262728293031323334353736

R

R

R

R

7R

I/O

I/O

8R

OE

R/W

SEM

CE

NC

CELSEMLR/W

NCANC

13L

A

NC

CY7C016

13R

GND

12LA11LA10LA9LA8LA7LA6L

CC

V

A

12RA11RA10R

A

A9RA8RA7RA

6R

NC

636261

383940

5R

NC

A

NC

NC

NC

60

A

5L

59

A

4L

58

A

3L

57

A

2L

56

A

1L

55

A

0L

54

INT
BUSY
GND
M/S

BUSY
INT

A

0R

A

1R

A

2R

A

3R

A

4R

NC
NC

C006-4

L

L

R

R

53
52

51
50
49
48
47
46

45
44
43
42
41

Pin Definitions

Left Port Right Port Description

I/O

0L–7L(8L)

A

0L–13L

CE

L

OE

L

R/W

L

SEML SEM

INT

L

BUSY

L

M/S Master or Slave Select
V

CC

GND Ground

I/O

0R–7R(8R)

A

0R–13R

CE

R

OE

R

R/W

INT

R

BUSY

Data Bus Input/Output
Address Lines
Chi p E nable
Output Enable

R

R

Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-

phores. The three least significant bits of the address lines will dete rmine
which semaphore to write or read. The I/O
semaphore. Semaph ores are requested by writi ng a 0 into the respective
location.

Interrupt Flag. INTL is set when right port writes location 3FFE and is
cleared when left port reads loc ation 3FFE. I NT
location 3FFF and is clear ed when right port reads location 3FFF.

R

Busy Flag

Power

pin is used when writing to a

0

is set when left port writes

R

3

CY7C006
CY7C016

Selection G uide

7C006-15
7C016-15

Maximum Access Time (ns) 15 25 35 55
Maximum Operating

260 220 210 200

Current (mA)
Maximum Standby

Current for I

SB1

(mA)

70 60 50 40

7C006-25
7C016-25

7C006-35
7C016-35

7C006-55
7C016-55

Maximum Ratings

(Abov e which the useful lif e m ay be impaired. For user guide­lines, not tested.)

Storage Temperature .............. ...................–65°C to +1 5 0°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State............................................... –0.5V to +7.0V

[4]

DC Input Voltage

Electrical Characteristics

......................................... –0.5V to +7.0V

Over the Operating Range

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ......................... .. ............... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............. ............ ............ ............ ... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

7C006-15
7C016-15

Ambient

Temperature V

7C006-25
7C016-25

CC

Parameter Description T est Conditions Min. Typ. Max. Min. Typ. Max. Unit

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

4. Pulse width < 20 ns.

5. f

MAX

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND ≤ VI ≤ V

CC

Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V
Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(One Port CMOS Level)

= 1/tRC = All inputs c ycling at f = 1/tRC (except output enab le) . f = 0 mea ns no add ress or contr ol lines change . T his appl ies onl y to inpu ts at C MOS le v el s tandby I

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

MAX

MAX

[5]

[5]

Both Ports
CE

and CER ≥ VCC – 0.2V,

V

≥ VCC – 0.2V

IN

or V

≤ 0.2V, f = 0

IN

One Port
CE

or CER ≥ VCC – 0.2V,

L

V

≥ VCC – 0.2V or

IN

V

≥ 0. 2V, Active

IN

Port Outputs, f = f

OUT

= 0 mA

[5]

[5]

MAX

Com’l 170 260 160 220 mA
Ind 160 270
Com’l 50 70 40 60 mA
Ind 40 75
Com’l 110 170 90 130 mA
Ind 90 150
Com’l 3 15 3 15 mA
Ind 3 15

Com’l 100 150 80 120 mA
Ind 80 130

–10 +10 –10 +10
–10 +10 –10 +10

CC

µA
µA

SB3

.

4

CY7C006
CY7C016

Electrical Characteristics

(continued)

7C006-35
7C016-35

7C006-55
7C016-55

Parameter Description T est Conditions Min. Typ. Max. Min. Typ. Max. Unit

V
V
V
V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

OH
OL
IH
IL

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND ≤ VI ≤ V

CC

Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V
Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(One Port CMOS Level)

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

MAX

MAX

[5]

[5]

Both Ports
CE

and CER ≥ VCC – 0.2V,

V

≥ VCC – 0.2V

IN

or V

≤ 0.2V, f = 0

IN

One Port
CE

or CER ≥ VCC – 0.2V,

L

V

≥ VCC – 0.2V or

IN

V

≤ 0. 2V, Active

IN

Port Outputs, f = f

OUT

= 0 mA

[5]

[5]

MAX

Com’l 150 210 140 200 mA
Ind 150 250 140 240
Com’l 30 50 20 40 mA
Ind 30 65 20 55
Com’l 80 120 70 100 mA
Ind 80 130 70 115
Com’l 3 15 3 15 mA
Ind 3 15 3 15

Com’l 70 100 60 90 mA
Ind 70 110 60 95

–10 +10 –10 +10
–10 +10 –10 +10

CC

µA
µA

Capacitance

[6]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 10 pF

CC

AC Test Loads and Waveforms

5V

R1=893

R2=347

C006-5

C006-8

Ω

Ω

OUTPUT

C= 30

pF

(a) Normal Load (Load 1)

OUTPUT

C = 30 pF

Load (Load 2)

Note:

6. Tested initially and after any design or process changes that may affect these parameters.

3.0V

GND

OUTPUT

C=30 pF

(b) ThéveninEquivalent (Load)

ALL INPUT PULSES

90%

≤

10%

3ns

=250

R

TH

10 pF

5V

R1=893

R2=347

Ω

Ω

Ω

=1.4V

V

TH

90%

10%

≤

OUTPUT

C= 5pF

C006-6 C006-7

ns

3

C006-9

(c) Three-State Delay (Load 3)

5