Cypress Semiconductor CY7B9911V-7JC, CY7B9911V-5JC Datasheet

High-Speed Low-Voltage Programmable Skew Clock Buffer

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 110-MHz output operation

• User-selectable output functions
—Selectable skew to 18 ns

—Inverted and non-inverted
—O peration at

1

—O peration at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input-to-output delay

• 50% duty-cycle outputs

LVTTL outputs drive 50Ω terminated lines

•

Operates from a single 3.3V supply

•

• Low op e rating curre n t

• 32-pin PLCC package

• Jitter < 200 ps peak-to-pe ak (< 25 ps RMS)

Functional Description

The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage
Programmable Skew Clock Buffer (LVPSCB) offers user-

and

⁄

2

1

input frequency

⁄

4

CY7B9911V

3.3V RoboClock+

(LV-PSCB)

selectabl e control over system clock functi ons. Thes e multi ple­output clock drivers provide the system integrator with func­tions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated
transmission lines with impedances as low as 50Ω while deliv­ering mi nima l and s pecif ied o utpu t sk ews and fu ll-s wi ng lo gic l e vel s
(L VTTL).

Each output can be hardwired to one of nine delay o r f unction
configurations. Delay increments of 0.7 to 1.5 ns are deter­mined by the operat ing freque ncy with outputs ab le to ske w up
to ±6 time units from their nominal “zero” skew position. The com­pletely integrated PLL allows external load and transmission
line dela y effects to be canceled. When t his “ ze ro del a y” capa ­bility of the LVPSCB is combined with the selectable output
skew f unctions, the user can create output-to-output delays of
up to ±12 tim e u nits.

Divide-by-t wo and div ide-by- four output func tions are pro vided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi­plied by two or four at the clock destination. This facility mini­mizes clock distribution difficulty while allowing maximum sys­tem clock speed and flexibility.

Logic Block Diagram Pin Configuration

TEST

PLCC

PHASE

FB

REF

FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

FREQ

DET

SELECT

INPUTS
(THREE

LEVEL)

FILTER

VCO AND

TIME UNIT

GENERATOR

SKEW

SELECT

MATRIX

7B9911V–1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

3F1
4F0

4F1

V

CCQ

V

CCN

4Q1

4Q0
GND
GND

5
6

7
8
9

10
11

12
13

3F0

3Q1

FS

V

CY7B9911V

CCNVCCN

3Q0

CCQ

17161514 18 19 20

REF

GND

TEST

2F1

1234323130

FB

2Q1

V

2F0

29

GND

28

1F1

27

1F0

26
25

V

CCN

24

1Q0

23

1Q1

22

GND
GND

21

2Q0

7B9911V–2

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1, 1999

CY7B9911V

3.3V Rob oC lock+

Pin Definitions

Signal Name I/O Description

REF I Reference fre quency input. This input supplie s the frequency and timing against which all fun ctional

FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three-level frequency rang e select. See Table 1.
1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Tabl e 2 .
2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Tabl e 2 .
3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Tabl e 2 .
4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Tabl e 2 .
TEST I Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V
V

CCN
CCQ

PWR Power supply for output drivers.
PWR Power supply for internal circuitry.

GND PWR Ground.

variation is measured.

Block Diagram Description

Phase Frequency Detector and Filter

These two bloc ks accep t inputs fr om the Ref erence F requency
(REF) input and the F eedbac k (FB) input and generate co rrec­tion information to control the frequency of the Voltage­Controlled Oscillator (VCO). These blocks, along with the
VCO, form a Phase-Lock ed Loop (PLL) that tracks the incom­ing REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator t o create discrete t ime units that are selected in the
skew selec t matrix. The operat ional ran ge of the VCO is deter­mined by the FS control pin. The time unit (t
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.

T able 1. Frequency Range Select and tU Calculation

f

(MHz)

FS

[2, 3]

NOM

t

U

1

=

------ ----------- ------ ­f

NOM

where N =

N

×

LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 110 16 62.5

) is determined

U

[1]

Approximate

Frequency (MHz) At

Which t

= 1.0 nsMin. Max.

U

Skew Select Matrix

The skew sel ect matrix is comprised of four independent sec­tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function selec t
(xF0, xF1) inputs. Table 2 below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0t

selected.

U

T able 2. Programmable Skew Configurations

[1]

Function Selects Output Functions

1F1, 2F1,

3F1, 4F1

LOW LOW –4t
LOW MID –3t
LOW HIGH –2t
MID LOW –1t
MID MID 0t
MID HIGH +1t
HIGH LOW +2t
HIGH MID +3t
HIGH HIGH +4t

1F0, 2F0,

3F0, 4F0

1Q0, 1Q1,

2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

Divide by 2 Divide b y 2

U
U
U
U

U

U
U
U
U

–6t

U

–4t

U

–2t

U

0t

U

+2t

U

+4t

U

+6t

U

Divide by 4 Inverted

–6t
–4t
–2t

0t
+2t
+4t
+6t

U
U
U

U

U
U
U

Notes:

1. For all three-state inputs, HIGH indicates a connection to V
circuitry holds an unconnected input to V

2. The level to be set on FS is determined by the “normal” operating frequency (f
frequency (f
REF and FB inputs will be f
is configured for a frequency multiplication by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 2.8V.

) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the

NOM

when the output connected to FB is undivided. The frequency of the REF and FB inputs will be f

NOM

CC

/2.

, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

CC

) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal

NOM

2

NOM

/2 or f

/4 when the part

NOM

1Fx
2Fx

(N/A)

3Fx
4Fx

LM

FBInput

REFInput

– 6t

CY7B9911V

3.3V Rob oC lock+

U

U

U

U

U

U

– 6t

– 5t

– 4t

– 3t

– 2t

0

0

0

t

t

U

0

t

t

– 1t

0

0

t

t

t 0t

U

+1t

+2tU+3tU+4tU+5tU+6t

0

t 0t 0t 0t 0t

U

0

LL

LM

LH

ML
MM
MH

HL
HM

HH

(N/A)
(N/A)
(N/A)

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

HH

– 4t

U

– 3t

U

– 2t

U

– 1t

U

0t

+1t

U

+2t

U

+3t

U

+4t

U

+6t

U

DIVIDED

INVERT

U

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

Test Mode

The TEST input is a three-level input. In normal system oper­ation, this pin is connected to ground, allowing the
CY7B9911V to operate as explained briefly above (for testing
purposes, any of the three-level inputs can have a removable
jumper to grou nd, or be tied LOW th rough a 100Ω resistor . This
will allow an external t ester to change the state of these pins.)

If the TEST input i s f orced to its MID or HIGH stat e, t he de vic e
will operate with its internal phase locked loop disconnected,
and input l eve ls sup plied to REF wi ll direc tly cont rol all o utputs.
Relative output to output functions are the same as in normal
mode.

In contras t with normal oper ation (TEST t ied LO W). All outp uts
will functi on based only on the connecti on of thei r own funct ion
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.

7B9911V–3

[4]

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

°

Storage Temperature ................................. –65

C to +150°C

Ambient Temperature with

Power Applied............................................. –55

°

C to +125°C

Supply Voltage to Ground P otential............ .. ..–0.5V to +7. 0V

DC Input Voltage ............................................–0.5V to +7. 0V

Output Current into Outputs (LOW).............................64 mA

Static Discharge Voltage ......................... ............... ...>2001 V

(per MIL-STD-883, Method 3015)

Latch-Up Current..................................................... >200 mA

Operating Range

Ambient

Range

Temperature

Commercial 0°C to +70°C 3.3V ± 10%

Note:

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
MID).

3

V

CC

CY7B9911V

3.3V Rob oC lock+

Electrical Characteristics

Over the Operating Range

[5]

CY7B9911V

Parameter Description Tes t Condi ti ons Min. Max. Unit

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltag e VCC = Min., IOH = –18 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 35 mA 0.45 V
Input HIG H Voltage

(REF and FB inputs only)
Input LOW Voltage

2.0 V

CC

–0.5 0.8 V

(REF and FB inputs only)

V

V

V

I

I

I

IHH

IMM

ILL

IH

IL

IHH

Three-Level Input HIGH
Voltage (Test, FS, xFn)

Three-Level Input MID
Voltage (Test, FS, xFn)

Three-Level Input LOW
Voltage (Test, FS, xFn)

[6]

[6]

[6]

Input HIGH Leakage Current
(REF and FB inputs only)

Input LOW Leakage Current
(REF and FB inputs only)

Input HIG H Current

Min. ≤ VCC ≤ Max. 0.87 * VCC V

Min. ≤ VCC ≤ Max. 0.47 * V

CC

CC

0.53 * V

Min. ≤ VCC ≤ Max. 0.0 0.13 * V

VCC = Max., VIN = Max. 20

VCC = Max., VIN = 0.4V –20

VIN = V

CC

200

CC

CC

(Test, FS, xFn)

I

IMM

I

ILL

I

OS

I

CCQ

I

CCN

PD Power Dissipation per

Capacitance

Input MID C u rrent
(Test, FS, xFn)

Input LOW Current
(Test, FS, xFn)

Short Circuit Current

[7]

Operating Current Used by
Internal Circuitry

Output Buffer Curr ent per
Output Pair

Output Pair

[10]

[8]

[9]

VIN = VCC/2 –50 50

VIN = GND –200

VCC = MAX, V
V

= V

CCN

All Inp u t S e lects Open
V

= V

CCN

I

= 0 mA

OUT

Input Selects Open, f
V

= V

CCN

I

= 0 mA

OUT

Input Selects Open, f

= GND (25° only) –200 mA

OUT

CCQ

= Max.,

Com’l 95 mA
Mil/Ind 100

= Max.,

CCQ

MAX

CCQ

= Max.,

MAX

104 mW

19 mA

Parameter Description Test Conditions Max. Unit

C

IN

Notes:

5. See the last page of this specification for Group A subgroup testing information.

6. These inputs are normally wired to V
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
before all data sheet limits are achieved.

7. CY7B9911V should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room tempe rature only.

8. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9911V:I
Where

F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C

9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1
See note 8 for variable definition.

10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 10 pF

, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold

CC

= [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1

CCN

LOCK

V

V

V

V

µA

µA

µA

µA

µA

time

4