Cypress Semiconductor CY7B9911V-7JC, CY7B9911V-5JC Datasheet

High-Speed Low-Voltage Programmable Skew Clock Buffer

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 110-MHz output operation

• User-selectable output functions
—Selectable skew to 18 ns

—Inverted and non-inverted
—O peration at

1

—O peration at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input-to-output delay

• 50% duty-cycle outputs

LVTTL outputs drive 50Ω terminated lines

•

Operates from a single 3.3V supply

•

• Low op e rating curre n t

• 32-pin PLCC package

• Jitter < 200 ps peak-to-pe ak (< 25 ps RMS)

Functional Description

The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage
Programmable Skew Clock Buffer (LVPSCB) offers user-

and

⁄

2

1

input frequency

⁄

4

CY7B9911V

3.3V RoboClock+

(LV-PSCB)

selectabl e control over system clock functi ons. Thes e multi ple­output clock drivers provide the system integrator with func­tions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated
transmission lines with impedances as low as 50Ω while deliv­ering mi nima l and s pecif ied o utpu t sk ews and fu ll-s wi ng lo gic l e vel s
(L VTTL).

Each output can be hardwired to one of nine delay o r f unction
configurations. Delay increments of 0.7 to 1.5 ns are deter­mined by the operat ing freque ncy with outputs ab le to ske w up
to ±6 time units from their nominal “zero” skew position. The com­pletely integrated PLL allows external load and transmission
line dela y effects to be canceled. When t his “ ze ro del a y” capa ­bility of the LVPSCB is combined with the selectable output
skew f unctions, the user can create output-to-output delays of
up to ±12 tim e u nits.

Divide-by-t wo and div ide-by- four output func tions are pro vided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi­plied by two or four at the clock destination. This facility mini­mizes clock distribution difficulty while allowing maximum sys­tem clock speed and flexibility.

Logic Block Diagram Pin Configuration

TEST

PLCC

PHASE

FB

REF

FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

FREQ

DET

SELECT

INPUTS
(THREE

LEVEL)

FILTER

VCO AND

TIME UNIT

GENERATOR

SKEW

SELECT

MATRIX

7B9911V–1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

3F1
4F0

4F1

V

CCQ

V

CCN

4Q1

4Q0
GND
GND

5
6

7
8
9

10
11

12
13

3F0

3Q1

FS

V

CY7B9911V

CCNVCCN

3Q0

CCQ

17161514 18 19 20

REF

GND

TEST

2F1

1234323130

FB

2Q1

V

2F0

29

GND

28

1F1

27

1F0

26
25

V

CCN

24

1Q0

23

1Q1

22

GND
GND

21

2Q0

7B9911V–2

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1, 1999

CY7B9911V

3.3V Rob oC lock+

Pin Definitions

Signal Name I/O Description

REF I Reference fre quency input. This input supplie s the frequency and timing against which all fun ctional

FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three-level frequency rang e select. See Table 1.
1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Tabl e 2 .
2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Tabl e 2 .
3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Tabl e 2 .
4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Tabl e 2 .
TEST I Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V
V

CCN
CCQ

PWR Power supply for output drivers.
PWR Power supply for internal circuitry.

GND PWR Ground.

variation is measured.

Block Diagram Description

Phase Frequency Detector and Filter

These two bloc ks accep t inputs fr om the Ref erence F requency
(REF) input and the F eedbac k (FB) input and generate co rrec­tion information to control the frequency of the Voltage­Controlled Oscillator (VCO). These blocks, along with the
VCO, form a Phase-Lock ed Loop (PLL) that tracks the incom­ing REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator t o create discrete t ime units that are selected in the
skew selec t matrix. The operat ional ran ge of the VCO is deter­mined by the FS control pin. The time unit (t
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.

T able 1. Frequency Range Select and tU Calculation

f

(MHz)

FS

[2, 3]

NOM

t

U

1

=

------ ----------- ------ ­f

NOM

where N =

N

×

LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 110 16 62.5

) is determined

U

[1]

Approximate

Frequency (MHz) At

Which t

= 1.0 nsMin. Max.

U

Skew Select Matrix

The skew sel ect matrix is comprised of four independent sec­tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function selec t
(xF0, xF1) inputs. Table 2 below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0t

selected.

U

T able 2. Programmable Skew Configurations

[1]

Function Selects Output Functions

1F1, 2F1,

3F1, 4F1

LOW LOW –4t
LOW MID –3t
LOW HIGH –2t
MID LOW –1t
MID MID 0t
MID HIGH +1t
HIGH LOW +2t
HIGH MID +3t
HIGH HIGH +4t

1F0, 2F0,

3F0, 4F0

1Q0, 1Q1,

2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

Divide by 2 Divide b y 2

U
U
U
U

U

U
U
U
U

–6t

U

–4t

U

–2t

U

0t

U

+2t

U

+4t

U

+6t

U

Divide by 4 Inverted

–6t
–4t
–2t

0t
+2t
+4t
+6t

U
U
U

U

U
U
U

Notes:

1. For all three-state inputs, HIGH indicates a connection to V
circuitry holds an unconnected input to V

2. The level to be set on FS is determined by the “normal” operating frequency (f
frequency (f
REF and FB inputs will be f
is configured for a frequency multiplication by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 2.8V.

) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the

NOM

when the output connected to FB is undivided. The frequency of the REF and FB inputs will be f

NOM

CC

/2.

, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

CC

) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal

NOM

2

NOM

/2 or f

/4 when the part

NOM

1Fx
2Fx

(N/A)

3Fx
4Fx

LM

FBInput

REFInput

– 6t

CY7B9911V

3.3V Rob oC lock+

U

U

U

U

U

U

– 6t

– 5t

– 4t

– 3t

– 2t

0

0

0

t

t

U

0

t

t

– 1t

0

0

t

t

t 0t

U

+1t

+2tU+3tU+4tU+5tU+6t

0

t 0t 0t 0t 0t

U

0

LL

LM

LH

ML
MM
MH

HL
HM

HH

(N/A)
(N/A)
(N/A)

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

HH

– 4t

U

– 3t

U

– 2t

U

– 1t

U

0t

+1t

U

+2t

U

+3t

U

+4t

U

+6t

U

DIVIDED

INVERT

U

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

Test Mode

The TEST input is a three-level input. In normal system oper­ation, this pin is connected to ground, allowing the
CY7B9911V to operate as explained briefly above (for testing
purposes, any of the three-level inputs can have a removable
jumper to grou nd, or be tied LOW th rough a 100Ω resistor . This
will allow an external t ester to change the state of these pins.)

If the TEST input i s f orced to its MID or HIGH stat e, t he de vic e
will operate with its internal phase locked loop disconnected,
and input l eve ls sup plied to REF wi ll direc tly cont rol all o utputs.
Relative output to output functions are the same as in normal
mode.

In contras t with normal oper ation (TEST t ied LO W). All outp uts
will functi on based only on the connecti on of thei r own funct ion
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.

7B9911V–3

[4]

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

°

Storage Temperature ................................. –65

C to +150°C

Ambient Temperature with

Power Applied............................................. –55

°

C to +125°C

Supply Voltage to Ground P otential............ .. ..–0.5V to +7. 0V

DC Input Voltage ............................................–0.5V to +7. 0V

Output Current into Outputs (LOW).............................64 mA

Static Discharge Voltage ......................... ............... ...>2001 V

(per MIL-STD-883, Method 3015)

Latch-Up Current..................................................... >200 mA

Operating Range

Ambient

Range

Temperature

Commercial 0°C to +70°C 3.3V ± 10%

Note:

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
MID).

3

V

CC

CY7B9911V

3.3V Rob oC lock+

Electrical Characteristics

Over the Operating Range

[5]

CY7B9911V

Parameter Description Tes t Condi ti ons Min. Max. Unit

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltag e VCC = Min., IOH = –18 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 35 mA 0.45 V
Input HIG H Voltage

(REF and FB inputs only)
Input LOW Voltage

2.0 V

CC

–0.5 0.8 V

(REF and FB inputs only)

V

V

V

I

I

I

IHH

IMM

ILL

IH

IL

IHH

Three-Level Input HIGH
Voltage (Test, FS, xFn)

Three-Level Input MID
Voltage (Test, FS, xFn)

Three-Level Input LOW
Voltage (Test, FS, xFn)

[6]

[6]

[6]

Input HIGH Leakage Current
(REF and FB inputs only)

Input LOW Leakage Current
(REF and FB inputs only)

Input HIG H Current

Min. ≤ VCC ≤ Max. 0.87 * VCC V

Min. ≤ VCC ≤ Max. 0.47 * V

CC

CC

0.53 * V

Min. ≤ VCC ≤ Max. 0.0 0.13 * V

VCC = Max., VIN = Max. 20

VCC = Max., VIN = 0.4V –20

VIN = V

CC

200

CC

CC

(Test, FS, xFn)

I

IMM

I

ILL

I

OS

I

CCQ

I

CCN

PD Power Dissipation per

Capacitance

Input MID C u rrent
(Test, FS, xFn)

Input LOW Current
(Test, FS, xFn)

Short Circuit Current

[7]

Operating Current Used by
Internal Circuitry

Output Buffer Curr ent per
Output Pair

Output Pair

[10]

[8]

[9]

VIN = VCC/2 –50 50

VIN = GND –200

VCC = MAX, V
V

= V

CCN

All Inp u t S e lects Open
V

= V

CCN

I

= 0 mA

OUT

Input Selects Open, f
V

= V

CCN

I

= 0 mA

OUT

Input Selects Open, f

= GND (25° only) –200 mA

OUT

CCQ

= Max.,

Com’l 95 mA
Mil/Ind 100

= Max.,

CCQ

MAX

CCQ

= Max.,

MAX

104 mW

19 mA

Parameter Description Test Conditions Max. Unit

C

IN

Notes:

5. See the last page of this specification for Group A subgroup testing information.

6. These inputs are normally wired to V
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
before all data sheet limits are achieved.

7. CY7B9911V should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room tempe rature only.

8. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9911V:I
Where

F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C

9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1
See note 8 for variable definition.

10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 10 pF

, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold

CC

= [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1

CCN

LOCK

V

V

V

V

µA

µA

µA

µA

µA

time

4

3.3V Rob oC lock+

AC Test Loads and Waveforms

V

CC

R1=100

R1

R2=100
C

=30pF

C

L

L

(Inclu des fixture an d pr o be cap ac itance)

R2

7B9911V–4

V

th

2.0V

=1.5V

0.8V

0.0V
1ns

≤

TTL ACTest Load TTL Input TestWaveform

3.0V

CY7B9911V

2.0V
V

=1.5V

th

0.8V

1ns

≤

7B9911V–5

Switching Characteristics

Over th e Op era t ing Ran ge

[2, 11]

CY7B9911V–5

Parameter Description Min. Typ. Max. Unit

[13, 14]

[12]

[1, 2]

[1, 2]

[1, 2 , 3]

[12]

[13, 17]

[13, 17]

[13, 17]

[13, 17]

15 30 MHz
25 50
40 110

0.1 0.25 ns

0.25 0.5 ns

0.6 0.7 ns

0.5 1.0 ns

0.5 0.7 ns

0.5 1.0 ns

–1.0 0.0 +1.0 ns

0.15 1.0 1.5 ns

0.15 1.0 1.5 ns

delay has been selected when all are

U

SKEW2

and t

SKEW4

specifications.

is measured at 2.0V . t

PWH

1.25 ns

2.5 ns
3 ns

0.5 ms

25 ps

200 ps

PWL

f

NOM

Operating Cloc k
Freque ncy in MHz

FS = LOW
FS = MID
FS = HIGH

t

RPWH

t

RPWL

t

U

t

SKEWPR

t

SKEW0

t

SKEW1

t

SKEW2

t

SKEW3

t

SKEW4

t

DEV

t

PD

t

ODCV

t

PWH

t

PWL

t

ORISE

t

OFALL

t

LOCK

t

JR

Notes:

11. T est measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). T est c on dit ion s ass ume s ign al tr ans it io n t im es of 2 ns or less and output loading as shown
in the AC T est Loads and Waveforms unless otherwise specified.

12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
loaded with 30 pF and terminated with 50Ω to V

14. t

SKEWPR

15. t

SKEW0

16. CL=0 pF . F or CL=30 pF, t

17. There are three classes of outputs: Nominal (multiple of t
2 or Divide-by-4 mode).

18. t

is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)

DEV

19. t

ODCV

20. Specified with outputs loaded with 30 pF for the CY7B9911V–5 and –7 devices. Devices are terminated through 50Ω to VCC/2.t
measured at 0.8V.

21. t

ORISE

22. t

LOCK

measured from the application of a new signal or frequency at REF or FB until tPD is with in s pe c ifi e d lim i t s .

REF Pulse W i dth HIG H 5.0 ns
REF Pulse W i dth LOW 5.0 ns
Programmable Skew Unit See Table 1
Zero Output Matched-Pair Skew (XQ0, XQ1)
Zero Output Skew (All Outputs)

[13, 15]

Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
Device-to-Device Skew

[12, 18]

Propagation Delay, REF Rise to FB Rise –0.5 0.0 +0.5 ns
Output Duty Cycle Variation
Output HIGH Time Deviation fr om 50%
Output LOW Time De viation from 50%
Output R ise Time
Outp ut Fall Time
PLL Lock Time

[20, 21]

[20, 21]

[22]

Cycle-to-C ycle Output
Jitter

is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.

is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.

is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

and t

is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is

measured between 0.8V and 2.0V .

OFALL

SKEW0

=0.35 ns.

[19]

/2 (CY7B9911V).

CC

[20]

[20]

RMS
Peak-to-Peak

delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-

U

is

5

CY7B9911V

3.3V Rob oC lock+

Switching Characteristics

Over th e Op era t ing Ran ge

[2, 11]

(continued)

CY7B9911V–7

Parameter Description Min. Typ. Max. Unit

[13, 14]

[12]

[1, 2]

[1, 2]

[1, 2 , 3]

[12]

[13, 17]

[13, 17]

[13, 17]

[13, 17]

15 30 MHz
25 50
40 110

0.1 0.25 ns

0.3 0.75 ns

0.6 1.0 ns

1.0 1.5 ns

0.7 1.2 ns

1.2 1.7 ns

1.65 ns

–1.2 0.0 +1.2 ns

3 ns

3.5 ns

0.15 1.5 2.5 ns

0.15 1.5 2.5 ns

0.5 ms
25 ps

200 ps

f

NOM

t

RPWH

t

RPWL

t

U

t

SKEWPR

t

SKEW0

t

SKEW1

t

SKEW2

t

SKEW3

t

SKEW4

t

DEV

t

PD

t

ODCV

t

PWH

t

PWL

t

ORISE

t

OFALL

t

LOCK

t

JR

Operating Cloc k
Freque ncy in MHz

FS = LOW
FS = MID

FS = HIGH
REF Pulse W i dth HIG H 5.0 ns
REF Pulse W i dth LOW 5.0 ns
Programmable Skew Unit See Table 1
Zero Output Matched-Pair Skew (XQ0, XQ1)
Zero Output Skew (All Outputs)

[13, 15]

Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
Device-to-Device Skew

[12, 18]

Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 ns
Output Duty Cycle Variation
Output HIGH Time Deviation fr om 50%
Output LOW Time De viation from 50%
Output R ise Time
Outp ut Fall Time
PLL Lock Time

[20, 21]

[20, 21]

[22]

Cycle-to-C ycle Output
Jitter

[19]

[20]

[20]

RMS

Peak-to-Peak

6

AC Timing Diagrams

CY7B9911V

3.3V Rob oC lock+

REF

FB

Q

OTHERQ

INVERTED Q

REF DIVIDED BY 2

t

REF

t

RPWH

t

PD

t

SKEWPR,

t

SKEW0,1

t

SKEW3,4

t

ODCV

t

SKEW3,4

t

RPWL

t

SKEW2

t

ODCV

t

SKEWPR,

t

SKEW0,1

t

SKEW2

t

SKEW3,4

t

JR

REF DIVIDED BY 4

t

SKEW1,3, 4

t

SKEW2,4

7B9911V–8

7

Operational Mode Descriptions

CY7B9911V

3.3V Rob oC lock+

REF

FB

SYSTEM
CLOCK

REF
FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

TEST

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

LENGTH L1 = L2 = L3= L4

Figure 2. Zero-Skew and/or Zero-Delay Clock Driver

Figure 2 shows the LVPSCB configured as a zero-skew clock
buffer. In this mode the CY7B9911V can be used as th e basis
for a low-skew clock distribution tree. When all of the function
select inputs (xF0, xF1) are left open, the outputs are aligned
and may each drive a terminated transmi ssion line to an inde-

REF

LOAD

Z

L1

L2

L3

L4

0

LOAD

Z

0

LOAD

Z

0

LOAD

Z

0

7B9911V–9

pendent load. The FB input can be tied to any output in this
configuration and the operating frequency range is selected
with the FS pin. The low-skew specification, coupled with the
ability to drive termin ated transmi ssion lin es (with impedances
as low as 50Ω), allows eff ici ent printed circuit board design.

LOAD

FB

SYS­TEM
CLOCK

REF
FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

TEST

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

LENGTH L1= L2

L3< L2by 6 inches
L4> L2by 6 inches

Figure 3. Programmable-Skew Clock Driver

Figure 3 shows a conf iguration t o equalize ske w between met­al traces of different lengths. In addition to low skew between
outputs, the LVPSCB can be programmed to stagger the tim­ing of its outputs. The four groups of output pairs can each be
programmed to different output timing. Skew timing can be
adjusted ov er a wide range in sm all incre ments with t he appro­priate strapp ing of the funct ion select pi ns. In this conf igurat ion
the 4Q0 output is fed back to FB and configur ed f or z ero sk e w .
The other three pairs of outputs are programmed to yield dif­ferent skews relative to the feedback. By advancing the clock
signal on the longer traces or retarding the clock signal on
shorter traces, all loads can receive the clock pulse at the
same time.

Z

L1

L2

L3

L4

0

LOAD

Z

0

LOAD

Z

0

LOAD

Z

0

7B9911V–10

In this illustr atio n the FB input is connected to an output with
0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn­chronizes t he FB and REF inputs and ali gns thei r rising ed ges
to insure that all outputs have precise phase alignment.

Clock skews can be advanced by ±6 time units (t
an outpu t sel ec ted f or z er o sk ew as the feed ba ck . A wid er range of

) when using

U

delays is possible if the output conne cted to FB is also skewed.
Since “Zero Skew”, +t
groups, and since the PLL aligns the rising edges of REF and FB,

, and –tU are defined relative to output

U

it is possible to create wider output skews by proper selection of the
xFn inputs. For example a +10 t
achieved by connect ing 1Q0 to FB and setting 1F0 = 1F1 = GND,
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 t

between REF and 3Qx can be

U

and 3Qx

U

8

CY7B9911V

7B9911V–13

FB
REF
FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

TEST

REF

20 MHz

5 MHz

10 MHz

20 MHz

3.3V Rob oC lock+

skews to +6 t

, a total of +10 tU skew is realized.) Many other con-

U

figur a ti ons ca n be rea li ze d b y skewing both the ou t pu t used as the
FB input and skewing the other outputs.

REF

FB
REF

FS
4F0

4F1
3F0

3F1
2F0

2F1
1F0

1F1
TEST

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

7B9911V–11

Figure 4. Inverted Output Connections

Figure 4 shows an example of the invert function of the
LVPSCB. In this example the 4Q0 o utput us ed as the FB i nput
is programmed for invert (4F0 = 4F1 = HIGH) while the other
three pairs of outputs are programmed for zero skew. When
4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted
zero phase outputs. The PLL aligns the rising edge of the FB
input with the rising edge of th e REF. This causes the 1Q, 2Q,
and 3Q outputs to become the “inverted” outputs wi th respect
to the REF input. By selecting which output is connect to FB,
it is possible to have 2 inverted and 6 non-inverted outputs or
6 inverted and 2 non-inverted outputs. The correct configura­tion would be determined by the need for more (or fewer) in­verted outputs. 1Q, 2Q, and 3Q outputs can also be skewed
to compensate for varying trace delays independent of inver­sion on 4Q.

REF

FB
REF
FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

TEST

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

40 MHz

20 MHz

80 MHz

7B9911V–12

20 MHz

Figure 5. Frequency Multiplier with Skew Connections

Figure 5 illust rate s the LVPSCB configured as a clock mult ipli­er. The 3Q0 output is programmed to divide by four and is fed
back to FB. Th is ca uses t he PL L to i nc rease i ts f requenc y u ntil
the 3Q0 and 3Q 1 outputs are locked at 20 MHz whi le the 1Qx
and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 out puts are
program med to divide b y two , which resul ts in a 40-MHz wav e­form at these out puts. Note that the 20- and 40-MHz cl ocks f all

simultaneousl y and are out of phase on their risi ng edge. Thi s
will allow the designer to use the rising edges of the
quency and
edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80

1

⁄

frequency outputs without concern for rising-

4

MHz and are skewed by programming their select inputs ac­cordingly. Note that the FS pin is wired for 80-MHz operation
because that is the frequency of the fastest output.

Figure 6. Frequency Divider Connect ions

Figure 6 demonstrates the LVPSCB in a clock divider applica ­tion. 2Q0 i s fed back to the FB input and programmed for zero
skew. 3Qx is programmed to divide by four. 4Qx is pro­grammed to divide by two. Note that the falling edges of the
4Qx and 3Qx outp uts ar e ali gned. This a llo ws use of t he rising
edges of the
for skew mismatch. The 1Qx outputs are programmed to zero

1

⁄

frequency and

2

1

⁄

frequency without concern

4

skew and are aligned with the 2Qx outputs. In this example,
the FS input is grounded to configure the device in the 15- to
30-MHz range since t he highest f requency outp ut is running at
20 MHz.

Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx outputs. These include in v erted outputs and
outputs that off er divi de-by-2 and divide-b y-4 timin g. An inv ert­ed output allows the system designer to clock different sub­systems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function allows
the two subsystems to each be clocked 180 degrees out of
phase, but still to be aligned within the skew spec.

The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without this f e ature , an e x ternal di vider would need to be add ­ed, and the propagation delay of the divider would add to the
skew between the differen t cl ock signals.

These divided outputs, coupled with the Phase Locked Loop,
allow the LVPSCB to multiply the clock rate at the REF input
by either two or four. This mode will enable the designer to
distribute a low-frequency clock between various portions of
the system, and then locally multiply the clock rate to a more
suitable frequency, while still maintain ing the lo w-ske w charac ­teristics of t he clo ck dri ver. The L VPSCB c an perform all of t he
functions des cribed above at the same time. It can multiply by
two and four or divide by two (and four) at the same time that
it is shifting its outputs over a wide range or maintaining zero
skew between selected outputs .

9

1

⁄

fre-

2

CY7B9911V

3.3V Rob oC lock+

27.5-MHz

DISTRIBUTION

CLOCK

SYSTEM
CLOCK

FB
REF

FS
4F0

4F1
3F0

3F1
2F0

2F1
1F0

1F1
TEST

FB
REF

FS
4F0

4F1
3F0

3F1
2F0

2F1
1F0

1F1
TEST

REF

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

110-MHz

SKEWED –2.273 ns (–4tU)

Figure 7. Multi-Function Clock Driver

REF

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

L4

110-MHz

INVERTED

27.5-MHz

110-MHz

ZERO SKEW

L1

L2

L3

Z

0

Z

FB
REF
FS
4F0

4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST

LOAD

0

LOAD

Z

0

LOAD

Z

0

LOAD

Z

0

7B9911V–14

LOAD

Z

0

LOAD

Z

0

LOAD

Z

0

4Q0
4Q1

3Q0
3Q1
2Q0
2Q1

1Q0
1Q1

LOAD

LOAD

Figure 8. Board-to-Board Clock Distribution

Figure 8 shows the CY7B9911V connected in series to con­struct a zero-sk e w cloc k distrib ut ion tree betw een boar ds. De­lays of the downstream clock buffers can be programmed to
compensate for the wire length (i.e., select negative skew
equal to t he wire del ay) necessary to c onnect them to the mas-

7B9911V–15

ter clock source, approximating a zero-delay clock tree. Cas­caded clock buffers will accumulate low-frequency jitter be­cause of the non-ideal fi ltering char acte risti cs of the PLL filt er.
It is recommended that not more than two clock buffers be
connected in series.

10

CY7B9911V

3.3V RoboClock+

Ordering Information

Accuracy

(ps)

Ordering Code

500 CY7B9911V–5JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
700 CY7B9911V–7JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

Document #: 38-00765-B

Package Diagram

Package

Name

Package Type

32-Lead Plastic Leaded Chip Carrier J65

Operating

Range

51-85002-B

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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