Datasheet CY62256VL-70RZC, CY62256VL-55ZC, CY62256VL-55SNC, CY62256VL-55RZC, CY62256V-70ZC Datasheet (Cypress Semiconductor)
...
32K x 8 Static RAM
fax id: 1069
CY62256V
PRELIMINARY
1CY62256V
Features
LOW output enable (OE
) and three-state drivers. This device
has an automatic power-down feature, reducing the power
• 55, 70 ns access time
• CMOS for optimum speed/power
• Wide voltage range: 2.7V−3.6V
• Low active power (70 ns, LL version)
—108 mW (max.)
• Low standby power (70 ns, LL version)
—18 µW (max.)
• Easy memory expansion with CE
and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY62256V is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
) and active
consumption by 98% when deselected. The CY62256V is in
the standard 450-mil-wid e (300-mil b ody width) SOI C, TSOP,
and reverse TSOP packages.
An active LOW write enable signal (WE
ing/reading operation of the memory . When CE
are both LOW, data on the eight data input/output pins (I/O
throug h I /O7) is written into the memory location addressed by
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE
and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins is present on t he eight data input/output pins.
The input/output pins remain in a high-impedance state unle ss
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH. A die coat is used to ensure alpha immunity.
Logic Block Dia gram Pin Configurations
SOIC
Top View
A
1
5
A
2
6
A
3
7
A
4
8
A
5
9
A
6
10
A
7
11
A
8
A
A
I/O
I/O
I/O
GND
12
9
13
10
14
11
0
12
1
13
2
14
CE
WE
OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUT BUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
512x512
Y
ARRA
COLUMN
DECODER
POWER
DOWN
) controls the writ-
and WE inputs
through A14).
0
V
28
CC
27
WE
26
A
4
A
25
3
24
A
2
23
A
1
22
OE
A
21
0
20
CE
19
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
C62256V–2
18
17
16
15
0
C62256V–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1996 – Revised May 1996
Pin Configurations (continued)
22
OE
A
23
1
A
24
2
A
25
3
A
26
4
CC
A
A
A7
A
A
A
A
A7
A
A
CC
A
A
A
A
OE
27
28
1
5
2
6
3
4
8
5
9
6
10
7
11
7
11
6
10
5
9
4
8
3
2
6
1
5
28
27
26
4
25
3
24
2
23
1
22
WE
V
A
A
A
A
V
WE
PRELIMINARY
TSOP
Top View
TSOP Reversed
Top View
21
20
19
18
17
16
15
14
13
12
11
10
9
8
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C62256V–3
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
C62256V–4
CY62256V
Selection G uide
CY62256V-55 CY62256V-70
Maximum Access Time (ns) 55 70
Maximum Operati ng Current (mA) 50 50
L 50 50
LL 30 30
Maximum Standby Current (µA) 500 500
L 50 50
LL 5 5
Shaded area contains advanced information.
[1]
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).............. ......................... ..........− 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... −0.5V to VCC + 0.5V
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
Note:
1. V
(min.) = −2.0V for pulse durations of less than 20 ns.
IL
..... .................... ........... −0.5V to VCC + 0.5V
CC
2
PRELIMINARY
3.0V
3V
OUTPUT
1.1k
Ω
R2
1.55kΩ
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
OUTPUT 1.75V
Equivalent to: THÉ VENINEQUIVALENT
ALL INPUT PULSES
C62256V–5
C62256V–6
643Ω
CY62256V
Electrical Characteristics Over the Operating Range
CY62256V-55 CY62256V-70
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Shaded area contains advanced information.
Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
Input LOW Voltage −0.5 0.8 −0.5 0.8 V
Input Load Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output
−1 +1 −1 +1 µA
−5 +5 −5 +5 µA
Disabled
Output Short Circuit
[2]
Current
VCC Operating Supply
Current
Automatic CE
Power-Down Current—
TTL Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
VCC = Max., V
= GND −200 −200 mA
OUT
VCC = Max.,
I
= 0 mA,
OUT
f = f
= 1/t
MAX
RC
Max. VCC, CE > VIH,
V
> VIH or
IN
V
< VIL, f = f
IN
MAX
Max. VCC,
CE
> VCC - 0.3V
V
> VCC - 0.3V
IN
or V
< 0.3V, f = 0
IN
50 50 mA
L 50 50 mA
LL 30 30 mA
5 5 mA
L 3 3 mA
LL 1 1 mA
500 500 µA
L 50 50 µA
LL 5 5 µA
V
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.0V
CC
Output Capacitance 8 pF
6 pF
3
PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions
V
DR
I
CCDR
[3]
t
CDR
[3]
t
R
Data Retention Waveform
V
CC
CE
VCC for Data Ret ention 2.0 V
Data Retention Current VCC = VDR = 3.0V ,
CE
L 20 µ A
LL 5 µA
> VCC - 0.3V ,
V
> VCC - 0.3V or
IN
V
< 0.3 V
IN
Chip Deselect to Data
Retention Time
Operation Recovery Time t
DATA RETENTION MOD E
VDR> 2V
t
CDR
CY62256V
[4]
Min. Max. Unit
200 µA
0 ns
RC
3.0V3.0V
t
R
ns
C62256V–7
Switching Characteristics Over the Operating Range
[5]
CY62256V-55 CY62256V- 70
Parameter Descripti on Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Shaded area contains advanced information.
Notes:
4. No input may exceed V
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
and 100-pF load c apacita nce.
OL/IOH
6. At any given temperature and voltage condition, t
7. t
HZOE
, t
HZCE
, and t
Read Cycle Time 55 70 ns
Address to Data Val id 55 70 ns
Data Hold from Address Change 3 3 ns
CE LOW to Data Valid 55 70 ns
OE LOW to Data Valid 25 35 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[6]
[6, 7]
[6]
[6, 7]
3 3 ns
20 25 ns
3 3 ns
20 25 ns
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 55 70 ns
+0.3V.
CC
is less than t
are specified with CL = 5 pF as in p art (b) of AC Test Loads. T rans ition is measur ed ±500 mV f rom st eady-stat e voltage.
HZWE
HZCE
LZCE
, t
HZOE
is less tha n t
LZOE
, and t
HZWE
is less than t
for any given dev ice.
LZWE
4
PRELIMINARY
CY62256V
Switching Characteristics Over the Operating Range
[5]
(continued)
CY62256V-55 CY62256V- 70
Parameter Descripti on Min. Max. Min. Max. Unit
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Shaded area contains advanced information.
[8,9]
Write Cycle Time 55 70 ns
CE LOW to Write End 45 60 ns
Address Set-Up to Write End 45 60 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 40 50 ns
Data Set-Up to Write End 25 30 ns
Data Hold from Write End 0 0 ns
WE LOW to High Z
WE HIGH to Low Z
[6, 7]
[6]
20 25 ns
3 3 ns
Switching Waveforms
Read Cycle No.1
[10, 11]
t
RC
ADDRESS
t
OHA
[10, 11][10, 11]
t
AA
DATA OUT PREVIOUS DATA VALID
Read Cycle No. 2
CE
[11, 12]
t
ACE
t
RC
OE
t
DOE
t
t
LZCE
, CE = VIL.
LZOE
50%
DATA VALID
LOW and WE LOW. Both signal s must be LOW to initiate a write and eith er signal can ter minate
and tSD.
HZWE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
PU
CURRENT
Notes:
8. The internal write time of the memory is defined by the overlap of CE
a write by going HIGH. The data i np ut set-up and hol d timing shoul d be refe renced to the rising ed ge of the s ignal t hat te rminat es the w rite.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
10. Device is co ntinuously selected. OE
11. WE
is HIGH for r ead cycle.
12. Address valid prior to or coincident with CE transition LOW.
DATA VALID
t
HZOE
t
HZCE
t
C62256V–8
HIGH
IMPEDANCE
PD
ICC
50%
ISB
C62256V–9
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)
ADDRESS
CE
[8, 13, 14]
t
CY62256V
WC
t
WE
SA
OE
DATA I/O
NOTE 15
t
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
DATA I/O
HZOE
[8, 13, 14]
t
SA
t
AW
t
PWE
t
SD
t
HA
t
HD
DATAINVALID
C62256V–10
t
WC
t
SCE
t
AW
t
SD
t
HA
t
HD
DATAINVALID
C62256V–11
Write Cycle No. 3 (WE Controlled, OE LOW)
[ 9, 14]
t
WC
ADDRESS
CE
t
AW
t
WE
DATA I/O
Notes:
13. Data I/O is high impedance if OE
14. If CE
15. During this period, the I/Os are in output state and input signals should not be applied.
goes HIGH simultaneously with WE HIGH, the output r emains in a high -impeda nce state.
SA
NOTE 15
= VIH.
t
HZWE
6
t
SD
DATAINVALID
t
HA
t
LZWE
t
HD
C62256V–12
PRELIMINARY
0.00
0.50
1.00
1.50
2.00
2.50
0.00 33.00
66.00
0.80
0.90
1.00
1.10
1.20
1.30
29.00 47.00 65.00
83.00
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY
VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
CYCLE FREQUENCY (MHz)
NORMALIZED I
CC
vs. CYCLE TIME
0.0
5.0
V
CC
=3.0V
T
A
=25°C
V
CC
=3.3V
T
A
=25°C
V
IN
=0.3V
T y pical DC and AC Characteristics
CY62256V
NORMALIZED SUPPLY CURRENT
vs. SUPPL Y VOLTAGE
1.40
1.20
I
CC
1.00
0.80
0.60
0.40
0.20
I
SB
VIN=3.3V
T
=25°C
A
0.00
2.70 3.00 3.30 3.60
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.40
1.30
1.20
1.10
TA=25°C
1.00
0.90
3.90
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
1.20
I
CC
1.00
0.80
0.60
=3.3V
0.40
0.20
0.00
I
SB
V
V
CC
IN
=3.3V
−55.00 40.00
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. AMBIE NT TEMPERAT URE
1.40
1.30
1.20
1.10
1.00
VCC=3.3V
0.90
135.00
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
50.00
40.00
30.00
20.00
10.00
2.00 2.25 2.50 2.75
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
10.00
8.00
6.00
4.00
2.00
V
T
CC
=25°C
A
=3.3V
3.00
0.80
2.70 3.00 3.30 3.60
SUPPLY VOLTAGE (V)
0.80
3.90
−55.00 40.00
AMBIENT TEMPERATURE (°C)
7
135.00
0.00 0.06 0.12 0.18
0.00
0.24
OUTPUT VOLTAGE (V)
PRELIMINARY
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Deselect, Ou tput Disabled Active (ICC)
Ordering Info rma tio n
Speed
(ns) Ordering Code
55 CY62256V-55SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256VL-55SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256VLL-55SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256V-55RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256VL-55RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256VLL-55RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256V-55ZC Z28 28-Lead Thin Small Outline Package
CY62256VL-55ZC Z28 28-Lead Thin Small Outline Package
CY62256VLL-55ZC Z28 28-Lead Thin Small Outline Package
70 CY62256V-70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256VL-70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256VLL-70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256V-70RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256VL-70RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256VLL-70RZC RZ28 28-Lead Reverse Thin Small Outline Package
CY62256V-70ZC Z28 28-Lead Thin Small Outline Package
CY62256VL-70ZC Z28 28-Lead Thin Small Outline Package
CY62256VLL-70ZC Z28 28-Lead Thin Small Outline Package
Shaded area contains advanced information.
Package
Name Package Type
Operating
Range
CY62256V
Document #: 38-00519
8
Package Diagrams
PRELIMINARY
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
CY62256V
28-Lead ReverseThin Small Outline Package
RZ28
9
Package Diagrams (continued)
PRELIMINARY
28-Lead Thin Small Outline Package Z28
CY62256V
© Cypress Semiconductor Corporation, 1996. The informatio n c ontained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circ uitry other than circui try embodi ed in a Cypress Semi conductor p roduct. Nor does it convey or imply any li cense under patent or other rights . Cypress Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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