Cypress Semiconductor CY62256VL-70RZC, CY62256VL-55ZC, CY62256VL-55SNC, CY62256VL-55RZC, CY62256V-70ZC Datasheet
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32K x 8 Static RAM
fax id: 1069
CY62256V
PRELIMINARY
1CY62256V
Features
LOW output enable (OE
) and three-state drivers. This device
has an automatic power-down feature, reducing the power
• 55, 70 ns access time
• CMOS for optimum speed/power
• Wide voltage range: 2.7V−3.6V
• Low active power (70 ns, LL version)
—108 mW (max.)
• Low standby power (70 ns, LL version)
—18 µW (max.)
• Easy memory expansion with CE
and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY62256V is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
) and active
consumption by 98% when deselected. The CY62256V is in
the standard 450-mil-wid e (300-mil b ody width) SOI C, TSOP,
and reverse TSOP packages.
An active LOW write enable signal (WE
ing/reading operation of the memory . When CE
are both LOW, data on the eight data input/output pins (I/O
throug h I /O7) is written into the memory location addressed by
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE
and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins is present on t he eight data input/output pins.
The input/output pins remain in a high-impedance state unle ss
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH. A die coat is used to ensure alpha immunity.
Logic Block Dia gram Pin Configurations
SOIC
Top View
A
1
5
A
2
6
A
3
7
A
4
8
A
5
9
A
6
10
A
7
11
A
8
A
A
I/O
I/O
I/O
GND
12
9
13
10
14
11
0
12
1
13
2
14
CE
WE
OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUT BUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
512x512
Y
ARRA
COLUMN
DECODER
POWER
DOWN
) controls the writ-
and WE inputs
through A14).
0
V
28
CC
27
WE
26
A
4
A
25
3
24
A
2
23
A
1
22
OE
A
21
0
20
CE
19
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
C62256V–2
18
17
16
15
0
C62256V–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1996 – Revised May 1996
Pin Configurations (continued)
22
OE
A
23
1
A
24
2
A
25
3
A
26
4
CC
A
A
A7
A
A
A
A
A7
A
A
CC
A
A
A
A
OE
27
28
1
5
2
6
3
4
8
5
9
6
10
7
11
7
11
6
10
5
9
4
8
3
2
6
1
5
28
27
26
4
25
3
24
2
23
1
22
WE
V
A
A
A
A
V
WE
PRELIMINARY
TSOP
Top View
TSOP Reversed
Top View
21
20
19
18
17
16
15
14
13
12
11
10
9
8
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C62256V–3
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
C62256V–4
CY62256V
Selection G uide
CY62256V-55 CY62256V-70
Maximum Access Time (ns) 55 70
Maximum Operati ng Current (mA) 50 50
L 50 50
LL 30 30
Maximum Standby Current (µA) 500 500
L 50 50
LL 5 5
Shaded area contains advanced information.
[1]
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).............. ......................... ..........− 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... −0.5V to VCC + 0.5V
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 2.7V to 3.6V
Note:
1. V
(min.) = −2.0V for pulse durations of less than 20 ns.
IL
..... .................... ........... −0.5V to VCC + 0.5V
CC
2
PRELIMINARY
3.0V
3V
OUTPUT
1.1k
Ω
R2
1.55kΩ
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
OUTPUT 1.75V
Equivalent to: THÉ VENINEQUIVALENT
ALL INPUT PULSES
C62256V–5
C62256V–6
643Ω
CY62256V
Electrical Characteristics Over the Operating Range
CY62256V-55 CY62256V-70
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Shaded area contains advanced information.
Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
Input LOW Voltage −0.5 0.8 −0.5 0.8 V
Input Load Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output
−1 +1 −1 +1 µA
−5 +5 −5 +5 µA
Disabled
Output Short Circuit
[2]
Current
VCC Operating Supply
Current
Automatic CE
Power-Down Current—
TTL Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
VCC = Max., V
= GND −200 −200 mA
OUT
VCC = Max.,
I
= 0 mA,
OUT
f = f
= 1/t
MAX
RC
Max. VCC, CE > VIH,
V
> VIH or
IN
V
< VIL, f = f
IN
MAX
Max. VCC,
CE
> VCC - 0.3V
V
> VCC - 0.3V
IN
or V
< 0.3V, f = 0
IN
50 50 mA
L 50 50 mA
LL 30 30 mA
5 5 mA
L 3 3 mA
LL 1 1 mA
500 500 µA
L 50 50 µA
LL 5 5 µA
V
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.0V
CC
Output Capacitance 8 pF
6 pF
3
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