CY62157EV30 MoBL
®
8-Mbit (512K x 16) Static RAM
Features
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
• High speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
Functional Description
[1]
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE
HIGH or CE2 LOW or both BHE and BLE are HIGH). The input
or output pins (IO
impedance state when:
through IO15) are placed in a high
0
• Deselected (CE1HIGH or CE2 LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE1 LOW, CE2 HIGH and WE
LOW)
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from IO pins (IO0 through IO7) is
LOW and CE
1
written into the location specified on the address pins (A
through A18). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO
specified on the address pins (A
through IO15) is written into the location
8
through A18).
0
To read from the device, take Chip Enable (CE1 LOW and CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO
Table” on page 10 for a complete description of read and write
to IO15. See the “Truth
8
modes.
1
2
0
2
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
A
A
A
A
A
A
6
5
4
3
2
1
0
ROW DECODER
512K × 16 / 1M x 8
RAM Array
SENSE AMPS
–IO
IO
0
IO8–IO
7
15
COLUMN DECODER
CE
2
CE
Power Down
Circuit
Notes
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
1
BHE
BLE
11
A
A12A13A14A
15
16
17
18
A
A
A
BYTE
BHE
WE
OE
BLE
CE
CE
2
1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05445 Rev. *E Revised May 07, 2007
[+] Feedback
CY62157EV30 MoBL
Product Portfolio
Power Dissipation
V
Range (V)
Product Range
CC
Min Typ
[2]
Max Typ
CY62157EV30LL Ind’l/Auto-A 2.2V 3.0 3.6 45 1.8 3 18 25 2 8
Pin Configuration
The following pictures show the 44-pin TSOP II and 48-pin TSOP I pinouts.
Speed
(ns)
Operating ICC, (mA)
f = 1MHz f = f
[2]
Max Typ
[3, 4, 5]
max
[2]
Standby, I
Max Typ
(µA)
[2]
SB2
Max
®
44-Pin TSOP II
A
4
A
3
A
2
A
1
A
0
CE
IO
0
IO
1
IO
2
IO
10
3
V
11
CC
V
12
SS
IO
13
4
IO
14
5
IO
15
6
IO
16
7
WE
17
A
18
18
A
19
17
A
20
16
A
21
15
A
22
14
Top View
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
15
IO
14
IO
13
IO
12
V
SS
V
CC
IO
11
IO
10
IO
9
IO
8
A
8
A
9
A
10
A
11
A
12
A
13
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-Pin TSOP I (512K x 16 / 1M x 8)
Top V iew
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
A16
47
BYTE
46
Vss
45
IO15/A19
44
IO7
43
IO14
42
IO6
41
IO13
40
IO5
39
IO12
38
IO4
37
Vcc
36
IO11
35
IO3
34
IO10
33
IO2
32
IO9
31
IO1
30
IO8
29
IO0
28
OE
27
Vss
26
CE1
25
A0
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
3. NC pins are not connected on the die.
4. The 44-TSOP II package has only one chip enable (CE
5. The BYTE
SRAM by tying the BYTE
pin in the 48-TSOP I package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).
Document #: 38-05445 Rev. *E Page 2 of 14
) pin.
CC
= V
CC(typ)
, TA = 25°C.
[+] Feedback
Pin Configuration (continued)
The following picture shows the 48-ball VFBGA pinout.
1
2
OE
BLE
IO
BHE
8
[3, 4, 5]
48-Ball VFBGA
Top V iew
3
4
A
A
1
0
A
A
3
4
A
CE
CY62157EV30 MoBL
5
6
CE
2
IO
1
A
2
B
0
®
IO
IO
IO
V
V
A
SS
CC
A
9
IO
IO
IO
14
NC
15
18
5
10
A
11
17
NC
12
A
13
14
A
12
A
A
8
9
A
IO
IO
6
1
IO
IO
IO
WE
A
V
3
V
4
5
11
A
7
A
16
A
15
A
13
A
10
IO
CC
IO
IO
NC
SS
C
2
D
E
F
6
G
7
H
Document #: 38-05445 Rev. *E Page 3 of 14
[+] Feedback
CY62157EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Supply Voltage to Ground
Potential ................................–0.3V to 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[6, 7]
................–0.3V to 3.9V (V
CCmax
CCmax
+ 0.3V)
+ 0.3V)
Device Range
CY62157EV30LL Ind’l/Auto-A –40°C to +85 °C 2.20V to
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
[9]
I
SB2
Capacitance
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
= 2.7V to 3.6V 2.2 V
V
CC
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
V
Operating Supply Current f = f
CC
= 1/t
max
RC
f = 1 MHz 1.8 3
VCC = V
I
= 0 mA
OUT
CMOS levels
Automatic CE Power Down
Current — CMOS Inputs
Automatic CE Power Down
Current — CMOS Inputs
[10]
> V
CE
1
V
>
IN
f = f
max
f = 0 (OE
CE
1
V
> VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
IN
− 0.2V, CE2 < 0.2V
CC
V
– 0.2V, V
CC
< 0.2V)
IN
(Address and Data Only),
, BHE, BLE and WE), V
> VCC – 0.2V or CE2 < 0.2V,
CCmax
CC
[6, 7]
= 3.60V
........... –0.3V to 3.9V (V
Ambient
Temperature
45 ns (Ind’l/Auto-A)
Min Typ
[2]
–1 +1 µA
18 25
28µA
28µA
CC max
V
Max
+ 0.3 V
CC
+ 0.3 V
CC
+ 0.3V)
CC
3.60V
[8]
Unit
mA
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes
6. V
7. V
8. Full device AC operation assumes a 100 µs ramp time from 0 to V
9. Only chip enables (CE
10. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V
IH(max)
inputs can be left floating.
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
+ 0.75V for pulse durations less than 20 ns.
CC
and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the I
1
Document #: 38-05445 Rev. *E Page 4 of 14
10 pF
V
= V
CC
CC(typ)
(min) and 200 µs wait time after V
cc
stabilization.
CC
SB2
/ I
CCDR
spec. Other
[+] Feedback
CY62157EV30 MoBL
®
Thermal Resistance
[10]
Parameter Description Test Conditions BGA TSOP I TSOP II Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
72 74.88 76.88 °C/W
8.86 8.6 13.52 °C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
Rise Time = 1 V/ns
R2
VCC
GND
10%
INCLUDING
JIG AND
Equivalent to: THÉ VENIN EQUIVALENT
SCOPE
Parameters 2.5V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
R
TH
OUTPUT V
TH
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[11]
t
R
Data Retention Waveform
BHE.BLE
VCC for Data Retention 1.5 V
[9]
Data Retention Current
= 1.5V, CE1 > VCC – 0.2V,
V
CC
Ind’l/Auto-A 2 5 µA
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
[10]
Chip Deselect to Data
0ns
Retention Time
Operation Recovery Time t
[12]
RC
Figure 2. Data Retention Waveform
DATA RETENTION MODE
V
CC
CE1 or
CE
V
CC(min)
t
CDR
or
2
VDR
>
1.5V
V
CC(min)
t
R
[2]
Max Unit
ns
Notes
11. Full device operation requires linear V
12. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
ramp from V
CC
Document #: 38-05445 Rev. *E Page 5 of 14
DR
to V
> 100 µs or stable at V
CC(min)
CC(min)
> 100 µs.
[+] Feedback
CY62157EV30 MoBL
®
Switching Characteristics
Over the Operating Range
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[18]
[13, 14]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 45 ns
OE LOW to Data Valid 22 ns
OE LOW to LOW-Z
OE HIGH to High-Z
[15]
[15, 16]
CE1 LOW and CE2 HIGH to Low-Z
CE1 HIGH and CE2 LOW to High-Z
CE1 LOW and CE2 HIGH to Power Up 0 ns
CE1 HIGH and CE2 LOW to Power Down 45 ns
BLE/BHE LOW to Data Valid 45 ns
BLE/BHE LOW to Low-Z
BLE/BHE HIGH to HIGH-Z
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH to Write End 35 ns
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
BLE/BHE LOW to Write End 35 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[15, 16]
[15]
[15, 17]
[15, 16]
[15]
[15, 16]
45 ns (Ind’l/Auto-A)
Min Max
Unit
5ns
18 ns
10 ns
18 ns
5ns
18 ns
18 ns
10 ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
levels of 0 to V
14. AC timing parameters are subject to byte enable signals (BHE
15. At any temperature and voltage condition, t
, t
16. t
HZOE
17. If both byte enables are toggled together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE
HZCE
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
CC(typ)
, t
HZBE
, and t
transitions are measured when the outputs enter a high-impedance state.
HZWE
HZCE
Document #: 38-05445 Rev. *E Page 6 of 14
is less than t
/2, input pulse
CC(typ)
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
, t
LZCE
is less than t
HZBE
, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
for any device.
LZWE
[+] Feedback
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[19, 20]
Figure 3. Read Cycle No. 1
t
RC
RC
t
AA
CY62157EV30 MoBL
®
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
1
CE
2
BHE/BLE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[20, 21]
t
LZBE
t
ACE
t
LZOE
Figure 4. Read Cycle No. 2
t
RC
t
DBE
t
DOE
50%
DATA VALID
t
HZOE
t
HZBE
t
HZCE
t
PD
HIGH
IMPEDANCE
I
CC
50%
I
SB
Notes
19. The device is continuously selected. OE
20. WE
is HIGH for read cycle.
21. Address valid before or similar to CE
, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
, BHE, BLE transition LOW and CE2 transition HIGH.
1
Document #: 38-05445 Rev. *E Page 7 of 14
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
ADDRESS
CE
1
CE
2
[18, 22, 23]
Figure 5. Write Cycle No. 1
t
WC
t
SCE
CY62157EV30 MoBL
®
t
WE
SA
BHE/BLE
OE
DATA IO
NOTE 24
t
HZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)
ADDRESS
CE
1
CE
2
WE
t
AW
[18, 22, 23]
Figure 6. Write Cycle No. 1
t
WC
t
SA
t
AW
t
PWE
t
BW
t
SD
VAL I D DATA
t
PWE
t
SCE
t
HA
t
HD
t
HA
BHE/BLE
OE
DATA IO
Notes
22. Data IO is high impedance if OE
23. If CE
goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
1
24. During this period, the IOs are in output state. Do not apply input signals.
NOTE 24
= VIH.
t
HZOE
Document #: 38-05445 Rev. *E Page 8 of 14
t
BW
t
SD
VALID DATA
t
HD
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
BHE
/BLE
[23]
Figure 7. Write Cycle No. 3
t
WC
t
SCE
t
BW
CY62157EV30 MoBL
®
t
SA
WE
DATA IO
NOTE 24
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
Figure 8. Write Cycle No. 4
ADDRESS
CE
1
CE
2
/BLE
BHE
[23]
t
AW
t
PWE
t
SD
t
HA
t
HD
VAL I D DATA
t
LZWE
t
WC
t
SCE
t
AW
t
BW
t
HA
t
SA
WE
DATA IO
NOTE 24
Document #: 38-05445 Rev. *E Page 9 of 14
t
PWE
t
SD
VAL I D DATA
t
HD
[+] Feedback
Truth Table
CY62157EV30 MoBL
®
CE
CE
1
H X X X X X High-Z Deselect/Power Down Standby (ISB)
X L X X X X High-Z Deselect/Power Down Standby (ISB)
X X X X H H High-Z Deselect/Power Down Standby (ISB)
L H H L L L Data Out (IO0–IO15) Read Active (ICC)
L H H L H L Data Out (IO0–IO7);
L H H L L H High-Z (IO0–IO7);
L H H H L H High-Z Output Disabled Active (ICC)
L H H H H L High-Z Output Disabled Active (ICC)
L H H H L L High-Z Output Disabled Active (ICC)
L H L X L L Data In (IO0–IO15) Write Active (ICC)
L H L X H L Data In (IO0–IO7);
L H L X L H High-Z (IO0–IO7);
WE OE BHE BLE Inputs/Outputs Mode Power
2
High-Z (IO
Data Out (IO
High-Z (IO
Data In (IO
–IO15)
8
–IO15)
8
–IO15)
8
–IO15)
8
Read Active (ICC)
Read Active (ICC)
Write Active (ICC)
Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
45 CY62157EV30LL-45BVI 51-85150 48-ball Very Fine Pitch Ball Grid Array Industrial
CY62157EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62157EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
CY62157EV30LL-45ZXI 51-85183 48-pin Thin Small Outline Package Type I (Pb-free)
45 CY62157EV30LL-45BVXA 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Automotive-A
CY62157EV30LL-45ZSXA 51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Package
Diagram
Package Type
Operating
Range
Document #: 38-05445 Rev. *E Page 10 of 14
[+] Feedback
Package Diagrams
Figure 9. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150
CY62157EV30 MoBL
®
0.25 C
8.00±0.10
A
0.55 MAX.
0.26 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
A
B
SEATING PLANE
C
6.00±0.10
0.21±0.05
0.10 C
0.75
5.25
8.00±0.10
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
6.00±0.10
3.75
A1 CORNER
234
1
A
B
C
D
E
F
G
H
51-85150-*D
1.00 MAX
Document #: 38-05445 Rev. *E Page 11 of 14
[+] Feedback
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
CY62157EV30 MoBL
®
51-85087-*A
Document #: 38-05445 Rev. *E Page 12 of 14
[+] Feedback
Package Diagrams (continued)
Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN.
JEDEC # MO-142
1
MAX.
CY62157EV30 MoBL
0.037[0.95]
0.041[1.05]
N
0.020[0.50]
TYP.
®
0.004[0.10]
0.008[0.21]
0°-5°
0.724 [18.40]
0.787[20.00]
0.020[0.50]
0.028[0.70]
0.472[12.00]
0.010[0.25]
GAUGE PLANE
0.047[1.20]
MAX.
SEATING PLANE
0.002[0.05]
0.006[0.15]
0.004[0.10]
0.007[0.17]
0.011[0.27]
51-85183-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05445 Rev. *E Page 13 of 14
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62157EV30 MoBL
Document History Page
Document Title: CY62157EV30 MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05445
REV. ECN NO. Issue Date
** 202940 See ECN AJU New Data Sheet
*A 291272 See ECN SYT Converted from Advance Information to Preliminary
*B 444306 See ECN NXR Converted from Preliminary to Final.
*C 467052 See ECN NXR Modified Data sheet to include x8 configurability.
*D 925501 See ECN VKN Removed Automotive-E information
*E 1045801 See ECN VKN Converted Automotive-A specs from preliminary to final
Orig. of
Change Description of Change
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE
Changed V
Changed I
Changed t
Changed t
Changed t
and 45 ns Speed Bins respectively
Changed t
Bins respectively
Changed t
Speed Bins respectively
stabilization time in footnote #7 from 100 µs to 200 µs
CC
from 4 to 4.5 µA
CCDR
from 6 to 10 ns for both 35 and 45 ns Speed Bins
OHA
from 15 to 18 ns for 35 ns Speed Bin
DOE
, t
HZOE
HZCE
, tAW and t
SCE
and t
HZBE
from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed
Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
respectively
Added Lead-Free Package Information
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the I
mA to 25 mA for test condition f = fax = 1/t
Changed the I
Changed the I
0.9 µA to 2 µA respectively.
Modified ISB
Updated Thermal Resistance table.
Typ value from 16 mA to 18 mA and I
CC
Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
CC
and I
SB1
test condition to include BHE, BLE
1
SB2
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for I
Changed the I
Corrected t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Added footnote #15
in Data Retention Characteristics from 100 µs to t
R
LZOE
LZCE
HZCE
LZBE
PWE
from 22 to 25
SD
LZWE
CCDR .
Max value from 4.5 µA to 5 µA
CCDR
from 3 to 5
from 6 to 10
from 22 to 18
from 6 to 5
from 30 to 35
from 6 to 10
Updated the ordering Information and replaced the Package Name column
with Package Diagram.
Updated the Ordering Information table
Added Preliminary Automotive-A information
Added footnote #10 related to I
Added footnote #15 related AC timing parameters
Updated footnote #9
from 12 and 15 ns to 15 and 18 ns for 35
HZWE
from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns
BW
RC.
Max value from 4.5 µA to 8 µA and Typ value from
and I
SB2
CCDR
on Page # 2
Max value from 28
CC
ns.
RC
®
Document #: 38-05445 Rev. *E Page 14 of 14
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