CY62157E MoBL
®
8-Mbit (512K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Functional Description
[1]
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
, CE2 and OE features
1
®
) in
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE
HIGH). The input/output pins (IO
a high-impedance state when: deselected (CE
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE
or during a write operation (CE
LOW).
HIGH or CE2 LOW or both BHE and BLE are
1
through IO15) are placed in
0
HIGH or CE
1
, BLE HIGH),
LOW, CE2 HIGH and WE
1
Writing to the device is accomplished by taking Chip Enable
LOW and CE2 HIGH) and Write Enable (WE) input LOW.
(CE
1
If Byte Low Enable (BLE
) is LOW, then data from IO pins (IO
through IO7), is written into the location specified on the
address pins (A
LOW, then data from IO pins (IO
the location specified on the address pins (A
through A18). If Byte High Enable (BHE) is
0
through IO15) is written into
8
through A18).
0
Reading from the device is accomplished by taking Chip
Enable (CE
LOW while forcing the Write Enable (WE
Enable (BLE
specified by the address pins will appear on IO
High Enable (BHE
on IO
8
for a complete description of read and write modes.
LOW and CE2 HIGH) and Output Enable (OE)
1
) HIGH. If Byte Low
) is LOW, then data from the memory location
to IO7. If Byte
) is LOW, then data from memory will appear
0
to IO15. See the truth table at the back of this data sheet
2
0
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
ROW DECODER
512K x 16
RAM Array
COLUMN DECODER
13
15
A11A12A
14
A
A
POWER-DOWN
CIRCUIT
A
IO
–IO
0
7
BHE
BLE
IO8–IO
15
BHE
WE
OE
BLE
CE
CE
2
1
SENSE AMPS
18
16
17
A
A
CE
CE
2
1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05695 Rev. *C Revised November 21, 2006
[+] Feedback
CY62157E MoBL
®
Pin Configuration
[2, 3]
A
A
A
A
A
CE
IO
IO
IO
IO
V
CC
V
SS
IO
IO
IO
IO
WE
A
A
A
A
A
18
17
16
15
14
4
3
2
1
0
0
1
2
3
4
5
6
7
TSOP II
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
15
IO
14
IO
13
IO
12
V
SS
V
CC
IO
11
IO
10
IO
9
IO
8
A
8
A
9
A
10
A
11
A
12
A
13
1
BLE
IO
IO
V
SS
V
CC
IO
IO
A
VFBGA
Top View
2
OE
BHE
8
IO
10
9
IO
11
NC
IO
12
IO
13
14
NC
15
A
8
18
4
3
A
0
A
3
A
5
A
17
A
14
A
12
A
9
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
IO
IO
IO
IO
WE
A
CE
2
2
IO
1
IO
1
Vcc
3
Vss
4
IO
5
IO
NC
11
A
B
0
C
2
D
E
F
6
G
7
H
Product Portfolio
Power Dissipation
Operating I
[4]
Max Typ
Product Range
V
Range (V)
CC
Min T yp
[4]
Max Typ
Speed
(ns)
CY62157E-45 Ind’l 4.5 5.0 5.5 45 1.8 3 18 25 2 8
CY62157E-55
Notes:
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
5. Automotive product information is Preliminary.
[5]
Auto 4.5 5.0 5.5 55 1.8 4 18 35 2 30
) pin.
CC
, (mA)
[4]
= V
CC
max
Max Typ
, TA = 25°C.
CC(typ)
Standby, I
(µA)f = 1MHz f = f
[4]
SB2
Max
Document #: 38-05695 Rev. *C Page 2 of 12
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CY62157E MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .......................................................... –0.5V to 6.0V
DC Voltage Applied to Outputs
in High Z State
[6, 7]
...........................................–0.5V to 6.0V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
I
I
OH
OL
IH
IL
IX
OZ
CC
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply
Current
I
SB1
Automatic CE
Power-Down
Current —
CMOS Inputs
I
SB2
Automatic CE
Power-Down
Current —
CMOS Inputs
Capacitance
[9]
IOH = –1 mA V
IOL = 2.1 mA V
V
= 4.5V to 5.5V 2.2 V
CC
V
= 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
CC
GND < VI < V
= 4.5V 2.4 2.4 V
CC
= 4.5V 0.4 0.4 V
CC
CC
GND < VO < VCC, Output Disabled – 1 +1 –1 +1 µA
f = f
= 1/tRCVCC = V
max
f = 1 MHz 1.8 3
CE
> V
1
CC
V
>
V
IN
CC
f = f
f = 0 (OE
V
CE
V
f = 0, V
(Address and Data Only),
max
= 3.60V
CC
> VCC – 0.2V or CE2 < 0.2V,
1
> VCC – 0.2V or VIN < 0.2V,
IN
CC
I
CMOS levels
− 0.2V, CE2 < 0.2V,
– 0.2V, V
, BHE, BLE and WE),
= 3.60V
OUT
= 0 mA
< 0.2V,
IN
CCmax
DC Input Voltage
[6, 7]
........................................–0.5V to 6.0V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ..........................................> 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ...................................................> 200 mA
Operating Range
Device Range
Temperature V
CY62157E Industrial –40°C to +85°C 4.5V to 5.5V
Automotive –40°C to +125°C
Ambient
45 ns (Industrial)
[4]
Max Min Typ
CC
+ 0.5 2.2 V
55 ns (Automotive)
[4]
Max
+ 0.5 V
CC
–1 +1 –1 +1 µA
18 25
18 35
1.8 4
28
28
2 30 µA
2 30 µA
CC
[8]
UnitMin Typ
mA
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes:
6. V
IL(min)
7. V
IH(max)
8. Full device AC operation assumes a 100 µs ramp time from 0 to V
9. Tested initially and after any design or process ch anges that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz, VCC = V
Output Capacitance 10 pF
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
= V
+ 0.75V for pulse durations less than 20 ns.
CC
Document #: 38-05695 Rev. *C Page 3 of 12
CC(typ)
(min) and 200 µs wait time after V
CC
stabilization.
CC
10 pF
[+] Feedback
CY62157E MoBL
®
Thermal Resistance
[9]
Parameter Description Test Conditions TSOP II VFBGA Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
77 72 °C/W
13 8.86 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
30 pF
JIG AND
SCOPE
R1
R2
3V
GND
10%
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT V
ALL INPUT PULSES
90%
R
TH
90%
10%
Fall Time = 1 V/ns
Parameters Values Unit
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
639 Ω
1.77 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[9]
t
CDR
[10]
t
R
Data Retention Waveform
BHE
VCC for Data Retention 2 V
Data Retention Current
Chip Deselect to Data
=2V, CE1> VCC – 0.2V,
V
CC
< 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
CE
2
Industrial 8 µA
Automotive 30
0ns
Retention Time
Operation Recovery Time t
[11]
DATA RETENTION MODE
V
V
CC
CE1or
.BLE
CC(min)
t
CDR
VDR> 2 V
V
CC(min)
RC
t
R
[4]
Max Unit
ns
CE
2
Notes:
10.Full device operation requires linear V
.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
11. BHE
ramp from V
CC
Document #: 38-05695 Rev. *C Page 4 of 12
DR
to V
> 100 µs or stable at V
CC(min)
CC(min)
> 100 µs.
[+] Feedback
CY62157E MoBL
®
Switching Characteristics Over the Operating Range
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid 45 55 ns
OE LOW to Data Valid 22 25 ns
OE LOW to LOW Z
OE HIGH to High Z
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH and CE2 LOW to High Z
[13]
[13, 14]
[13]
[13, 14]
CE1 LOW and CE2 HIGH to Power-Up 0 0 ns
CE1 HIGH and CE2 LOW to Power-Down 45 55 ns
BLE/BHE LOW to Data Valid 45 55 ns
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
[15]
[13]
[13, 14]
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End 35 40 ns
Address Set-Up to Write End
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start
WE Pulse Width 35 40 ns
BLE/BHE LOW to Write End 35 40 ns
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
[13, 14]
[13]
[12]
45 ns
55 ns
Min Max
45
55
45
10
10
5 5 ns
18 20 ns
10 10 ns
18 20 ns
10 10 ns
18 20 ns
45
35
0
25
0
55
40
0
25
0
18 20 ns
10 10 ns
55
UnitMin Max
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
12.Test conditions for all p arame ter s oth er t han Tri-state parameters assume sign al tran sit ion time of 3 ns or l ess, t iming ref erence levels of V
levels of 0 to V
13.At any given temperature and voltage condition, t
given device.
, t
14.t
HZOE
15.The internal Write time of the memory is defined by the overlap of WE
HZCE
a write and any of these signals can terminate a write by going INACTIVE. Th e dat a input set-up and hold t iming should be ref erenced to the edg e of th e signal
that terminates the Write.
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
CC(typ)
, t
HZBE
, and t
transitions are measured when the outputs enter a high-impedance state.
HZWE
Document #: 38-05695 Rev. *C Page 5 of 12
is less than t
HZCE
/2, input pulse
CC(typ)
, t
LZCE
is less than t
HZBE
, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
LZBE
, t
HZOE
is less than t
LZOE
, and t
is less than t
HZWE
LZWE
for any
[+] Feedback
Switching Waveforms
E
Read Cycle 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[16, 17]
t
AA
CY62157E MoBL
t
RC
®
Read Cycle 2 (OE Controlled)
ADDRESS
CE
1
CE
2
/BLE
BHE
OE
DATA OUT
V
CC
HIGH IMPEDANCE
t
PU
SUPPLY
CURRENT
[17, 18]
t
LZBE
t
LZCE
t
ACE
t
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZBE
t
HZOE
HIGH
50%
IMPEDANC
I
CC
I
SB
DATA VALID
Notes:
16.The device is continuously selected. OE
is HIGH for read cycle.
17.WE
18.Address valid prior to or coincident with CE
, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
, BHE, BLE transition LOW and CE2 transition HIGH.
1
Document #: 38-05695 Rev. *C Page 6 of 12
[+] Feedback
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
ADDRESS
CE
1
CE
2
[15, 19, 20, 21]
t
SCE
t
WC
CY62157E MoBL
®
t
SA
WE
BHE/BLE
OE
IO
DATA
See Note 21
t
HZOE
Write Cycle 2 (CE1 or CE2 Controlled)
ADDRESS
CE
1
CE
2
WE
[15, 19, 20, 21]
t
SA
t
t
AW
AW
t
WC
t
PWE
t
BW
t
SD
VALID DATA
t
PWE
t
SCE
t
HA
t
HD
t
HA
BHE/BLE
OE
DATAIO
Notes:
19.Data IO is high impedance if OE
goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
20.If CE
1
21.During this period, the IOs are in output state and input signals should not be applied.
See Note 21
= VIH.
t
HZOE
Document #: 38-05695 Rev. *C Page 7 of 12
t
BW
t
SD
VALID DATA
t
HD
[+] Feedback
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
BHE
/BLE
[20, 21]
t
t
SCE
BW
t
WC
CY62157E MoBL
®
t
WE
DATA IO
SA
See Note 21
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
BHE/BLE
t
SA
WE
[20, 21]
t
AW
t
AW
t
SCE
t
PWE
t
WC
t
PWE
t
BW
t
SD
VALID DATA
t
t
t
HA
HA
t
HD
LZWE
DATA IO
See Note 21
Document #: 38-05695 Rev. *C Page 8 of 12
t
SD
VALID DATA
t
HD
[+] Feedback
Truth Table
CY62157E MoBL
®
CE
CE
1
H X X X X X High Z Deselect/Power-Down Standby (ISB)
X L X X X X High Z Deselect/Power-Down Standby (ISB)
X X X X H H High Z Deselect/Power-Down Standby (ISB)
L H H L L L Data Out (IO0–IO15) Read Active (ICC)
L H H L H L Data Out (IO0–IO7);
L H H L L H High Z (IO0–IO7);
L H H H L H High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (ICC)
L H H H L L High Z Output Disabled Active (ICC)
L H L X L L Data In (IO0–IO15) Write Active (ICC)
L H L X H L Data In (IO0–IO7);
L H L X L H High Z (IO0–IO7);
WE OE BHE BLE Inputs/Outputs Mode Power
2
High Z (IO
Data Out (IO
High Z (IO
Data In (IO
8
8
–IO15)
–IO15)
8
–IO15)
–IO15)
8
Read Active (ICC)
Read Active (ICC)
Write Active (ICC)
Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
45 CY62157ELL-45ZSXI 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Industrial
55 CY62157ELL-55ZSXE 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Automotive
CY62157ELL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Package
Diagram Package Type
Operating
Range
Document #: 38-05695 Rev. *C Page 9 of 12
[+] Feedback
Package Diagrams
44-pin TSOP II (51-85087)
CY62157E MoBL
®
51-85087-*A
Document #: 38-05695 Rev. *C Page 10 of 12
[+] Feedback
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
CY62157E MoBL
®
0.25 C
8.00±0.10
A
0.55 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
B
SEATING PLANE
C
6.00±0.10
0.21±0.05
0.10 C
8.00±0.10
A
0.75
5.25
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
6.00±0.10
51-85150-*D
3.75
A1 CORNER
1
234
A
B
C
D
E
F
G
H
0.26 MAX.
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semicond uctor Corporatio n. All prod uct a nd
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05695 Rev. *C Pa ge 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch ange without notice. Cypress Semiconductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
1.00 MAX
[+] Feedback
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
REV. ECN NO. Issue Date
** 291273 See ECN PCI New data sheet
*A 457689 See ECN NXR Added Automotive Product
*B 467033 See ECN NXR Added Industrial Product (Final Information)
*C 569114 See ECN VKN Added 48 ball VFBGA package
Orig. of
Change Description of Change
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected t
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
Removed 48 ball VFBGA package and its relevant information
Changed the I
Changed the I
Modified footnote #4 to include current limit
Updated the Ordering Information table
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
in Data Retention Characteristics from 100 µs to t
R
value of Automotive from 2 mA to 1.8 mA for f = 1MHz
CC(typ)
value of Automotive from 5 µA to 1.8 µA
SB2(typ)
CY62157E MoBL
ns
RC
®
Document #: 38-05695 Rev. *C Page 12 of 12
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